drivers/iio/accel/bmc150-accel.c

   1 /*
   2  * 3-axis accelerometer driver supporting following Bosch-Sensortec chips:
   3  *  - BMC150
   4  *  - BMI055
   5  *  - BMA255
   6  *  - BMA250E
   7  *  - BMA222E
   8  *  - BMA280
   9  *
  10  * Copyright (c) 2014, Intel Corporation.
  11  *
  12  * This program is free software; you can redistribute it and/or modify it
  13  * under the terms and conditions of the GNU General Public License,
  14  * version 2, as published by the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope it will be useful, but WITHOUT
  17  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  * more details.
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/i2c.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/delay.h>
  26 #include <linux/slab.h>
  27 #include <linux/acpi.h>
  28 #include <linux/gpio/consumer.h>
  29 #include <linux/pm.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/iio/iio.h>
  32 #include <linux/iio/sysfs.h>
  33 #include <linux/iio/buffer.h>
  34 #include <linux/iio/events.h>
  35 #include <linux/iio/trigger.h>
  36 #include <linux/iio/trigger_consumer.h>
  37 #include <linux/iio/triggered_buffer.h>
  38
  39 #define BMC150_ACCEL_DRV_NAME                   "bmc150_accel"
  40 #define BMC150_ACCEL_IRQ_NAME                   "bmc150_accel_event"
  41 #define BMC150_ACCEL_GPIO_NAME                  "bmc150_accel_int"
  42
  43 #define BMC150_ACCEL_REG_CHIP_ID                0x00
  44
  45 #define BMC150_ACCEL_REG_INT_STATUS_2           0x0B
  46 #define BMC150_ACCEL_ANY_MOTION_MASK            0x07
  47 #define BMC150_ACCEL_ANY_MOTION_BIT_X           BIT(0)
  48 #define BMC150_ACCEL_ANY_MOTION_BIT_Y           BIT(1)
  49 #define BMC150_ACCEL_ANY_MOTION_BIT_Z           BIT(2)
  50 #define BMC150_ACCEL_ANY_MOTION_BIT_SIGN        BIT(3)
  51
  52 #define BMC150_ACCEL_REG_PMU_LPW                0x11
  53 #define BMC150_ACCEL_PMU_MODE_MASK              0xE0
  54 #define BMC150_ACCEL_PMU_MODE_SHIFT             5
  55 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK     0x17
  56 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT    1
  57
  58 #define BMC150_ACCEL_REG_PMU_RANGE              0x0F
  59
  60 #define BMC150_ACCEL_DEF_RANGE_2G               0x03
  61 #define BMC150_ACCEL_DEF_RANGE_4G               0x05
  62 #define BMC150_ACCEL_DEF_RANGE_8G               0x08
  63 #define BMC150_ACCEL_DEF_RANGE_16G              0x0C
  64
  65 /* Default BW: 125Hz */
  66 #define BMC150_ACCEL_REG_PMU_BW         0x10
  67 #define BMC150_ACCEL_DEF_BW                     125
  68
  69 #define BMC150_ACCEL_REG_INT_MAP_0              0x19
  70 #define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE        BIT(2)
  71
  72 #define BMC150_ACCEL_REG_INT_MAP_1              0x1A
  73 #define BMC150_ACCEL_INT_MAP_1_BIT_DATA         BIT(0)
  74 #define BMC150_ACCEL_INT_MAP_1_BIT_FWM          BIT(1)
  75 #define BMC150_ACCEL_INT_MAP_1_BIT_FFULL        BIT(2)
  76
  77 #define BMC150_ACCEL_REG_INT_RST_LATCH          0x21
  78 #define BMC150_ACCEL_INT_MODE_LATCH_RESET       0x80
  79 #define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F
  80 #define BMC150_ACCEL_INT_MODE_NON_LATCH_INT     0x00
  81
  82 #define BMC150_ACCEL_REG_INT_EN_0               0x16
  83 #define BMC150_ACCEL_INT_EN_BIT_SLP_X           BIT(0)
  84 #define BMC150_ACCEL_INT_EN_BIT_SLP_Y           BIT(1)
  85 #define BMC150_ACCEL_INT_EN_BIT_SLP_Z           BIT(2)
  86
  87 #define BMC150_ACCEL_REG_INT_EN_1               0x17
  88 #define BMC150_ACCEL_INT_EN_BIT_DATA_EN         BIT(4)
  89 #define BMC150_ACCEL_INT_EN_BIT_FFULL_EN        BIT(5)
  90 #define BMC150_ACCEL_INT_EN_BIT_FWM_EN          BIT(6)
  91
  92 #define BMC150_ACCEL_REG_INT_OUT_CTRL           0x20
  93 #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL      BIT(0)
  94
  95 #define BMC150_ACCEL_REG_INT_5                  0x27
  96 #define BMC150_ACCEL_SLOPE_DUR_MASK             0x03
  97
  98 #define BMC150_ACCEL_REG_INT_6                  0x28
  99 #define BMC150_ACCEL_SLOPE_THRES_MASK           0xFF
 100
 101 /* Slope duration in terms of number of samples */
 102 #define BMC150_ACCEL_DEF_SLOPE_DURATION         1
 103 /* in terms of multiples of g's/LSB, based on range */
 104 #define BMC150_ACCEL_DEF_SLOPE_THRESHOLD        1
 105
 106 #define BMC150_ACCEL_REG_XOUT_L         0x02
 107
 108 #define BMC150_ACCEL_MAX_STARTUP_TIME_MS        100
 109
 110 /* Sleep Duration values */
 111 #define BMC150_ACCEL_SLEEP_500_MICRO            0x05
 112 #define BMC150_ACCEL_SLEEP_1_MS         0x06
 113 #define BMC150_ACCEL_SLEEP_2_MS         0x07
 114 #define BMC150_ACCEL_SLEEP_4_MS         0x08
 115 #define BMC150_ACCEL_SLEEP_6_MS         0x09
 116 #define BMC150_ACCEL_SLEEP_10_MS                0x0A
 117 #define BMC150_ACCEL_SLEEP_25_MS                0x0B
 118 #define BMC150_ACCEL_SLEEP_50_MS                0x0C
 119 #define BMC150_ACCEL_SLEEP_100_MS               0x0D
 120 #define BMC150_ACCEL_SLEEP_500_MS               0x0E
 121 #define BMC150_ACCEL_SLEEP_1_SEC                0x0F
 122
 123 #define BMC150_ACCEL_REG_TEMP                   0x08
 124 #define BMC150_ACCEL_TEMP_CENTER_VAL            24
 125
 126 #define BMC150_ACCEL_AXIS_TO_REG(axis)  (BMC150_ACCEL_REG_XOUT_L + (axis * 2))
 127 #define BMC150_AUTO_SUSPEND_DELAY_MS            2000
 128
 129 #define BMC150_ACCEL_REG_FIFO_STATUS            0x0E
 130 #define BMC150_ACCEL_REG_FIFO_CONFIG0           0x30
 131 #define BMC150_ACCEL_REG_FIFO_CONFIG1           0x3E
 132 #define BMC150_ACCEL_REG_FIFO_DATA              0x3F
 133 #define BMC150_ACCEL_FIFO_LENGTH                32
 134
 135 enum bmc150_accel_axis {
 136         AXIS_X,
 137         AXIS_Y,
 138         AXIS_Z,
 139 };
 140
 141 enum bmc150_power_modes {
 142         BMC150_ACCEL_SLEEP_MODE_NORMAL,
 143         BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND,
 144         BMC150_ACCEL_SLEEP_MODE_LPM,
 145         BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04,
 146 };
 147
 148 struct bmc150_scale_info {
 149         int scale;
 150         u8 reg_range;
 151 };
 152
 153 struct bmc150_accel_chip_info {
 154         const char *name;
 155         u8 chip_id;
 156         const struct iio_chan_spec *channels;
 157         int num_channels;
 158         const struct bmc150_scale_info scale_table[4];
 159 };
 160
 161 struct bmc150_accel_interrupt {
 162         const struct bmc150_accel_interrupt_info *info;
 163         atomic_t users;
 164 };
 165
 166 struct bmc150_accel_trigger {
 167         struct bmc150_accel_data *data;
 168         struct iio_trigger *indio_trig;
 169         int (*setup)(struct bmc150_accel_trigger *t, bool state);
 170         int intr;
 171         bool enabled;
 172 };
 173
 174 enum bmc150_accel_interrupt_id {
 175         BMC150_ACCEL_INT_DATA_READY,
 176         BMC150_ACCEL_INT_ANY_MOTION,
 177         BMC150_ACCEL_INT_WATERMARK,
 178         BMC150_ACCEL_INTERRUPTS,
 179 };
 180
 181 enum bmc150_accel_trigger_id {
 182         BMC150_ACCEL_TRIGGER_DATA_READY,
 183         BMC150_ACCEL_TRIGGER_ANY_MOTION,
 184         BMC150_ACCEL_TRIGGERS,
 185 };
 186
 187 struct bmc150_accel_data {
 188         struct i2c_client *client;
 189         struct bmc150_accel_interrupt interrupts[BMC150_ACCEL_INTERRUPTS];
 190         atomic_t active_intr;
 191         struct bmc150_accel_trigger triggers[BMC150_ACCEL_TRIGGERS];
 192         struct mutex mutex;
 193         u8 fifo_mode, watermark;
 194         s16 buffer[8];
 195         u8 bw_bits;
 196         u32 slope_dur;
 197         u32 slope_thres;
 198         u32 range;
 199         int ev_enable_state;
 200         int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */
 201         const struct bmc150_accel_chip_info *chip_info;
 202 };
 203
 204 static const struct {
 205         int val;
 206         int val2;
 207         u8 bw_bits;
 208 } bmc150_accel_samp_freq_table[] = { {15, 620000, 0x08},
 209                                      {31, 260000, 0x09},
 210                                      {62, 500000, 0x0A},
 211                                      {125, 0, 0x0B},
 212                                      {250, 0, 0x0C},
 213                                      {500, 0, 0x0D},
 214                                      {1000, 0, 0x0E},
 215                                      {2000, 0, 0x0F} };
 216
 217 static const struct {
 218         int bw_bits;
 219         int msec;
 220 } bmc150_accel_sample_upd_time[] = { {0x08, 64},
 221                                      {0x09, 32},
 222                                      {0x0A, 16},
 223                                      {0x0B, 8},
 224                                      {0x0C, 4},
 225                                      {0x0D, 2},
 226                                      {0x0E, 1},
 227                                      {0x0F, 1} };
 228
 229 static const struct {
 230         int sleep_dur;
 231         u8 reg_value;
 232 } bmc150_accel_sleep_value_table[] = { {0, 0},
 233                                        {500, BMC150_ACCEL_SLEEP_500_MICRO},
 234                                        {1000, BMC150_ACCEL_SLEEP_1_MS},
 235                                        {2000, BMC150_ACCEL_SLEEP_2_MS},
 236                                        {4000, BMC150_ACCEL_SLEEP_4_MS},
 237                                        {6000, BMC150_ACCEL_SLEEP_6_MS},
 238                                        {10000, BMC150_ACCEL_SLEEP_10_MS},
 239                                        {25000, BMC150_ACCEL_SLEEP_25_MS},
 240                                        {50000, BMC150_ACCEL_SLEEP_50_MS},
 241                                        {100000, BMC150_ACCEL_SLEEP_100_MS},
 242                                        {500000, BMC150_ACCEL_SLEEP_500_MS},
 243                                        {1000000, BMC150_ACCEL_SLEEP_1_SEC} };
 244
 245 static int bmc150_accel_set_mode(struct bmc150_accel_data *data,
 246                                  enum bmc150_power_modes mode,
 247                                  int dur_us)
 248 {
 249         int i;
 250         int ret;
 251         u8 lpw_bits;
 252         int dur_val = -1;
 253
 254         if (dur_us > 0) {
 255                 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table);
 256                                                                          ++i) {
 257                         if (bmc150_accel_sleep_value_table[i].sleep_dur ==
 258                                                                         dur_us)
 259                                 dur_val =
 260                                 bmc150_accel_sleep_value_table[i].reg_value;
 261                 }
 262         } else {
 263                 dur_val = 0;
 264         }
 265
 266         if (dur_val < 0)
 267                 return -EINVAL;
 268
 269         lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT;
 270         lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT);
 271
 272         dev_dbg(&data->client->dev, "Set Mode bits %x\n", lpw_bits);
 273
 274         ret = i2c_smbus_write_byte_data(data->client,
 275                                         BMC150_ACCEL_REG_PMU_LPW, lpw_bits);
 276         if (ret < 0) {
 277                 dev_err(&data->client->dev, "Error writing reg_pmu_lpw\n");
 278                 return ret;
 279         }
 280
 281         return 0;
 282 }
 283
 284 static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val,
 285                                int val2)
 286 {
 287         int i;
 288         int ret;
 289
 290         for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
 291                 if (bmc150_accel_samp_freq_table[i].val == val &&
 292                     bmc150_accel_samp_freq_table[i].val2 == val2) {
 293                         ret = i2c_smbus_write_byte_data(
 294                                 data->client,
 295                                 BMC150_ACCEL_REG_PMU_BW,
 296                                 bmc150_accel_samp_freq_table[i].bw_bits);
 297                         if (ret < 0)
 298                                 return ret;
 299
 300                         data->bw_bits =
 301                                 bmc150_accel_samp_freq_table[i].bw_bits;
 302                         return 0;
 303                 }
 304         }
 305
 306         return -EINVAL;
 307 }
 308
 309 static int bmc150_accel_update_slope(struct bmc150_accel_data *data)
 310 {
 311         int ret, val;
 312
 313         ret = i2c_smbus_write_byte_data(data->client, BMC150_ACCEL_REG_INT_6,
 314                                         data->slope_thres);
 315         if (ret < 0) {
 316                 dev_err(&data->client->dev, "Error writing reg_int_6\n");
 317                 return ret;
 318         }
 319
 320         ret = i2c_smbus_read_byte_data(data->client, BMC150_ACCEL_REG_INT_5);
 321         if (ret < 0) {
 322                 dev_err(&data->client->dev, "Error reading reg_int_5\n");
 323                 return ret;
 324         }
 325
 326         val = (ret & ~BMC150_ACCEL_SLOPE_DUR_MASK) | data->slope_dur;
 327         ret = i2c_smbus_write_byte_data(data->client, BMC150_ACCEL_REG_INT_5,
 328                                         val);
 329         if (ret < 0) {
 330                 dev_err(&data->client->dev, "Error write reg_int_5\n");
 331                 return ret;
 332         }
 333
 334         dev_dbg(&data->client->dev, "%s: %x %x\n", __func__, data->slope_thres,
 335                 data->slope_dur);
 336
 337         return ret;
 338 }
 339
 340 static int bmc150_accel_any_motion_setup(struct bmc150_accel_trigger *t,
 341                                          bool state)
 342 {
 343         if (state)
 344                 return bmc150_accel_update_slope(t->data);
 345
 346         return 0;
 347 }
 348
 349 static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val,
 350                                int *val2)
 351 {
 352         int i;
 353
 354         for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
 355                 if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) {
 356                         *val = bmc150_accel_samp_freq_table[i].val;
 357                         *val2 = bmc150_accel_samp_freq_table[i].val2;
 358                         return IIO_VAL_INT_PLUS_MICRO;
 359                 }
 360         }
 361
 362         return -EINVAL;
 363 }
 364
 365 #ifdef CONFIG_PM
 366 static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data)
 367 {
 368         int i;
 369
 370         for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) {
 371                 if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits)
 372                         return bmc150_accel_sample_upd_time[i].msec;
 373         }
 374
 375         return BMC150_ACCEL_MAX_STARTUP_TIME_MS;
 376 }
 377
 378 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
 379 {
 380         int ret;
 381
 382         if (on) {
 383                 ret = pm_runtime_get_sync(&data->client->dev);
 384         } else {
 385                 pm_runtime_mark_last_busy(&data->client->dev);
 386                 ret = pm_runtime_put_autosuspend(&data->client->dev);
 387         }
 388
 389         if (ret < 0) {
 390                 dev_err(&data->client->dev,
 391                         "Failed: bmc150_accel_set_power_state for %d\n", on);
 392                 if (on)
 393                         pm_runtime_put_noidle(&data->client->dev);
 394
 395                 return ret;
 396         }
 397
 398         return 0;
 399 }
 400 #else
 401 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
 402 {
 403         return 0;
 404 }
 405 #endif
 406
 407 static const struct bmc150_accel_interrupt_info {
 408         u8 map_reg;
 409         u8 map_bitmask;
 410         u8 en_reg;
 411         u8 en_bitmask;
 412 } bmc150_accel_interrupts[BMC150_ACCEL_INTERRUPTS] = {
 413         { /* data ready interrupt */
 414                 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
 415                 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_DATA,
 416                 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
 417                 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN,
 418         },
 419         {  /* motion interrupt */
 420                 .map_reg = BMC150_ACCEL_REG_INT_MAP_0,
 421                 .map_bitmask = BMC150_ACCEL_INT_MAP_0_BIT_SLOPE,
 422                 .en_reg = BMC150_ACCEL_REG_INT_EN_0,
 423                 .en_bitmask =  BMC150_ACCEL_INT_EN_BIT_SLP_X |
 424                         BMC150_ACCEL_INT_EN_BIT_SLP_Y |
 425                         BMC150_ACCEL_INT_EN_BIT_SLP_Z
 426         },
 427         { /* fifo watermark interrupt */
 428                 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
 429                 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_FWM,
 430                 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
 431                 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN,
 432         },
 433 };
 434
 435 static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev,
 436                                           struct bmc150_accel_data *data)
 437 {
 438         int i;
 439
 440         for (i = 0; i < BMC150_ACCEL_INTERRUPTS; i++)
 441                 data->interrupts[i].info = &bmc150_accel_interrupts[i];
 442 }
 443
 444 static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i,
 445                                       bool state)
 446 {
 447         struct bmc150_accel_interrupt *intr = &data->interrupts[i];
 448         const struct bmc150_accel_interrupt_info *info = intr->info;
 449         int ret;
 450
 451         if (state) {
 452                 if (atomic_inc_return(&intr->users) > 1)
 453                         return 0;
 454         } else {
 455                 if (atomic_dec_return(&intr->users) > 0)
 456                         return 0;
 457         }
 458
 459         /*
 460          * We will expect the enable and disable to do operation in reverse
 461          * order. This will happen here anyway, as our resume operation uses
 462          * sync mode runtime pm calls. The suspend operation will be delayed
 463          * by autosuspend delay.
 464          * So the disable operation will still happen in reverse order of
 465          * enable operation. When runtime pm is disabled the mode is always on,
 466          * so sequence doesn't matter.
 467          */
 468         ret = bmc150_accel_set_power_state(data, state);
 469         if (ret < 0)
 470                 return ret;
 471
 472         /* map the interrupt to the appropriate pins */
 473         ret = i2c_smbus_read_byte_data(data->client, info->map_reg);
 474         if (ret < 0) {
 475                 dev_err(&data->client->dev, "Error reading reg_int_map\n");
 476                 goto out_fix_power_state;
 477         }
 478         if (state)
 479                 ret |= info->map_bitmask;
 480         else
 481                 ret &= ~info->map_bitmask;
 482
 483         ret = i2c_smbus_write_byte_data(data->client, info->map_reg,
 484                                         ret);
 485         if (ret < 0) {
 486                 dev_err(&data->client->dev, "Error writing reg_int_map\n");
 487                 goto out_fix_power_state;
 488         }
 489
 490         /* enable/disable the interrupt */
 491         ret = i2c_smbus_read_byte_data(data->client, info->en_reg);
 492         if (ret < 0) {
 493                 dev_err(&data->client->dev, "Error reading reg_int_en\n");
 494                 goto out_fix_power_state;
 495         }
 496
 497         if (state)
 498                 ret |= info->en_bitmask;
 499         else
 500                 ret &= ~info->en_bitmask;
 501
 502         ret = i2c_smbus_write_byte_data(data->client, info->en_reg, ret);
 503         if (ret < 0) {
 504                 dev_err(&data->client->dev, "Error writing reg_int_en\n");
 505                 goto out_fix_power_state;
 506         }
 507
 508         if (state)
 509                 atomic_inc(&data->active_intr);
 510         else
 511                 atomic_dec(&data->active_intr);
 512
 513         return 0;
 514
 515 out_fix_power_state:
 516         bmc150_accel_set_power_state(data, false);
 517         return ret;
 518 }
 519
 520 static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val)
 521 {
 522         int ret, i;
 523
 524         for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) {
 525                 if (data->chip_info->scale_table[i].scale == val) {
 526                         ret = i2c_smbus_write_byte_data(
 527                                      data->client,
 528                                      BMC150_ACCEL_REG_PMU_RANGE,
 529                                      data->chip_info->scale_table[i].reg_range);
 530                         if (ret < 0) {
 531                                 dev_err(&data->client->dev,
 532                                         "Error writing pmu_range\n");
 533                                 return ret;
 534                         }
 535
 536                         data->range = data->chip_info->scale_table[i].reg_range;
 537                         return 0;
 538                 }
 539         }
 540
 541         return -EINVAL;
 542 }
 543
 544 static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val)
 545 {
 546         int ret;
 547
 548         mutex_lock(&data->mutex);
 549
 550         ret = i2c_smbus_read_byte_data(data->client, BMC150_ACCEL_REG_TEMP);
 551         if (ret < 0) {
 552                 dev_err(&data->client->dev, "Error reading reg_temp\n");
 553                 mutex_unlock(&data->mutex);
 554                 return ret;
 555         }
 556         *val = sign_extend32(ret, 7);
 557
 558         mutex_unlock(&data->mutex);
 559
 560         return IIO_VAL_INT;
 561 }
 562
 563 static int bmc150_accel_get_axis(struct bmc150_accel_data *data,
 564                                  struct iio_chan_spec const *chan,
 565                                  int *val)
 566 {
 567         int ret;
 568         int axis = chan->scan_index;
 569
 570         mutex_lock(&data->mutex);
 571         ret = bmc150_accel_set_power_state(data, true);
 572         if (ret < 0) {
 573                 mutex_unlock(&data->mutex);
 574                 return ret;
 575         }
 576
 577         ret = i2c_smbus_read_word_data(data->client,
 578                                        BMC150_ACCEL_AXIS_TO_REG(axis));
 579         if (ret < 0) {
 580                 dev_err(&data->client->dev, "Error reading axis %d\n", axis);
 581                 bmc150_accel_set_power_state(data, false);
 582                 mutex_unlock(&data->mutex);
 583                 return ret;
 584         }
 585         *val = sign_extend32(ret >> chan->scan_type.shift,
 586                              chan->scan_type.realbits - 1);
 587         ret = bmc150_accel_set_power_state(data, false);
 588         mutex_unlock(&data->mutex);
 589         if (ret < 0)
 590                 return ret;
 591
 592         return IIO_VAL_INT;
 593 }
 594
 595 static int bmc150_accel_read_raw(struct iio_dev *indio_dev,
 596                                  struct iio_chan_spec const *chan,
 597                                  int *val, int *val2, long mask)
 598 {
 599         struct bmc150_accel_data *data = iio_priv(indio_dev);
 600         int ret;
 601
 602         switch (mask) {
 603         case IIO_CHAN_INFO_RAW:
 604                 switch (chan->type) {
 605                 case IIO_TEMP:
 606                         return bmc150_accel_get_temp(data, val);
 607                 case IIO_ACCEL:
 608                         if (iio_buffer_enabled(indio_dev))
 609                                 return -EBUSY;
 610                         else
 611                                 return bmc150_accel_get_axis(data, chan, val);
 612                 default:
 613                         return -EINVAL;
 614                 }
 615         case IIO_CHAN_INFO_OFFSET:
 616                 if (chan->type == IIO_TEMP) {
 617                         *val = BMC150_ACCEL_TEMP_CENTER_VAL;
 618                         return IIO_VAL_INT;
 619                 } else {
 620                         return -EINVAL;
 621                 }
 622         case IIO_CHAN_INFO_SCALE:
 623                 *val = 0;
 624                 switch (chan->type) {
 625                 case IIO_TEMP:
 626                         *val2 = 500000;
 627                         return IIO_VAL_INT_PLUS_MICRO;
 628                 case IIO_ACCEL:
 629                 {
 630                         int i;
 631                         const struct bmc150_scale_info *si;
 632                         int st_size = ARRAY_SIZE(data->chip_info->scale_table);
 633
 634                         for (i = 0; i < st_size; ++i) {
 635                                 si = &data->chip_info->scale_table[i];
 636                                 if (si->reg_range == data->range) {
 637                                         *val2 = si->scale;
 638                                         return IIO_VAL_INT_PLUS_MICRO;
 639                                 }
 640                         }
 641                         return -EINVAL;
 642                 }
 643                 default:
 644                         return -EINVAL;
 645                 }
 646         case IIO_CHAN_INFO_SAMP_FREQ:
 647                 mutex_lock(&data->mutex);
 648                 ret = bmc150_accel_get_bw(data, val, val2);
 649                 mutex_unlock(&data->mutex);
 650                 return ret;
 651         default:
 652                 return -EINVAL;
 653         }
 654 }
 655
 656 static int bmc150_accel_write_raw(struct iio_dev *indio_dev,
 657                                   struct iio_chan_spec const *chan,
 658                                   int val, int val2, long mask)
 659 {
 660         struct bmc150_accel_data *data = iio_priv(indio_dev);
 661         int ret;
 662
 663         switch (mask) {
 664         case IIO_CHAN_INFO_SAMP_FREQ:
 665                 mutex_lock(&data->mutex);
 666                 ret = bmc150_accel_set_bw(data, val, val2);
 667                 mutex_unlock(&data->mutex);
 668                 break;
 669         case IIO_CHAN_INFO_SCALE:
 670                 if (val)
 671                         return -EINVAL;
 672
 673                 mutex_lock(&data->mutex);
 674                 ret = bmc150_accel_set_scale(data, val2);
 675                 mutex_unlock(&data->mutex);
 676                 return ret;
 677         default:
 678                 ret = -EINVAL;
 679         }
 680
 681         return ret;
 682 }
 683
 684 static int bmc150_accel_read_event(struct iio_dev *indio_dev,
 685                                    const struct iio_chan_spec *chan,
 686                                    enum iio_event_type type,
 687                                    enum iio_event_direction dir,
 688                                    enum iio_event_info info,
 689                                    int *val, int *val2)
 690 {
 691         struct bmc150_accel_data *data = iio_priv(indio_dev);
 692
 693         *val2 = 0;
 694         switch (info) {
 695         case IIO_EV_INFO_VALUE:
 696                 *val = data->slope_thres;
 697                 break;
 698         case IIO_EV_INFO_PERIOD:
 699                 *val = data->slope_dur;
 700                 break;
 701         default:
 702                 return -EINVAL;
 703         }
 704
 705         return IIO_VAL_INT;
 706 }
 707
 708 static int bmc150_accel_write_event(struct iio_dev *indio_dev,
 709                                     const struct iio_chan_spec *chan,
 710                                     enum iio_event_type type,
 711                                     enum iio_event_direction dir,
 712                                     enum iio_event_info info,
 713                                     int val, int val2)
 714 {
 715         struct bmc150_accel_data *data = iio_priv(indio_dev);
 716
 717         if (data->ev_enable_state)
 718                 return -EBUSY;
 719
 720         switch (info) {
 721         case IIO_EV_INFO_VALUE:
 722                 data->slope_thres = val & BMC150_ACCEL_SLOPE_THRES_MASK;
 723                 break;
 724         case IIO_EV_INFO_PERIOD:
 725                 data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK;
 726                 break;
 727         default:
 728                 return -EINVAL;
 729         }
 730
 731         return 0;
 732 }
 733
 734 static int bmc150_accel_read_event_config(struct iio_dev *indio_dev,
 735                                           const struct iio_chan_spec *chan,
 736                                           enum iio_event_type type,
 737                                           enum iio_event_direction dir)
 738 {
 739         struct bmc150_accel_data *data = iio_priv(indio_dev);
 740
 741         return data->ev_enable_state;
 742 }
 743
 744 static int bmc150_accel_write_event_config(struct iio_dev *indio_dev,
 745                                            const struct iio_chan_spec *chan,
 746                                            enum iio_event_type type,
 747                                            enum iio_event_direction dir,
 748                                            int state)
 749 {
 750         struct bmc150_accel_data *data = iio_priv(indio_dev);
 751         int ret;
 752
 753         if (state == data->ev_enable_state)
 754                 return 0;
 755
 756         mutex_lock(&data->mutex);
 757
 758         ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_ANY_MOTION,
 759                                          state);
 760         if (ret < 0) {
 761                 mutex_unlock(&data->mutex);
 762                 return ret;
 763         }
 764
 765         data->ev_enable_state = state;
 766         mutex_unlock(&data->mutex);
 767
 768         return 0;
 769 }
 770
 771 static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev,
 772                                          struct iio_trigger *trig)
 773 {
 774         struct bmc150_accel_data *data = iio_priv(indio_dev);
 775         int i;
 776
 777         for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
 778                 if (data->triggers[i].indio_trig == trig)
 779                         return 0;
 780         }
 781
 782         return -EINVAL;
 783 }
 784
 785 static ssize_t bmc150_accel_get_fifo_watermark(struct device *dev,
 786                                                struct device_attribute *attr,
 787                                                char *buf)
 788 {
 789         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 790         struct bmc150_accel_data *data = iio_priv(indio_dev);
 791         int wm;
 792
 793         mutex_lock(&data->mutex);
 794         wm = data->watermark;
 795         mutex_unlock(&data->mutex);
 796
 797         return sprintf(buf, "%d\n", wm);
 798 }
 799
 800 static ssize_t bmc150_accel_get_fifo_state(struct device *dev,
 801                                            struct device_attribute *attr,
 802                                            char *buf)
 803 {
 804         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 805         struct bmc150_accel_data *data = iio_priv(indio_dev);
 806         bool state;
 807
 808         mutex_lock(&data->mutex);
 809         state = data->fifo_mode;
 810         mutex_unlock(&data->mutex);
 811
 812         return sprintf(buf, "%d\n", state);
 813 }
 814
 815 static IIO_CONST_ATTR(hwfifo_watermark_min, "1");
 816 static IIO_CONST_ATTR(hwfifo_watermark_max,
 817                       __stringify(BMC150_ACCEL_FIFO_LENGTH));
 818 static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO,
 819                        bmc150_accel_get_fifo_state, NULL, 0);
 820 static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO,
 821                        bmc150_accel_get_fifo_watermark, NULL, 0);
 822
 823 static const struct attribute *bmc150_accel_fifo_attributes[] = {
 824         &iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
 825         &iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
 826         &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
 827         &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
 828         NULL,
 829 };
 830
 831 static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val)
 832 {
 833         struct bmc150_accel_data *data = iio_priv(indio_dev);
 834
 835         if (val > BMC150_ACCEL_FIFO_LENGTH)
 836                 val = BMC150_ACCEL_FIFO_LENGTH;
 837
 838         mutex_lock(&data->mutex);
 839         data->watermark = val;
 840         mutex_unlock(&data->mutex);
 841
 842         return 0;
 843 }
 844
 845 /*
 846  * We must read at least one full frame in one burst, otherwise the rest of the
 847  * frame data is discarded.
 848  */
 849 static int bmc150_accel_fifo_transfer(const struct i2c_client *client,
 850                                       char *buffer, int samples)
 851 {
 852         int sample_length = 3 * 2;
 853         u8 reg_fifo_data = BMC150_ACCEL_REG_FIFO_DATA;
 854         int ret = -EIO;
 855
 856         if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
 857                 struct i2c_msg msg[2] = {
 858                         {
 859                                 .addr = client->addr,
 860                                 .flags = 0,
 861                                 .buf = &reg_fifo_data,
 862                                 .len = sizeof(reg_fifo_data),
 863                         },
 864                         {
 865                                 .addr = client->addr,
 866                                 .flags = I2C_M_RD,
 867                                 .buf = (u8 *)buffer,
 868                                 .len = samples * sample_length,
 869                         }
 870                 };
 871
 872                 ret = i2c_transfer(client->adapter, msg, 2);
 873                 if (ret != 2)
 874                         ret = -EIO;
 875                 else
 876                         ret = 0;
 877         } else {
 878                 int i, step = I2C_SMBUS_BLOCK_MAX / sample_length;
 879
 880                 for (i = 0; i < samples * sample_length; i += step) {
 881                         ret = i2c_smbus_read_i2c_block_data(client,
 882                                                             reg_fifo_data, step,
 883                                                             &buffer[i]);
 884                         if (ret != step) {
 885                                 ret = -EIO;
 886                                 break;
 887                         }
 888
 889                         ret = 0;
 890                 }
 891         }
 892
 893         if (ret)
 894                 dev_err(&client->dev, "Error transferring data from fifo\n");
 895
 896         return ret;
 897 }
 898
 899 static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev,
 900                                      unsigned samples, bool irq)
 901 {
 902         struct bmc150_accel_data *data = iio_priv(indio_dev);
 903         int ret, i;
 904         u8 count;
 905         u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3];
 906         int64_t tstamp;
 907         uint64_t sample_period;
 908
 909         ret = i2c_smbus_read_byte_data(data->client,
 910                                        BMC150_ACCEL_REG_FIFO_STATUS);
 911         if (ret < 0) {
 912                 dev_err(&data->client->dev, "Error reading reg_fifo_status\n");
 913                 return ret;
 914         }
 915
 916         count = ret & 0x7F;
 917
 918         if (!count)
 919                 return 0;
 920
 921         /*
 922          * If we getting called from IRQ handler we know the stored timestamp is
 923          * fairly accurate for the last stored sample. Otherwise, if we are
 924          * called as a result of a read operation from userspace and hence
 925          * before the watermark interrupt was triggered, take a timestamp
 926          * now. We can fall anywhere in between two samples so the error in this
 927          * case is at most one sample period.
 928          */
 929         if (!irq) {
 930                 data->old_timestamp = data->timestamp;
 931                 data->timestamp = iio_get_time_ns();
 932         }
 933
 934         /*
 935          * Approximate timestamps for each of the sample based on the sampling
 936          * frequency, timestamp for last sample and number of samples.
 937          *
 938          * Note that we can't use the current bandwidth settings to compute the
 939          * sample period because the sample rate varies with the device
 940          * (e.g. between 31.70ms to 32.20ms for a bandwidth of 15.63HZ). That
 941          * small variation adds when we store a large number of samples and
 942          * creates significant jitter between the last and first samples in
 943          * different batches (e.g. 32ms vs 21ms).
 944          *
 945          * To avoid this issue we compute the actual sample period ourselves
 946          * based on the timestamp delta between the last two flush operations.
 947          */
 948         sample_period = (data->timestamp - data->old_timestamp);
 949         do_div(sample_period, count);
 950         tstamp = data->timestamp - (count - 1) * sample_period;
 951
 952         if (samples && count > samples)
 953                 count = samples;
 954
 955         ret = bmc150_accel_fifo_transfer(data->client, (u8 *)buffer, count);
 956         if (ret)
 957                 return ret;
 958
 959         /*
 960          * Ideally we want the IIO core to handle the demux when running in fifo
 961          * mode but not when running in triggered buffer mode. Unfortunately
 962          * this does not seem to be possible, so stick with driver demux for
 963          * now.
 964          */
 965         for (i = 0; i < count; i++) {
 966                 u16 sample[8];
 967                 int j, bit;
 968
 969                 j = 0;
 970                 for_each_set_bit(bit, indio_dev->active_scan_mask,
 971                                  indio_dev->masklength)
 972                         memcpy(&sample[j++], &buffer[i * 3 + bit], 2);
 973
 974                 iio_push_to_buffers_with_timestamp(indio_dev, sample, tstamp);
 975
 976                 tstamp += sample_period;
 977         }
 978
 979         return count;
 980 }
 981
 982 static int bmc150_accel_fifo_flush(struct iio_dev *indio_dev, unsigned samples)
 983 {
 984         struct bmc150_accel_data *data = iio_priv(indio_dev);
 985         int ret;
 986
 987         mutex_lock(&data->mutex);
 988         ret = __bmc150_accel_fifo_flush(indio_dev, samples, false);
 989         mutex_unlock(&data->mutex);
 990
 991         return ret;
 992 }
 993
 994 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
 995                 "15.620000 31.260000 62.50000 125 250 500 1000 2000");
 996
 997 static struct attribute *bmc150_accel_attributes[] = {
 998         &iio_const_attr_sampling_frequency_available.dev_attr.attr,
 999         NULL,
1000 };
1001
1002 static const struct attribute_group bmc150_accel_attrs_group = {
1003         .attrs = bmc150_accel_attributes,
1004 };
1005
1006 static const struct iio_event_spec bmc150_accel_event = {
1007                 .type = IIO_EV_TYPE_ROC,
1008                 .dir = IIO_EV_DIR_EITHER,
1009                 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
1010                                  BIT(IIO_EV_INFO_ENABLE) |
1011                                  BIT(IIO_EV_INFO_PERIOD)
1012 };
1013
1014 #define BMC150_ACCEL_CHANNEL(_axis, bits) {                             \
1015         .type = IIO_ACCEL,                                              \
1016         .modified = 1,                                                  \
1017         .channel2 = IIO_MOD_##_axis,                                    \
1018         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),                   \
1019         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |          \
1020                                 BIT(IIO_CHAN_INFO_SAMP_FREQ),           \
1021         .scan_index = AXIS_##_axis,                                     \
1022         .scan_type = {                                                  \
1023                 .sign = 's',                                            \
1024                 .realbits = (bits),                                     \
1025                 .storagebits = 16,                                      \
1026                 .shift = 16 - (bits),                                   \
1027         },                                                              \
1028         .event_spec = &bmc150_accel_event,                              \
1029         .num_event_specs = 1                                            \
1030 }
1031
1032 #define BMC150_ACCEL_CHANNELS(bits) {                                   \
1033         {                                                               \
1034                 .type = IIO_TEMP,                                       \
1035                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |          \
1036                                       BIT(IIO_CHAN_INFO_SCALE) |        \
1037                                       BIT(IIO_CHAN_INFO_OFFSET),        \
1038                 .scan_index = -1,                                       \
1039         },                                                              \
1040         BMC150_ACCEL_CHANNEL(X, bits),                                  \
1041         BMC150_ACCEL_CHANNEL(Y, bits),                                  \
1042         BMC150_ACCEL_CHANNEL(Z, bits),                                  \
1043         IIO_CHAN_SOFT_TIMESTAMP(3),                                     \
1044 }
1045
1046 static const struct iio_chan_spec bma222e_accel_channels[] =
1047         BMC150_ACCEL_CHANNELS(8);
1048 static const struct iio_chan_spec bma250e_accel_channels[] =
1049         BMC150_ACCEL_CHANNELS(10);
1050 static const struct iio_chan_spec bmc150_accel_channels[] =
1051         BMC150_ACCEL_CHANNELS(12);
1052 static const struct iio_chan_spec bma280_accel_channels[] =
1053         BMC150_ACCEL_CHANNELS(14);
1054
1055 enum {
1056         bmc150,
1057         bmi055,
1058         bma255,
1059         bma250e,
1060         bma222e,
1061         bma280,
1062 };
1063
1064 static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = {
1065         [bmc150] = {
1066                 .name = "BMC150A",
1067                 .chip_id = 0xFA,
1068                 .channels = bmc150_accel_channels,
1069                 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1070                 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1071                                  {19122, BMC150_ACCEL_DEF_RANGE_4G},
1072                                  {38344, BMC150_ACCEL_DEF_RANGE_8G},
1073                                  {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1074         },
1075         [bmi055] = {
1076                 .name = "BMI055A",
1077                 .chip_id = 0xFA,
1078                 .channels = bmc150_accel_channels,
1079                 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1080                 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1081                                  {19122, BMC150_ACCEL_DEF_RANGE_4G},
1082                                  {38344, BMC150_ACCEL_DEF_RANGE_8G},
1083                                  {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1084         },
1085         [bma255] = {
1086                 .name = "BMA0255",
1087                 .chip_id = 0xFA,
1088                 .channels = bmc150_accel_channels,
1089                 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1090                 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1091                                  {19122, BMC150_ACCEL_DEF_RANGE_4G},
1092                                  {38344, BMC150_ACCEL_DEF_RANGE_8G},
1093                                  {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1094         },
1095         [bma250e] = {
1096                 .name = "BMA250E",
1097                 .chip_id = 0xF9,
1098                 .channels = bma250e_accel_channels,
1099                 .num_channels = ARRAY_SIZE(bma250e_accel_channels),
1100                 .scale_table = { {38344, BMC150_ACCEL_DEF_RANGE_2G},
1101                                  {76590, BMC150_ACCEL_DEF_RANGE_4G},
1102                                  {153277, BMC150_ACCEL_DEF_RANGE_8G},
1103                                  {306457, BMC150_ACCEL_DEF_RANGE_16G} },
1104         },
1105         [bma222e] = {
1106                 .name = "BMA222E",
1107                 .chip_id = 0xF8,
1108                 .channels = bma222e_accel_channels,
1109                 .num_channels = ARRAY_SIZE(bma222e_accel_channels),
1110                 .scale_table = { {153277, BMC150_ACCEL_DEF_RANGE_2G},
1111                                  {306457, BMC150_ACCEL_DEF_RANGE_4G},
1112                                  {612915, BMC150_ACCEL_DEF_RANGE_8G},
1113                                  {1225831, BMC150_ACCEL_DEF_RANGE_16G} },
1114         },
1115         [bma280] = {
1116                 .name = "BMA0280",
1117                 .chip_id = 0xFB,
1118                 .channels = bma280_accel_channels,
1119                 .num_channels = ARRAY_SIZE(bma280_accel_channels),
1120                 .scale_table = { {2392, BMC150_ACCEL_DEF_RANGE_2G},
1121                                  {4785, BMC150_ACCEL_DEF_RANGE_4G},
1122                                  {9581, BMC150_ACCEL_DEF_RANGE_8G},
1123                                  {19152, BMC150_ACCEL_DEF_RANGE_16G} },
1124         },
1125 };
1126
1127 static const struct iio_info bmc150_accel_info = {
1128         .attrs                  = &bmc150_accel_attrs_group,
1129         .read_raw               = bmc150_accel_read_raw,
1130         .write_raw              = bmc150_accel_write_raw,
1131         .read_event_value       = bmc150_accel_read_event,
1132         .write_event_value      = bmc150_accel_write_event,
1133         .write_event_config     = bmc150_accel_write_event_config,
1134         .read_event_config      = bmc150_accel_read_event_config,
1135         .driver_module          = THIS_MODULE,
1136 };
1137
1138 static const struct iio_info bmc150_accel_info_fifo = {
1139         .attrs                  = &bmc150_accel_attrs_group,
1140         .read_raw               = bmc150_accel_read_raw,
1141         .write_raw              = bmc150_accel_write_raw,
1142         .read_event_value       = bmc150_accel_read_event,
1143         .write_event_value      = bmc150_accel_write_event,
1144         .write_event_config     = bmc150_accel_write_event_config,
1145         .read_event_config      = bmc150_accel_read_event_config,
1146         .validate_trigger       = bmc150_accel_validate_trigger,
1147         .hwfifo_set_watermark   = bmc150_accel_set_watermark,
1148         .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush,
1149         .driver_module          = THIS_MODULE,
1150 };
1151
1152 static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p)
1153 {
1154         struct iio_poll_func *pf = p;
1155         struct iio_dev *indio_dev = pf->indio_dev;
1156         struct bmc150_accel_data *data = iio_priv(indio_dev);
1157         int bit, ret, i = 0;
1158
1159         mutex_lock(&data->mutex);
1160         for_each_set_bit(bit, indio_dev->active_scan_mask,
1161                          indio_dev->masklength) {
1162                 ret = i2c_smbus_read_word_data(data->client,
1163                                                BMC150_ACCEL_AXIS_TO_REG(bit));
1164                 if (ret < 0) {
1165                         mutex_unlock(&data->mutex);
1166                         goto err_read;
1167                 }
1168                 data->buffer[i++] = ret;
1169         }
1170         mutex_unlock(&data->mutex);
1171
1172         iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
1173                                            pf->timestamp);
1174 err_read:
1175         iio_trigger_notify_done(indio_dev->trig);
1176
1177         return IRQ_HANDLED;
1178 }
1179
1180 static int bmc150_accel_trig_try_reen(struct iio_trigger *trig)
1181 {
1182         struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1183         struct bmc150_accel_data *data = t->data;
1184         int ret;
1185
1186         /* new data interrupts don't need ack */
1187         if (t == &t->data->triggers[BMC150_ACCEL_TRIGGER_DATA_READY])
1188                 return 0;
1189
1190         mutex_lock(&data->mutex);
1191         /* clear any latched interrupt */
1192         ret = i2c_smbus_write_byte_data(data->client,
1193                                         BMC150_ACCEL_REG_INT_RST_LATCH,
1194                                         BMC150_ACCEL_INT_MODE_LATCH_INT |
1195                                         BMC150_ACCEL_INT_MODE_LATCH_RESET);
1196         mutex_unlock(&data->mutex);
1197         if (ret < 0) {
1198                 dev_err(&data->client->dev,
1199                         "Error writing reg_int_rst_latch\n");
1200                 return ret;
1201         }
1202
1203         return 0;
1204 }
1205
1206 static int bmc150_accel_trigger_set_state(struct iio_trigger *trig,
1207                                           bool state)
1208 {
1209         struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1210         struct bmc150_accel_data *data = t->data;
1211         int ret;
1212
1213         mutex_lock(&data->mutex);
1214
1215         if (t->enabled == state) {
1216                 mutex_unlock(&data->mutex);
1217                 return 0;
1218         }
1219
1220         if (t->setup) {
1221                 ret = t->setup(t, state);
1222                 if (ret < 0) {
1223                         mutex_unlock(&data->mutex);
1224                         return ret;
1225                 }
1226         }
1227
1228         ret = bmc150_accel_set_interrupt(data, t->intr, state);
1229         if (ret < 0) {
1230                 mutex_unlock(&data->mutex);
1231                 return ret;
1232         }
1233
1234         t->enabled = state;
1235
1236         mutex_unlock(&data->mutex);
1237
1238         return ret;
1239 }
1240
1241 static const struct iio_trigger_ops bmc150_accel_trigger_ops = {
1242         .set_trigger_state = bmc150_accel_trigger_set_state,
1243         .try_reenable = bmc150_accel_trig_try_reen,
1244         .owner = THIS_MODULE,
1245 };
1246
1247 static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev)
1248 {
1249         struct bmc150_accel_data *data = iio_priv(indio_dev);
1250         int dir;
1251         int ret;
1252
1253         ret = i2c_smbus_read_byte_data(data->client,
1254                                        BMC150_ACCEL_REG_INT_STATUS_2);
1255         if (ret < 0) {
1256                 dev_err(&data->client->dev, "Error reading reg_int_status_2\n");
1257                 return ret;
1258         }
1259
1260         if (ret & BMC150_ACCEL_ANY_MOTION_BIT_SIGN)
1261                 dir = IIO_EV_DIR_FALLING;
1262         else
1263                 dir = IIO_EV_DIR_RISING;
1264
1265         if (ret & BMC150_ACCEL_ANY_MOTION_BIT_X)
1266                 iio_push_event(indio_dev,
1267                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
1268                                                   0,
1269                                                   IIO_MOD_X,
1270                                                   IIO_EV_TYPE_ROC,
1271                                                   dir),
1272                                data->timestamp);
1273
1274         if (ret & BMC150_ACCEL_ANY_MOTION_BIT_Y)
1275                 iio_push_event(indio_dev,
1276                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
1277                                                   0,
1278                                                   IIO_MOD_Y,
1279                                                   IIO_EV_TYPE_ROC,
1280                                                   dir),
1281                                data->timestamp);
1282
1283         if (ret & BMC150_ACCEL_ANY_MOTION_BIT_Z)
1284                 iio_push_event(indio_dev,
1285                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
1286                                                   0,
1287                                                   IIO_MOD_Z,
1288                                                   IIO_EV_TYPE_ROC,
1289                                                   dir),
1290                                data->timestamp);
1291
1292         return ret;
1293 }
1294
1295 static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private)
1296 {
1297         struct iio_dev *indio_dev = private;
1298         struct bmc150_accel_data *data = iio_priv(indio_dev);
1299         bool ack = false;
1300         int ret;
1301
1302         mutex_lock(&data->mutex);
1303
1304         if (data->fifo_mode) {
1305                 ret = __bmc150_accel_fifo_flush(indio_dev,
1306                                                 BMC150_ACCEL_FIFO_LENGTH, true);
1307                 if (ret > 0)
1308                         ack = true;
1309         }
1310
1311         if (data->ev_enable_state) {
1312                 ret = bmc150_accel_handle_roc_event(indio_dev);
1313                 if (ret > 0)
1314                         ack = true;
1315         }
1316
1317         if (ack) {
1318                 ret = i2c_smbus_write_byte_data(data->client,
1319                                         BMC150_ACCEL_REG_INT_RST_LATCH,
1320                                         BMC150_ACCEL_INT_MODE_LATCH_INT |
1321                                         BMC150_ACCEL_INT_MODE_LATCH_RESET);
1322                 if (ret)
1323                         dev_err(&data->client->dev,
1324                                 "Error writing reg_int_rst_latch\n");
1325
1326                 ret = IRQ_HANDLED;
1327         } else {
1328                 ret = IRQ_NONE;
1329         }
1330
1331         mutex_unlock(&data->mutex);
1332
1333         return ret;
1334 }
1335
1336 static irqreturn_t bmc150_accel_irq_handler(int irq, void *private)
1337 {
1338         struct iio_dev *indio_dev = private;
1339         struct bmc150_accel_data *data = iio_priv(indio_dev);
1340         bool ack = false;
1341         int i;
1342
1343         data->old_timestamp = data->timestamp;
1344         data->timestamp = iio_get_time_ns();
1345
1346         for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1347                 if (data->triggers[i].enabled) {
1348                         iio_trigger_poll(data->triggers[i].indio_trig);
1349                         ack = true;
1350                         break;
1351                 }
1352         }
1353
1354         if (data->ev_enable_state || data->fifo_mode)
1355                 return IRQ_WAKE_THREAD;
1356
1357         if (ack)
1358                 return IRQ_HANDLED;
1359
1360         return IRQ_NONE;
1361 }
1362
1363 static int bmc150_accel_gpio_probe(struct i2c_client *client,
1364                                    struct bmc150_accel_data *data)
1365 {
1366         struct device *dev;
1367         struct gpio_desc *gpio;
1368         int ret;
1369
1370         if (!client)
1371                 return -EINVAL;
1372
1373         dev = &client->dev;
1374
1375         /* data ready gpio interrupt pin */
1376         gpio = devm_gpiod_get_index(dev, BMC150_ACCEL_GPIO_NAME, 0, GPIOD_IN);
1377         if (IS_ERR(gpio)) {
1378                 dev_err(dev, "Failed: gpio get index\n");
1379                 return PTR_ERR(gpio);
1380         }
1381
1382         ret = gpiod_to_irq(gpio);
1383
1384         dev_dbg(dev, "GPIO resource, no:%d irq:%d\n", desc_to_gpio(gpio), ret);
1385
1386         return ret;
1387 }
1388
1389 static const struct {
1390         int intr;
1391         const char *name;
1392         int (*setup)(struct bmc150_accel_trigger *t, bool state);
1393 } bmc150_accel_triggers[BMC150_ACCEL_TRIGGERS] = {
1394         {
1395                 .intr = 0,
1396                 .name = "%s-dev%d",
1397         },
1398         {
1399                 .intr = 1,
1400                 .name = "%s-any-motion-dev%d",
1401                 .setup = bmc150_accel_any_motion_setup,
1402         },
1403 };
1404
1405 static void bmc150_accel_unregister_triggers(struct bmc150_accel_data *data,
1406                                              int from)
1407 {
1408         int i;
1409
1410         for (i = from; i >= 0; i--) {
1411                 if (data->triggers[i].indio_trig) {
1412                         iio_trigger_unregister(data->triggers[i].indio_trig);
1413                         data->triggers[i].indio_trig = NULL;
1414                 }
1415         }
1416 }
1417
1418 static int bmc150_accel_triggers_setup(struct iio_dev *indio_dev,
1419                                        struct bmc150_accel_data *data)
1420 {
1421         int i, ret;
1422
1423         for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1424                 struct bmc150_accel_trigger *t = &data->triggers[i];
1425
1426                 t->indio_trig = devm_iio_trigger_alloc(&data->client->dev,
1427                                                bmc150_accel_triggers[i].name,
1428                                                        indio_dev->name,
1429                                                        indio_dev->id);
1430                 if (!t->indio_trig) {
1431                         ret = -ENOMEM;
1432                         break;
1433                 }
1434
1435                 t->indio_trig->dev.parent = &data->client->dev;
1436                 t->indio_trig->ops = &bmc150_accel_trigger_ops;
1437                 t->intr = bmc150_accel_triggers[i].intr;
1438                 t->data = data;
1439                 t->setup = bmc150_accel_triggers[i].setup;
1440                 iio_trigger_set_drvdata(t->indio_trig, t);
1441
1442                 ret = iio_trigger_register(t->indio_trig);
1443                 if (ret)
1444                         break;
1445         }
1446
1447         if (ret)
1448                 bmc150_accel_unregister_triggers(data, i - 1);
1449
1450         return ret;
1451 }
1452
1453 #define BMC150_ACCEL_FIFO_MODE_STREAM          0x80
1454 #define BMC150_ACCEL_FIFO_MODE_FIFO            0x40
1455 #define BMC150_ACCEL_FIFO_MODE_BYPASS          0x00
1456
1457 static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data *data)
1458 {
1459         u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1;
1460         int ret;
1461
1462         ret = i2c_smbus_write_byte_data(data->client, reg, data->fifo_mode);
1463         if (ret < 0) {
1464                 dev_err(&data->client->dev, "Error writing reg_fifo_config1\n");
1465                 return ret;
1466         }
1467
1468         if (!data->fifo_mode)
1469                 return 0;
1470
1471         ret = i2c_smbus_write_byte_data(data->client,
1472                                         BMC150_ACCEL_REG_FIFO_CONFIG0,
1473                                         data->watermark);
1474         if (ret < 0)
1475                 dev_err(&data->client->dev, "Error writing reg_fifo_config0\n");
1476
1477         return ret;
1478 }
1479
1480 static int bmc150_accel_buffer_preenable(struct iio_dev *indio_dev)
1481 {
1482         struct bmc150_accel_data *data = iio_priv(indio_dev);
1483
1484         return bmc150_accel_set_power_state(data, true);
1485 }
1486
1487 static int bmc150_accel_buffer_postenable(struct iio_dev *indio_dev)
1488 {
1489         struct bmc150_accel_data *data = iio_priv(indio_dev);
1490         int ret = 0;
1491
1492         if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1493                 return iio_triggered_buffer_postenable(indio_dev);
1494
1495         mutex_lock(&data->mutex);
1496
1497         if (!data->watermark)
1498                 goto out;
1499
1500         ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1501                                          true);
1502         if (ret)
1503                 goto out;
1504
1505         data->fifo_mode = BMC150_ACCEL_FIFO_MODE_FIFO;
1506
1507         ret = bmc150_accel_fifo_set_mode(data);
1508         if (ret) {
1509                 data->fifo_mode = 0;
1510                 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1511                                            false);
1512         }
1513
1514 out:
1515         mutex_unlock(&data->mutex);
1516
1517         return ret;
1518 }
1519
1520 static int bmc150_accel_buffer_predisable(struct iio_dev *indio_dev)
1521 {
1522         struct bmc150_accel_data *data = iio_priv(indio_dev);
1523
1524         if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1525                 return iio_triggered_buffer_predisable(indio_dev);
1526
1527         mutex_lock(&data->mutex);
1528
1529         if (!data->fifo_mode)
1530                 goto out;
1531
1532         bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, false);
1533         __bmc150_accel_fifo_flush(indio_dev, BMC150_ACCEL_FIFO_LENGTH, false);
1534         data->fifo_mode = 0;
1535         bmc150_accel_fifo_set_mode(data);
1536
1537 out:
1538         mutex_unlock(&data->mutex);
1539
1540         return 0;
1541 }
1542
1543 static int bmc150_accel_buffer_postdisable(struct iio_dev *indio_dev)
1544 {
1545         struct bmc150_accel_data *data = iio_priv(indio_dev);
1546
1547         return bmc150_accel_set_power_state(data, false);
1548 }
1549
1550 static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops = {
1551         .preenable = bmc150_accel_buffer_preenable,
1552         .postenable = bmc150_accel_buffer_postenable,
1553         .predisable = bmc150_accel_buffer_predisable,
1554         .postdisable = bmc150_accel_buffer_postdisable,
1555 };
1556
1557 static int bmc150_accel_chip_init(struct bmc150_accel_data *data)
1558 {
1559         int ret, i;
1560
1561         ret = i2c_smbus_read_byte_data(data->client, BMC150_ACCEL_REG_CHIP_ID);
1562         if (ret < 0) {
1563                 dev_err(&data->client->dev, "Error: Reading chip id\n");
1564                 return ret;
1565         }
1566
1567         dev_dbg(&data->client->dev, "Chip Id %x\n", ret);
1568         for (i = 0; i < ARRAY_SIZE(bmc150_accel_chip_info_tbl); i++) {
1569                 if (bmc150_accel_chip_info_tbl[i].chip_id == ret) {
1570                         data->chip_info = &bmc150_accel_chip_info_tbl[i];
1571                         break;
1572                 }
1573         }
1574
1575         if (!data->chip_info) {
1576                 dev_err(&data->client->dev, "Unsupported chip %x\n", ret);
1577                 return -ENODEV;
1578         }
1579
1580         ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1581         if (ret < 0)
1582                 return ret;
1583
1584         /* Set Bandwidth */
1585         ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0);
1586         if (ret < 0)
1587                 return ret;
1588
1589         /* Set Default Range */
1590         ret = i2c_smbus_write_byte_data(data->client,
1591                                         BMC150_ACCEL_REG_PMU_RANGE,
1592                                         BMC150_ACCEL_DEF_RANGE_4G);
1593         if (ret < 0) {
1594                 dev_err(&data->client->dev, "Error writing reg_pmu_range\n");
1595                 return ret;
1596         }
1597
1598         data->range = BMC150_ACCEL_DEF_RANGE_4G;
1599
1600         /* Set default slope duration and thresholds */
1601         data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD;
1602         data->slope_dur = BMC150_ACCEL_DEF_SLOPE_DURATION;
1603         ret = bmc150_accel_update_slope(data);
1604         if (ret < 0)
1605                 return ret;
1606
1607         /* Set default as latched interrupts */
1608         ret = i2c_smbus_write_byte_data(data->client,
1609                                         BMC150_ACCEL_REG_INT_RST_LATCH,
1610                                         BMC150_ACCEL_INT_MODE_LATCH_INT |
1611                                         BMC150_ACCEL_INT_MODE_LATCH_RESET);
1612         if (ret < 0) {
1613                 dev_err(&data->client->dev,
1614                         "Error writing reg_int_rst_latch\n");
1615                 return ret;
1616         }
1617
1618         return 0;
1619 }
1620
1621 static int bmc150_accel_probe(struct i2c_client *client,
1622                               const struct i2c_device_id *id)
1623 {
1624         struct bmc150_accel_data *data;
1625         struct iio_dev *indio_dev;
1626         int ret;
1627         const char *name = NULL;
1628
1629         indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1630         if (!indio_dev)
1631                 return -ENOMEM;
1632
1633         data = iio_priv(indio_dev);
1634         i2c_set_clientdata(client, indio_dev);
1635         data->client = client;
1636
1637         if (id)
1638                 name = id->name;
1639
1640         ret = bmc150_accel_chip_init(data);
1641         if (ret < 0)
1642                 return ret;
1643
1644         mutex_init(&data->mutex);
1645
1646         indio_dev->dev.parent = &client->dev;
1647         indio_dev->channels = data->chip_info->channels;
1648         indio_dev->num_channels = data->chip_info->num_channels;
1649         indio_dev->name = name ? name : data->chip_info->name;
1650         indio_dev->modes = INDIO_DIRECT_MODE;
1651         indio_dev->info = &bmc150_accel_info;
1652
1653         ret = iio_triggered_buffer_setup(indio_dev,
1654                                          &iio_pollfunc_store_time,
1655                                          bmc150_accel_trigger_handler,
1656                                          &bmc150_accel_buffer_ops);
1657         if (ret < 0) {
1658                 dev_err(&client->dev, "Failed: iio triggered buffer setup\n");
1659                 return ret;
1660         }
1661
1662         if (client->irq < 0)
1663                 client->irq = bmc150_accel_gpio_probe(client, data);
1664
1665         if (client->irq > 0) {
1666                 ret = devm_request_threaded_irq(
1667                                                 &client->dev, client->irq,
1668                                                 bmc150_accel_irq_handler,
1669                                                 bmc150_accel_irq_thread_handler,
1670                                                 IRQF_TRIGGER_RISING,
1671                                                 BMC150_ACCEL_IRQ_NAME,
1672                                                 indio_dev);
1673                 if (ret)
1674                         goto err_buffer_cleanup;
1675
1676                 /*
1677                  * Set latched mode interrupt. While certain interrupts are
1678                  * non-latched regardless of this settings (e.g. new data) we
1679                  * want to use latch mode when we can to prevent interrupt
1680                  * flooding.
1681                  */
1682                 ret = i2c_smbus_write_byte_data(data->client,
1683                                                 BMC150_ACCEL_REG_INT_RST_LATCH,
1684                                              BMC150_ACCEL_INT_MODE_LATCH_RESET);
1685                 if (ret < 0) {
1686                         dev_err(&data->client->dev, "Error writing reg_int_rst_latch\n");
1687                         goto err_buffer_cleanup;
1688                 }
1689
1690                 bmc150_accel_interrupts_setup(indio_dev, data);
1691
1692                 ret = bmc150_accel_triggers_setup(indio_dev, data);
1693                 if (ret)
1694                         goto err_buffer_cleanup;
1695
1696                 if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C) ||
1697                     i2c_check_functionality(client->adapter,
1698                                             I2C_FUNC_SMBUS_READ_I2C_BLOCK)) {
1699                         indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1700                         indio_dev->info = &bmc150_accel_info_fifo;
1701                         indio_dev->buffer->attrs = bmc150_accel_fifo_attributes;
1702                 }
1703         }
1704
1705         ret = iio_device_register(indio_dev);
1706         if (ret < 0) {
1707                 dev_err(&client->dev, "Unable to register iio device\n");
1708                 goto err_trigger_unregister;
1709         }
1710
1711         ret = pm_runtime_set_active(&client->dev);
1712         if (ret)
1713                 goto err_iio_unregister;
1714
1715         pm_runtime_enable(&client->dev);
1716         pm_runtime_set_autosuspend_delay(&client->dev,
1717                                          BMC150_AUTO_SUSPEND_DELAY_MS);
1718         pm_runtime_use_autosuspend(&client->dev);
1719
1720         return 0;
1721
1722 err_iio_unregister:
1723         iio_device_unregister(indio_dev);
1724 err_trigger_unregister:
1725         bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1726 err_buffer_cleanup:
1727         iio_triggered_buffer_cleanup(indio_dev);
1728
1729         return ret;
1730 }
1731
1732 static int bmc150_accel_remove(struct i2c_client *client)
1733 {
1734         struct iio_dev *indio_dev = i2c_get_clientdata(client);
1735         struct bmc150_accel_data *data = iio_priv(indio_dev);
1736
1737         pm_runtime_disable(&client->dev);
1738         pm_runtime_set_suspended(&client->dev);
1739         pm_runtime_put_noidle(&client->dev);
1740
1741         iio_device_unregister(indio_dev);
1742
1743         bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1744
1745         iio_triggered_buffer_cleanup(indio_dev);
1746
1747         mutex_lock(&data->mutex);
1748         bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0);
1749         mutex_unlock(&data->mutex);
1750
1751         return 0;
1752 }
1753
1754 #ifdef CONFIG_PM_SLEEP
1755 static int bmc150_accel_suspend(struct device *dev)
1756 {
1757         struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1758         struct bmc150_accel_data *data = iio_priv(indio_dev);
1759
1760         mutex_lock(&data->mutex);
1761         bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1762         mutex_unlock(&data->mutex);
1763
1764         return 0;
1765 }
1766
1767 static int bmc150_accel_resume(struct device *dev)
1768 {
1769         struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1770         struct bmc150_accel_data *data = iio_priv(indio_dev);
1771
1772         mutex_lock(&data->mutex);
1773         if (atomic_read(&data->active_intr))
1774                 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1775         bmc150_accel_fifo_set_mode(data);
1776         mutex_unlock(&data->mutex);
1777
1778         return 0;
1779 }
1780 #endif
1781
1782 #ifdef CONFIG_PM
1783 static int bmc150_accel_runtime_suspend(struct device *dev)
1784 {
1785         struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1786         struct bmc150_accel_data *data = iio_priv(indio_dev);
1787         int ret;
1788
1789         dev_dbg(&data->client->dev,  __func__);
1790         ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1791         if (ret < 0)
1792                 return -EAGAIN;
1793
1794         return 0;
1795 }
1796
1797 static int bmc150_accel_runtime_resume(struct device *dev)
1798 {
1799         struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1800         struct bmc150_accel_data *data = iio_priv(indio_dev);
1801         int ret;
1802         int sleep_val;
1803
1804         dev_dbg(&data->client->dev,  __func__);
1805
1806         ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1807         if (ret < 0)
1808                 return ret;
1809         ret = bmc150_accel_fifo_set_mode(data);
1810         if (ret < 0)
1811                 return ret;
1812
1813         sleep_val = bmc150_accel_get_startup_times(data);
1814         if (sleep_val < 20)
1815                 usleep_range(sleep_val * 1000, 20000);
1816         else
1817                 msleep_interruptible(sleep_val);
1818
1819         return 0;
1820 }
1821 #endif
1822
1823 static const struct dev_pm_ops bmc150_accel_pm_ops = {
1824         SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume)
1825         SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend,
1826                            bmc150_accel_runtime_resume, NULL)
1827 };
1828
1829 static const struct acpi_device_id bmc150_accel_acpi_match[] = {
1830         {"BSBA0150",    bmc150},
1831         {"BMC150A",     bmc150},
1832         {"BMI055A",     bmi055},
1833         {"BMA0255",     bma255},
1834         {"BMA250E",     bma250e},
1835         {"BMA222E",     bma222e},
1836         {"BMA0280",     bma280},
1837         { },
1838 };
1839 MODULE_DEVICE_TABLE(acpi, bmc150_accel_acpi_match);
1840
1841 static const struct i2c_device_id bmc150_accel_id[] = {
1842         {"bmc150_accel",        bmc150},
1843         {"bmi055_accel",        bmi055},
1844         {"bma255",              bma255},
1845         {"bma250e",             bma250e},
1846         {"bma222e",             bma222e},
1847         {"bma280",              bma280},
1848         {}
1849 };
1850
1851 MODULE_DEVICE_TABLE(i2c, bmc150_accel_id);
1852
1853 static struct i2c_driver bmc150_accel_driver = {
1854         .driver = {
1855                 .name   = BMC150_ACCEL_DRV_NAME,
1856                 .acpi_match_table = ACPI_PTR(bmc150_accel_acpi_match),
1857                 .pm     = &bmc150_accel_pm_ops,
1858         },
1859         .probe          = bmc150_accel_probe,
1860         .remove         = bmc150_accel_remove,
1861         .id_table       = bmc150_accel_id,
1862 };
1863 module_i2c_driver(bmc150_accel_driver);
1864
1865 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1866 MODULE_LICENSE("GPL v2");
1867 MODULE_DESCRIPTION("BMC150 accelerometer driver");