2 * drivers/i2c/busses/i2c-tegra.c
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Colin Cross <ccross@android.com>
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
22 #include <linux/err.h>
23 #include <linux/i2c.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/of_device.h>
29 #include <linux/module.h>
30 #include <linux/reset.h>
32 #include <asm/unaligned.h>
34 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
35 #define BYTES_PER_FIFO_WORD 4
37 #define I2C_CNFG 0x000
38 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12
39 #define I2C_CNFG_PACKET_MODE_EN (1<<10)
40 #define I2C_CNFG_NEW_MASTER_FSM (1<<11)
41 #define I2C_STATUS 0x01C
42 #define I2C_SL_CNFG 0x020
43 #define I2C_SL_CNFG_NACK (1<<1)
44 #define I2C_SL_CNFG_NEWSL (1<<2)
45 #define I2C_SL_ADDR1 0x02c
46 #define I2C_SL_ADDR2 0x030
47 #define I2C_TX_FIFO 0x050
48 #define I2C_RX_FIFO 0x054
49 #define I2C_PACKET_TRANSFER_STATUS 0x058
50 #define I2C_FIFO_CONTROL 0x05c
51 #define I2C_FIFO_CONTROL_TX_FLUSH (1<<1)
52 #define I2C_FIFO_CONTROL_RX_FLUSH (1<<0)
53 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5
54 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2
55 #define I2C_FIFO_STATUS 0x060
56 #define I2C_FIFO_STATUS_TX_MASK 0xF0
57 #define I2C_FIFO_STATUS_TX_SHIFT 4
58 #define I2C_FIFO_STATUS_RX_MASK 0x0F
59 #define I2C_FIFO_STATUS_RX_SHIFT 0
60 #define I2C_INT_MASK 0x064
61 #define I2C_INT_STATUS 0x068
62 #define I2C_INT_PACKET_XFER_COMPLETE (1<<7)
63 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE (1<<6)
64 #define I2C_INT_TX_FIFO_OVERFLOW (1<<5)
65 #define I2C_INT_RX_FIFO_UNDERFLOW (1<<4)
66 #define I2C_INT_NO_ACK (1<<3)
67 #define I2C_INT_ARBITRATION_LOST (1<<2)
68 #define I2C_INT_TX_FIFO_DATA_REQ (1<<1)
69 #define I2C_INT_RX_FIFO_DATA_REQ (1<<0)
70 #define I2C_CLK_DIVISOR 0x06c
71 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT 16
72 #define I2C_CLK_MULTIPLIER_STD_FAST_MODE 8
74 #define DVC_CTRL_REG1 0x000
75 #define DVC_CTRL_REG1_INTR_EN (1<<10)
76 #define DVC_CTRL_REG2 0x004
77 #define DVC_CTRL_REG3 0x008
78 #define DVC_CTRL_REG3_SW_PROG (1<<26)
79 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN (1<<30)
80 #define DVC_STATUS 0x00c
81 #define DVC_STATUS_I2C_DONE_INTR (1<<30)
83 #define I2C_ERR_NONE 0x00
84 #define I2C_ERR_NO_ACK 0x01
85 #define I2C_ERR_ARBITRATION_LOST 0x02
86 #define I2C_ERR_UNKNOWN_INTERRUPT 0x04
88 #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28
89 #define PACKET_HEADER0_PACKET_ID_SHIFT 16
90 #define PACKET_HEADER0_CONT_ID_SHIFT 12
91 #define PACKET_HEADER0_PROTOCOL_I2C (1<<4)
93 #define I2C_HEADER_HIGHSPEED_MODE (1<<22)
94 #define I2C_HEADER_CONT_ON_NAK (1<<21)
95 #define I2C_HEADER_SEND_START_BYTE (1<<20)
96 #define I2C_HEADER_READ (1<<19)
97 #define I2C_HEADER_10BIT_ADDR (1<<18)
98 #define I2C_HEADER_IE_ENABLE (1<<17)
99 #define I2C_HEADER_REPEAT_START (1<<16)
100 #define I2C_HEADER_CONTINUE_XFER (1<<15)
101 #define I2C_HEADER_MASTER_ADDR_SHIFT 12
102 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1
104 * msg_end_type: The bus control which need to be send at end of transfer.
105 * @MSG_END_STOP: Send stop pulse at end of transfer.
106 * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
107 * @MSG_END_CONTINUE: The following on message is coming and so do not send
108 * stop or repeat start.
112 MSG_END_REPEAT_START,
117 * struct tegra_i2c_hw_feature : Different HW support on Tegra
118 * @has_continue_xfer_support: Continue transfer supports.
119 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
120 * complete interrupt per packet basis.
121 * @has_single_clk_source: The i2c controller has single clock source. Tegra30
122 * and earlier Socs has two clock sources i.e. div-clk and
124 * @clk_divisor_hs_mode: Clock divisor in HS mode.
125 * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is
126 * applicable if there is no fast clock source i.e. single clock
130 struct tegra_i2c_hw_feature {
131 bool has_continue_xfer_support;
132 bool has_per_pkt_xfer_complete_irq;
133 bool has_single_clk_source;
134 int clk_divisor_hs_mode;
135 int clk_divisor_std_fast_mode;
139 * struct tegra_i2c_dev - per device i2c context
140 * @dev: device reference for power management
141 * @hw: Tegra i2c hw feature.
142 * @adapter: core i2c layer adapter information
143 * @div_clk: clock reference for div clock of i2c controller.
144 * @fast_clk: clock reference for fast clock of i2c controller.
145 * @base: ioremapped registers cookie
146 * @cont_id: i2c controller id, used for for packet header
147 * @irq: irq number of transfer complete interrupt
148 * @is_dvc: identifies the DVC i2c controller, has a different register layout
149 * @msg_complete: transfer completion notifier
150 * @msg_err: error code for completed message
151 * @msg_buf: pointer to current message data
152 * @msg_buf_remaining: size of unsent data in the message buffer
153 * @msg_read: identifies read transfers
154 * @bus_clk_rate: current i2c bus clock rate
155 * @is_suspended: prevents i2c controller accesses after suspend is called
157 struct tegra_i2c_dev {
159 const struct tegra_i2c_hw_feature *hw;
160 struct i2c_adapter adapter;
162 struct clk *fast_clk;
163 struct reset_control *rst;
169 struct completion msg_complete;
172 size_t msg_buf_remaining;
178 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
180 writel(val, i2c_dev->base + reg);
183 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
185 return readl(i2c_dev->base + reg);
189 * i2c_writel and i2c_readl will offset the register if necessary to talk
190 * to the I2C block inside the DVC block
192 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
196 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
200 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
203 writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
205 /* Read back register to make sure that register writes completed */
206 if (reg != I2C_TX_FIFO)
207 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
210 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
212 return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
215 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
216 unsigned long reg, int len)
218 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
221 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
222 unsigned long reg, int len)
224 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
227 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
229 u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
231 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
234 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
236 u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
238 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
241 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
243 unsigned long timeout = jiffies + HZ;
244 u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
245 val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
246 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
248 while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
249 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
250 if (time_after(jiffies, timeout)) {
251 dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
259 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
263 u8 *buf = i2c_dev->msg_buf;
264 size_t buf_remaining = i2c_dev->msg_buf_remaining;
265 int words_to_transfer;
267 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
268 rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
269 I2C_FIFO_STATUS_RX_SHIFT;
271 /* Rounds down to not include partial word at the end of buf */
272 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
273 if (words_to_transfer > rx_fifo_avail)
274 words_to_transfer = rx_fifo_avail;
276 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
278 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
279 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
280 rx_fifo_avail -= words_to_transfer;
283 * If there is a partial word at the end of buf, handle it manually to
284 * prevent overwriting past the end of buf
286 if (rx_fifo_avail > 0 && buf_remaining > 0) {
287 BUG_ON(buf_remaining > 3);
288 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
289 val = cpu_to_le32(val);
290 memcpy(buf, &val, buf_remaining);
295 BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
296 i2c_dev->msg_buf_remaining = buf_remaining;
297 i2c_dev->msg_buf = buf;
301 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
305 u8 *buf = i2c_dev->msg_buf;
306 size_t buf_remaining = i2c_dev->msg_buf_remaining;
307 int words_to_transfer;
309 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
310 tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
311 I2C_FIFO_STATUS_TX_SHIFT;
313 /* Rounds down to not include partial word at the end of buf */
314 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
316 /* It's very common to have < 4 bytes, so optimize that case. */
317 if (words_to_transfer) {
318 if (words_to_transfer > tx_fifo_avail)
319 words_to_transfer = tx_fifo_avail;
322 * Update state before writing to FIFO. If this casues us
323 * to finish writing all bytes (AKA buf_remaining goes to 0) we
324 * have a potential for an interrupt (PACKET_XFER_COMPLETE is
325 * not maskable). We need to make sure that the isr sees
326 * buf_remaining as 0 and doesn't call us back re-entrantly.
328 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
329 tx_fifo_avail -= words_to_transfer;
330 i2c_dev->msg_buf_remaining = buf_remaining;
331 i2c_dev->msg_buf = buf +
332 words_to_transfer * BYTES_PER_FIFO_WORD;
335 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
337 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
341 * If there is a partial word at the end of buf, handle it manually to
342 * prevent reading past the end of buf, which could cross a page
343 * boundary and fault.
345 if (tx_fifo_avail > 0 && buf_remaining > 0) {
346 BUG_ON(buf_remaining > 3);
347 memcpy(&val, buf, buf_remaining);
348 val = le32_to_cpu(val);
350 /* Again update before writing to FIFO to make sure isr sees. */
351 i2c_dev->msg_buf_remaining = 0;
352 i2c_dev->msg_buf = NULL;
355 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
362 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
363 * block. This block is identical to the rest of the I2C blocks, except that
364 * it only supports master mode, it has registers moved around, and it needs
365 * some extra init to get it into I2C mode. The register moves are handled
366 * by i2c_readl and i2c_writel
368 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
371 val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
372 val |= DVC_CTRL_REG3_SW_PROG;
373 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
374 dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
376 val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
377 val |= DVC_CTRL_REG1_INTR_EN;
378 dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
381 static inline int tegra_i2c_clock_enable(struct tegra_i2c_dev *i2c_dev)
384 if (!i2c_dev->hw->has_single_clk_source) {
385 ret = clk_enable(i2c_dev->fast_clk);
387 dev_err(i2c_dev->dev,
388 "Enabling fast clk failed, err %d\n", ret);
392 ret = clk_enable(i2c_dev->div_clk);
394 dev_err(i2c_dev->dev,
395 "Enabling div clk failed, err %d\n", ret);
396 clk_disable(i2c_dev->fast_clk);
401 static inline void tegra_i2c_clock_disable(struct tegra_i2c_dev *i2c_dev)
403 clk_disable(i2c_dev->div_clk);
404 if (!i2c_dev->hw->has_single_clk_source)
405 clk_disable(i2c_dev->fast_clk);
408 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
414 err = tegra_i2c_clock_enable(i2c_dev);
416 dev_err(i2c_dev->dev, "Clock enable failed %d\n", err);
420 reset_control_assert(i2c_dev->rst);
422 reset_control_deassert(i2c_dev->rst);
425 tegra_dvc_init(i2c_dev);
427 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
428 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
429 i2c_writel(i2c_dev, val, I2C_CNFG);
430 i2c_writel(i2c_dev, 0, I2C_INT_MASK);
432 /* Make sure clock divisor programmed correctly */
433 clk_divisor = i2c_dev->hw->clk_divisor_hs_mode;
434 clk_divisor |= i2c_dev->hw->clk_divisor_std_fast_mode <<
435 I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
436 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
438 if (!i2c_dev->is_dvc) {
439 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
440 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
441 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
442 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
443 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
447 val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
448 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
449 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
451 if (tegra_i2c_flush_fifos(i2c_dev))
454 tegra_i2c_clock_disable(i2c_dev);
456 if (i2c_dev->irq_disabled) {
457 i2c_dev->irq_disabled = 0;
458 enable_irq(i2c_dev->irq);
464 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
467 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
468 struct tegra_i2c_dev *i2c_dev = dev_id;
470 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
473 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
474 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
475 i2c_readl(i2c_dev, I2C_STATUS),
476 i2c_readl(i2c_dev, I2C_CNFG));
477 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
479 if (!i2c_dev->irq_disabled) {
480 disable_irq_nosync(i2c_dev->irq);
481 i2c_dev->irq_disabled = 1;
486 if (unlikely(status & status_err)) {
487 if (status & I2C_INT_NO_ACK)
488 i2c_dev->msg_err |= I2C_ERR_NO_ACK;
489 if (status & I2C_INT_ARBITRATION_LOST)
490 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
494 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
495 if (i2c_dev->msg_buf_remaining)
496 tegra_i2c_empty_rx_fifo(i2c_dev);
501 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
502 if (i2c_dev->msg_buf_remaining)
503 tegra_i2c_fill_tx_fifo(i2c_dev);
505 tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
508 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
510 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
512 if (status & I2C_INT_PACKET_XFER_COMPLETE) {
513 BUG_ON(i2c_dev->msg_buf_remaining);
514 complete(&i2c_dev->msg_complete);
518 /* An error occurred, mask all interrupts */
519 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
520 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
521 I2C_INT_RX_FIFO_DATA_REQ);
522 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
524 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
526 complete(&i2c_dev->msg_complete);
530 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
531 struct i2c_msg *msg, enum msg_end_type end_state)
535 unsigned long time_left;
537 tegra_i2c_flush_fifos(i2c_dev);
542 i2c_dev->msg_buf = msg->buf;
543 i2c_dev->msg_buf_remaining = msg->len;
544 i2c_dev->msg_err = I2C_ERR_NONE;
545 i2c_dev->msg_read = (msg->flags & I2C_M_RD);
546 reinit_completion(&i2c_dev->msg_complete);
548 packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
549 PACKET_HEADER0_PROTOCOL_I2C |
550 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
551 (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
552 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
554 packet_header = msg->len - 1;
555 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
557 packet_header = I2C_HEADER_IE_ENABLE;
558 if (end_state == MSG_END_CONTINUE)
559 packet_header |= I2C_HEADER_CONTINUE_XFER;
560 else if (end_state == MSG_END_REPEAT_START)
561 packet_header |= I2C_HEADER_REPEAT_START;
562 if (msg->flags & I2C_M_TEN) {
563 packet_header |= msg->addr;
564 packet_header |= I2C_HEADER_10BIT_ADDR;
566 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
568 if (msg->flags & I2C_M_IGNORE_NAK)
569 packet_header |= I2C_HEADER_CONT_ON_NAK;
570 if (msg->flags & I2C_M_RD)
571 packet_header |= I2C_HEADER_READ;
572 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
574 if (!(msg->flags & I2C_M_RD))
575 tegra_i2c_fill_tx_fifo(i2c_dev);
577 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
578 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
579 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
580 if (msg->flags & I2C_M_RD)
581 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
582 else if (i2c_dev->msg_buf_remaining)
583 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
584 tegra_i2c_unmask_irq(i2c_dev, int_mask);
585 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
586 i2c_readl(i2c_dev, I2C_INT_MASK));
588 time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
590 tegra_i2c_mask_irq(i2c_dev, int_mask);
592 if (time_left == 0) {
593 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
595 tegra_i2c_init(i2c_dev);
599 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
600 time_left, completion_done(&i2c_dev->msg_complete),
603 if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
607 * NACK interrupt is generated before the I2C controller generates the
608 * STOP condition on the bus. So wait for 2 clock periods before resetting
609 * the controller so that STOP condition has been delivered properly.
611 if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
612 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
614 tegra_i2c_init(i2c_dev);
615 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
616 if (msg->flags & I2C_M_IGNORE_NAK)
624 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
627 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
631 if (i2c_dev->is_suspended)
634 ret = tegra_i2c_clock_enable(i2c_dev);
636 dev_err(i2c_dev->dev, "Clock enable failed %d\n", ret);
640 for (i = 0; i < num; i++) {
641 enum msg_end_type end_type = MSG_END_STOP;
643 if (msgs[i + 1].flags & I2C_M_NOSTART)
644 end_type = MSG_END_CONTINUE;
646 end_type = MSG_END_REPEAT_START;
648 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
652 tegra_i2c_clock_disable(i2c_dev);
656 static u32 tegra_i2c_func(struct i2c_adapter *adap)
658 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
659 u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
660 I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING;
662 if (i2c_dev->hw->has_continue_xfer_support)
663 ret |= I2C_FUNC_NOSTART;
667 static const struct i2c_algorithm tegra_i2c_algo = {
668 .master_xfer = tegra_i2c_xfer,
669 .functionality = tegra_i2c_func,
672 /* payload size is only 12 bit */
673 static struct i2c_adapter_quirks tegra_i2c_quirks = {
674 .max_read_len = 4096,
675 .max_write_len = 4096,
678 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
679 .has_continue_xfer_support = false,
680 .has_per_pkt_xfer_complete_irq = false,
681 .has_single_clk_source = false,
682 .clk_divisor_hs_mode = 3,
683 .clk_divisor_std_fast_mode = 0,
686 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
687 .has_continue_xfer_support = true,
688 .has_per_pkt_xfer_complete_irq = false,
689 .has_single_clk_source = false,
690 .clk_divisor_hs_mode = 3,
691 .clk_divisor_std_fast_mode = 0,
694 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
695 .has_continue_xfer_support = true,
696 .has_per_pkt_xfer_complete_irq = true,
697 .has_single_clk_source = true,
698 .clk_divisor_hs_mode = 1,
699 .clk_divisor_std_fast_mode = 0x19,
702 /* Match table for of_platform binding */
703 static const struct of_device_id tegra_i2c_of_match[] = {
704 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
705 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
706 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
707 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
710 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
712 static int tegra_i2c_probe(struct platform_device *pdev)
714 struct tegra_i2c_dev *i2c_dev;
715 struct resource *res;
717 struct clk *fast_clk;
721 int clk_multiplier = I2C_CLK_MULTIPLIER_STD_FAST_MODE;
723 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
724 base = devm_ioremap_resource(&pdev->dev, res);
726 return PTR_ERR(base);
728 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
730 dev_err(&pdev->dev, "no irq resource\n");
735 div_clk = devm_clk_get(&pdev->dev, "div-clk");
736 if (IS_ERR(div_clk)) {
737 dev_err(&pdev->dev, "missing controller clock");
738 return PTR_ERR(div_clk);
741 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
745 i2c_dev->base = base;
746 i2c_dev->div_clk = div_clk;
747 i2c_dev->adapter.algo = &tegra_i2c_algo;
748 i2c_dev->adapter.quirks = &tegra_i2c_quirks;
750 i2c_dev->cont_id = pdev->id;
751 i2c_dev->dev = &pdev->dev;
753 i2c_dev->rst = devm_reset_control_get(&pdev->dev, "i2c");
754 if (IS_ERR(i2c_dev->rst)) {
755 dev_err(&pdev->dev, "missing controller reset");
756 return PTR_ERR(i2c_dev->rst);
759 ret = of_property_read_u32(i2c_dev->dev->of_node, "clock-frequency",
760 &i2c_dev->bus_clk_rate);
762 i2c_dev->bus_clk_rate = 100000; /* default clock rate */
764 i2c_dev->hw = &tegra20_i2c_hw;
766 if (pdev->dev.of_node) {
767 const struct of_device_id *match;
768 match = of_match_device(tegra_i2c_of_match, &pdev->dev);
769 i2c_dev->hw = match->data;
770 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
771 "nvidia,tegra20-i2c-dvc");
772 } else if (pdev->id == 3) {
775 init_completion(&i2c_dev->msg_complete);
777 if (!i2c_dev->hw->has_single_clk_source) {
778 fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
779 if (IS_ERR(fast_clk)) {
780 dev_err(&pdev->dev, "missing fast clock");
781 return PTR_ERR(fast_clk);
783 i2c_dev->fast_clk = fast_clk;
786 platform_set_drvdata(pdev, i2c_dev);
788 if (!i2c_dev->hw->has_single_clk_source) {
789 ret = clk_prepare(i2c_dev->fast_clk);
791 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
796 clk_multiplier *= (i2c_dev->hw->clk_divisor_std_fast_mode + 1);
797 ret = clk_set_rate(i2c_dev->div_clk,
798 i2c_dev->bus_clk_rate * clk_multiplier);
800 dev_err(i2c_dev->dev, "Clock rate change failed %d\n", ret);
801 goto unprepare_fast_clk;
804 ret = clk_prepare(i2c_dev->div_clk);
806 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
807 goto unprepare_fast_clk;
810 ret = tegra_i2c_init(i2c_dev);
812 dev_err(&pdev->dev, "Failed to initialize i2c controller");
813 goto unprepare_div_clk;
816 ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
817 tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev);
819 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
820 goto unprepare_div_clk;
823 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
824 i2c_dev->adapter.owner = THIS_MODULE;
825 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
826 strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",
827 sizeof(i2c_dev->adapter.name));
828 i2c_dev->adapter.algo = &tegra_i2c_algo;
829 i2c_dev->adapter.dev.parent = &pdev->dev;
830 i2c_dev->adapter.nr = pdev->id;
831 i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
833 ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
835 dev_err(&pdev->dev, "Failed to add I2C adapter\n");
836 goto unprepare_div_clk;
842 clk_unprepare(i2c_dev->div_clk);
845 if (!i2c_dev->hw->has_single_clk_source)
846 clk_unprepare(i2c_dev->fast_clk);
851 static int tegra_i2c_remove(struct platform_device *pdev)
853 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
854 i2c_del_adapter(&i2c_dev->adapter);
856 clk_unprepare(i2c_dev->div_clk);
857 if (!i2c_dev->hw->has_single_clk_source)
858 clk_unprepare(i2c_dev->fast_clk);
863 #ifdef CONFIG_PM_SLEEP
864 static int tegra_i2c_suspend(struct device *dev)
866 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
868 i2c_lock_adapter(&i2c_dev->adapter);
869 i2c_dev->is_suspended = true;
870 i2c_unlock_adapter(&i2c_dev->adapter);
875 static int tegra_i2c_resume(struct device *dev)
877 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
880 i2c_lock_adapter(&i2c_dev->adapter);
882 ret = tegra_i2c_init(i2c_dev);
885 i2c_unlock_adapter(&i2c_dev->adapter);
889 i2c_dev->is_suspended = false;
891 i2c_unlock_adapter(&i2c_dev->adapter);
896 static SIMPLE_DEV_PM_OPS(tegra_i2c_pm, tegra_i2c_suspend, tegra_i2c_resume);
897 #define TEGRA_I2C_PM (&tegra_i2c_pm)
899 #define TEGRA_I2C_PM NULL
902 static struct platform_driver tegra_i2c_driver = {
903 .probe = tegra_i2c_probe,
904 .remove = tegra_i2c_remove,
907 .of_match_table = tegra_i2c_of_match,
912 static int __init tegra_i2c_init_driver(void)
914 return platform_driver_register(&tegra_i2c_driver);
917 static void __exit tegra_i2c_exit_driver(void)
919 platform_driver_unregister(&tegra_i2c_driver);
922 subsys_initcall(tegra_i2c_init_driver);
923 module_exit(tegra_i2c_exit_driver);
925 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
926 MODULE_AUTHOR("Colin Cross");
927 MODULE_LICENSE("GPL v2");