drivers/i2c/busses/i2c-tegra.c

   1 /*
   2  * drivers/i2c/busses/i2c-tegra.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Author: Colin Cross <ccross@android.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/clk.h>
  22 #include <linux/i2c.h>
  23 #include <linux/io.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/delay.h>
  26 #include <linux/slab.h>
  27 #include <linux/i2c-tegra.h>
  28
  29 #include <asm/unaligned.h>
  30
  31 #include <mach/clk.h>
  32 #include <mach/pinmux.h>
  33
  34 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
  35 #define BYTES_PER_FIFO_WORD 4
  36
  37 #define I2C_CNFG                                0x000
  38 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT             12
  39 #define I2C_CNFG_PACKET_MODE_EN                 (1<<10)
  40 #define I2C_CNFG_NEW_MASTER_FSM                 (1<<11)
  41 #define I2C_STATUS                              0x01C
  42 #define I2C_SL_CNFG                             0x020
  43 #define I2C_SL_CNFG_NEWSL                       (1<<2)
  44 #define I2C_SL_ADDR1                            0x02c
  45 #define I2C_TX_FIFO                             0x050
  46 #define I2C_RX_FIFO                             0x054
  47 #define I2C_PACKET_TRANSFER_STATUS              0x058
  48 #define I2C_FIFO_CONTROL                        0x05c
  49 #define I2C_FIFO_CONTROL_TX_FLUSH               (1<<1)
  50 #define I2C_FIFO_CONTROL_RX_FLUSH               (1<<0)
  51 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT          5
  52 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT          2
  53 #define I2C_FIFO_STATUS                         0x060
  54 #define I2C_FIFO_STATUS_TX_MASK                 0xF0
  55 #define I2C_FIFO_STATUS_TX_SHIFT                4
  56 #define I2C_FIFO_STATUS_RX_MASK                 0x0F
  57 #define I2C_FIFO_STATUS_RX_SHIFT                0
  58 #define I2C_INT_MASK                            0x064
  59 #define I2C_INT_STATUS                          0x068
  60 #define I2C_INT_PACKET_XFER_COMPLETE            (1<<7)
  61 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE       (1<<6)
  62 #define I2C_INT_TX_FIFO_OVERFLOW                (1<<5)
  63 #define I2C_INT_RX_FIFO_UNDERFLOW               (1<<4)
  64 #define I2C_INT_NO_ACK                          (1<<3)
  65 #define I2C_INT_ARBITRATION_LOST                (1<<2)
  66 #define I2C_INT_TX_FIFO_DATA_REQ                (1<<1)
  67 #define I2C_INT_RX_FIFO_DATA_REQ                (1<<0)
  68 #define I2C_CLK_DIVISOR                         0x06c
  69
  70 #define DVC_CTRL_REG1                           0x000
  71 #define DVC_CTRL_REG1_INTR_EN                   (1<<10)
  72 #define DVC_CTRL_REG2                           0x004
  73 #define DVC_CTRL_REG3                           0x008
  74 #define DVC_CTRL_REG3_SW_PROG                   (1<<26)
  75 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN          (1<<30)
  76 #define DVC_STATUS                              0x00c
  77 #define DVC_STATUS_I2C_DONE_INTR                (1<<30)
  78
  79 #define I2C_ERR_NONE                            0x00
  80 #define I2C_ERR_NO_ACK                          0x01
  81 #define I2C_ERR_ARBITRATION_LOST                0x02
  82 #define I2C_ERR_UNKNOWN_INTERRUPT               0x04
  83
  84 #define PACKET_HEADER0_HEADER_SIZE_SHIFT        28
  85 #define PACKET_HEADER0_PACKET_ID_SHIFT          16
  86 #define PACKET_HEADER0_CONT_ID_SHIFT            12
  87 #define PACKET_HEADER0_PROTOCOL_I2C             (1<<4)
  88
  89 #define I2C_HEADER_HIGHSPEED_MODE               (1<<22)
  90 #define I2C_HEADER_CONT_ON_NAK                  (1<<21)
  91 #define I2C_HEADER_SEND_START_BYTE              (1<<20)
  92 #define I2C_HEADER_READ                         (1<<19)
  93 #define I2C_HEADER_10BIT_ADDR                   (1<<18)
  94 #define I2C_HEADER_IE_ENABLE                    (1<<17)
  95 #define I2C_HEADER_REPEAT_START                 (1<<16)
  96 #define I2C_HEADER_MASTER_ADDR_SHIFT            12
  97 #define I2C_HEADER_SLAVE_ADDR_SHIFT             1
  98
  99 #define DEBUG_TEGRA_I2C_TEMP
 100
 101 struct tegra_i2c_dev;
 102
 103 struct tegra_i2c_bus {
 104         struct tegra_i2c_dev *dev;
 105         const struct tegra_pingroup_config *mux;
 106         int mux_len;
 107         unsigned long bus_clk_rate;
 108         struct i2c_adapter adapter;
 109 };
 110
 111 struct tegra_i2c_dev {
 112         struct device *dev;
 113         struct clk *clk;
 114         struct clk *i2c_clk;
 115         struct resource *iomem;
 116         struct rt_mutex dev_lock;
 117         void __iomem *base;
 118         int cont_id;
 119         int irq;
 120         bool irq_disabled;
 121         int is_dvc;
 122         struct completion msg_complete;
 123         int msg_err;
 124         u8 *msg_buf;
 125         size_t msg_buf_remaining;
 126         int msg_read;
 127         int msg_transfer_complete;
 128         bool is_suspended;
 129         int bus_count;
 130         const struct tegra_pingroup_config *last_mux;
 131         int last_mux_len;
 132         unsigned long last_bus_clk;
 133         struct tegra_i2c_bus busses[1];
 134 #ifdef DEBUG_TEGRA_I2C_TEMP
 135         atomic_t incmplt_irq_count;
 136 #endif
 137 };
 138
 139 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
 140 {
 141         writel(val, i2c_dev->base + reg);
 142 }
 143
 144 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 145 {
 146         return readl(i2c_dev->base + reg);
 147 }
 148
 149 /* i2c_writel and i2c_readl will offset the register if necessary to talk
 150  * to the I2C block inside the DVC block
 151  */
 152 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
 153 {
 154         if (i2c_dev->is_dvc)
 155                 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
 156         writel(val, i2c_dev->base + reg);
 157 }
 158
 159 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 160 {
 161         if (i2c_dev->is_dvc)
 162                 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
 163         return readl(i2c_dev->base + reg);
 164 }
 165
 166 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 167 {
 168         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
 169         int_mask &= ~mask;
 170         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 171 }
 172
 173 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 174 {
 175         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
 176         int_mask |= mask;
 177         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 178 }
 179
 180 static void tegra_i2c_set_clk(struct tegra_i2c_dev *i2c_dev, unsigned int freq)
 181 {
 182         clk_set_rate(i2c_dev->clk, freq * 8);
 183 }
 184
 185 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
 186 {
 187         unsigned long timeout = jiffies + HZ;
 188         u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
 189         val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
 190         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 191
 192         while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
 193                 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
 194                 if (time_after(jiffies, timeout)) {
 195                         dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
 196                         return -ETIMEDOUT;
 197                 }
 198                 msleep(1);
 199         }
 200         return 0;
 201 }
 202
 203 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
 204 {
 205         u32 val;
 206         int rx_fifo_avail;
 207         int word;
 208         u8 *buf = i2c_dev->msg_buf;
 209         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 210         int words_to_transfer;
 211
 212         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 213         rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
 214                 I2C_FIFO_STATUS_RX_SHIFT;
 215
 216         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 217         if (words_to_transfer > rx_fifo_avail)
 218                 words_to_transfer = rx_fifo_avail;
 219
 220         for (word = 0; word < words_to_transfer; word++) {
 221                 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
 222                 put_unaligned_le32(val, buf);
 223                 buf += BYTES_PER_FIFO_WORD;
 224                 buf_remaining -= BYTES_PER_FIFO_WORD;
 225                 rx_fifo_avail--;
 226         }
 227
 228         if (rx_fifo_avail > 0 && buf_remaining > 0) {
 229                 int bytes_to_transfer = buf_remaining;
 230                 int byte;
 231                 BUG_ON(bytes_to_transfer > 3);
 232                 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
 233                 for (byte = 0; byte < bytes_to_transfer; byte++) {
 234                         *buf++ = val & 0xFF;
 235                         val >>= 8;
 236                 }
 237                 buf_remaining -= bytes_to_transfer;
 238                 rx_fifo_avail--;
 239         }
 240         BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
 241         i2c_dev->msg_buf_remaining = buf_remaining;
 242         i2c_dev->msg_buf = buf;
 243         return 0;
 244 }
 245
 246 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
 247 {
 248         u32 val;
 249         int tx_fifo_avail;
 250         int word;
 251         u8 *buf = i2c_dev->msg_buf;
 252         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 253         int words_to_transfer;
 254
 255         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 256         tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
 257                 I2C_FIFO_STATUS_TX_SHIFT;
 258
 259         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 260         if (words_to_transfer > tx_fifo_avail)
 261                 words_to_transfer = tx_fifo_avail;
 262
 263         for (word = 0; word < words_to_transfer; word++) {
 264                 val = get_unaligned_le32(buf);
 265                 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
 266                 buf += BYTES_PER_FIFO_WORD;
 267                 buf_remaining -= BYTES_PER_FIFO_WORD;
 268                 tx_fifo_avail--;
 269         }
 270
 271         if (tx_fifo_avail > 0 && buf_remaining > 0) {
 272                 int bytes_to_transfer = buf_remaining;
 273                 int byte;
 274                 BUG_ON(bytes_to_transfer > 3);
 275                 val = 0;
 276                 for (byte = 0; byte < bytes_to_transfer; byte++)
 277                         val |= (*buf++) << (byte * 8);
 278                 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
 279                 buf_remaining -= bytes_to_transfer;
 280                 tx_fifo_avail--;
 281         }
 282         BUG_ON(tx_fifo_avail > 0 && buf_remaining > 0);
 283         i2c_dev->msg_buf_remaining = buf_remaining;
 284         i2c_dev->msg_buf = buf;
 285         return 0;
 286 }
 287
 288 /* One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
 289  * block.  This block is identical to the rest of the I2C blocks, except that
 290  * it only supports master mode, it has registers moved around, and it needs
 291  * some extra init to get it into I2C mode.  The register moves are handled
 292  * by i2c_readl and i2c_writel
 293  */
 294 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
 295 {
 296         u32 val = 0;
 297         val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
 298         val |= DVC_CTRL_REG3_SW_PROG;
 299         val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
 300         dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
 301
 302         val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
 303         val |= DVC_CTRL_REG1_INTR_EN;
 304         dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
 305 }
 306
 307 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
 308 {
 309         u32 val;
 310         int err = 0;
 311
 312         clk_enable(i2c_dev->clk);
 313
 314         tegra_periph_reset_assert(i2c_dev->clk);
 315         udelay(2);
 316         tegra_periph_reset_deassert(i2c_dev->clk);
 317
 318         if (i2c_dev->is_dvc)
 319                 tegra_dvc_init(i2c_dev);
 320
 321         val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN | (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
 322         i2c_writel(i2c_dev, val, I2C_CNFG);
 323         i2c_writel(i2c_dev, 0, I2C_INT_MASK);
 324         tegra_i2c_set_clk(i2c_dev, i2c_dev->last_bus_clk);
 325
 326         val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
 327                 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
 328         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 329
 330         if (tegra_i2c_flush_fifos(i2c_dev))
 331                 err = -ETIMEDOUT;
 332
 333         clk_disable(i2c_dev->clk);
 334
 335 #ifdef DEBUG_TEGRA_I2C_TEMP
 336         atomic_set(&i2c_dev->incmplt_irq_count, 0);
 337 #endif
 338
 339         if (i2c_dev->irq_disabled) {
 340                 i2c_dev->irq_disabled = 0;
 341                 enable_irq(i2c_dev->irq);
 342         }
 343
 344         return 0;
 345 }
 346
 347 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
 348 {
 349         u32 status;
 350         const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 351         struct tegra_i2c_dev *i2c_dev = dev_id;
 352
 353         status = i2c_readl(i2c_dev, I2C_INT_STATUS);
 354
 355 #ifdef DEBUG_TEGRA_I2C_TEMP
 356         if (atomic_inc_return(&i2c_dev->incmplt_irq_count) == 1000) {
 357                 dev_err(i2c_dev->dev, "suspected irq storm\n");
 358                 pr_err("ist=%x im=%x pxst=%x st=%x cfg=%x fst=%x fc=%x\n",
 359                        i2c_readl(i2c_dev, I2C_INT_STATUS),
 360                        i2c_readl(i2c_dev, I2C_INT_MASK),
 361                        i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
 362                        i2c_readl(i2c_dev, I2C_STATUS),
 363                        i2c_readl(i2c_dev, I2C_CNFG),
 364                        i2c_readl(i2c_dev, I2C_FIFO_STATUS),
 365                        i2c_readl(i2c_dev, I2C_FIFO_CONTROL));
 366                 pr_err("mbrm=%d mcmp=%d merr=%d\n",
 367                        i2c_dev->msg_buf_remaining,
 368                        i2c_dev->msg_transfer_complete,
 369                        i2c_dev->msg_err);
 370
 371                 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT << 1;
 372
 373                 if (! i2c_dev->irq_disabled) {
 374                         disable_irq_nosync(i2c_dev->irq);
 375                         i2c_dev->irq_disabled = 1;
 376                 }
 377
 378                 complete(&i2c_dev->msg_complete);
 379                 goto err;
 380         }
 381 #endif
 382
 383         if (status == 0) {
 384                 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
 385                          i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
 386                          i2c_readl(i2c_dev, I2C_STATUS),
 387                          i2c_readl(i2c_dev, I2C_CNFG));
 388                 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 389
 390                 if (! i2c_dev->irq_disabled) {
 391                         disable_irq_nosync(i2c_dev->irq);
 392                         i2c_dev->irq_disabled = 1;
 393                 }
 394
 395                 complete(&i2c_dev->msg_complete);
 396                 goto err;
 397         }
 398
 399         if (unlikely(status & status_err)) {
 400                 if (status & I2C_INT_NO_ACK)
 401                         i2c_dev->msg_err |= I2C_ERR_NO_ACK;
 402                 if (status & I2C_INT_ARBITRATION_LOST)
 403                         i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
 404                 complete(&i2c_dev->msg_complete);
 405                 goto err;
 406         }
 407
 408         if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
 409                 if (i2c_dev->msg_buf_remaining)
 410                         tegra_i2c_empty_rx_fifo(i2c_dev);
 411                 else
 412                         BUG();
 413         }
 414
 415         if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
 416                 if (i2c_dev->msg_buf_remaining)
 417                         tegra_i2c_fill_tx_fifo(i2c_dev);
 418                 else
 419                         tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
 420         }
 421
 422         if (status & I2C_INT_PACKET_XFER_COMPLETE)
 423                 i2c_dev->msg_transfer_complete = 1;
 424
 425         if (i2c_dev->msg_transfer_complete && !i2c_dev->msg_buf_remaining)
 426                 complete(&i2c_dev->msg_complete);
 427         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 428         if (i2c_dev->is_dvc)
 429                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 430         return IRQ_HANDLED;
 431 err:
 432         /* An error occured, mask all interrupts */
 433         tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
 434                 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
 435                 I2C_INT_RX_FIFO_DATA_REQ);
 436         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 437         if (i2c_dev->is_dvc)
 438                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 439         return IRQ_NONE;
 440 }
 441
 442 static int tegra_i2c_xfer_msg(struct tegra_i2c_bus *i2c_bus,
 443         struct i2c_msg *msg, int stop)
 444 {
 445         struct tegra_i2c_dev *i2c_dev = i2c_bus->dev;
 446         u32 packet_header;
 447         u32 int_mask;
 448         int ret;
 449
 450         tegra_i2c_flush_fifos(i2c_dev);
 451         i2c_writel(i2c_dev, 0xFF, I2C_INT_STATUS);
 452
 453         if (msg->len == 0)
 454                 return -EINVAL;
 455
 456         i2c_dev->msg_buf = msg->buf;
 457         i2c_dev->msg_buf_remaining = msg->len;
 458         i2c_dev->msg_err = I2C_ERR_NONE;
 459         i2c_dev->msg_transfer_complete = 0;
 460         i2c_dev->msg_read = (msg->flags & I2C_M_RD);
 461         INIT_COMPLETION(i2c_dev->msg_complete);
 462
 463         packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
 464                         PACKET_HEADER0_PROTOCOL_I2C |
 465                         (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
 466                         (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
 467         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 468
 469         packet_header = msg->len - 1;
 470         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 471
 472         packet_header = msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
 473         packet_header |= I2C_HEADER_IE_ENABLE;
 474         if (!stop)
 475                 packet_header |= I2C_HEADER_REPEAT_START;
 476         if (msg->flags & I2C_M_TEN)
 477                 packet_header |= I2C_HEADER_10BIT_ADDR;
 478         if (msg->flags & I2C_M_IGNORE_NAK)
 479                 packet_header |= I2C_HEADER_CONT_ON_NAK;
 480         if (msg->flags & I2C_M_RD)
 481                 packet_header |= I2C_HEADER_READ;
 482         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 483
 484         if (!(msg->flags & I2C_M_RD))
 485                 tegra_i2c_fill_tx_fifo(i2c_dev);
 486
 487         int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 488         if (msg->flags & I2C_M_RD)
 489                 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
 490         else if (i2c_dev->msg_buf_remaining)
 491                 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
 492         tegra_i2c_unmask_irq(i2c_dev, int_mask);
 493         pr_debug("unmasked irq: %02x\n", i2c_readl(i2c_dev, I2C_INT_MASK));
 494
 495         ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT);
 496         tegra_i2c_mask_irq(i2c_dev, int_mask);
 497
 498 #ifdef DEBUG_TEGRA_I2C_TEMP
 499         atomic_set(&i2c_dev->incmplt_irq_count, 0);
 500 #endif
 501
 502         if (WARN_ON(ret == 0)) {
 503                 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
 504 #ifdef DEBUG_TEGRA_I2C_TEMP
 505                 pr_err("ist=%x im=%x pxst=%x st=%x cfg=%x fst=%x fc=%x\n",
 506                        i2c_readl(i2c_dev, I2C_INT_STATUS),
 507                        i2c_readl(i2c_dev, I2C_INT_MASK),
 508                        i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
 509                        i2c_readl(i2c_dev, I2C_STATUS),
 510                        i2c_readl(i2c_dev, I2C_CNFG),
 511                        i2c_readl(i2c_dev, I2C_FIFO_STATUS),
 512                        i2c_readl(i2c_dev, I2C_FIFO_CONTROL));
 513                 pr_err("mbrm=%d mcmp=%d merr=%d\n",
 514                        i2c_dev->msg_buf_remaining,
 515                        i2c_dev->msg_transfer_complete,
 516                        i2c_dev->msg_err);
 517                 pr_err("madr=%x mlen=%d mfl=%x stop=%d\n", msg->addr, msg->len,
 518                        msg->flags, stop);
 519 #endif
 520                 tegra_i2c_init(i2c_dev);
 521                 return -ETIMEDOUT;
 522         }
 523
 524         pr_debug("transfer complete: %d %d %d\n", ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
 525
 526         if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
 527                 return 0;
 528
 529         tegra_i2c_init(i2c_dev);
 530         if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
 531                 if (msg->flags & I2C_M_IGNORE_NAK)
 532                         return 0;
 533                 return -EREMOTEIO;
 534         }
 535
 536         return -EIO;
 537 }
 538
 539 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
 540         int num)
 541 {
 542         struct tegra_i2c_bus *i2c_bus = i2c_get_adapdata(adap);
 543         struct tegra_i2c_dev *i2c_dev = i2c_bus->dev;
 544         int i;
 545         int ret = 0;
 546
 547         if (i2c_dev->is_suspended)
 548                 return -EBUSY;
 549
 550         rt_mutex_lock(&i2c_dev->dev_lock);
 551
 552         if (i2c_dev->last_mux != i2c_bus->mux) {
 553                 tegra_pinmux_set_safe_pinmux_table(i2c_dev->last_mux,
 554                         i2c_dev->last_mux_len);
 555                 tegra_pinmux_config_pinmux_table(i2c_bus->mux,
 556                         i2c_bus->mux_len);
 557                 i2c_dev->last_mux = i2c_bus->mux;
 558                 i2c_dev->last_mux_len = i2c_bus->mux_len;
 559         }
 560
 561         if (i2c_dev->last_bus_clk != i2c_bus->bus_clk_rate) {
 562                 tegra_i2c_set_clk(i2c_dev, i2c_bus->bus_clk_rate);
 563                 i2c_dev->last_bus_clk = i2c_bus->bus_clk_rate;
 564         }
 565
 566         clk_enable(i2c_dev->clk);
 567         for (i = 0; i < num; i++) {
 568                 int stop = (i == (num - 1)) ? 1  : 0;
 569                 ret = tegra_i2c_xfer_msg(i2c_bus, &msgs[i], stop);
 570                 if (ret)
 571                         goto out;
 572         }
 573         ret = i;
 574
 575 out:
 576         clk_disable(i2c_dev->clk);
 577
 578         rt_mutex_unlock(&i2c_dev->dev_lock);
 579
 580         return ret;
 581 }
 582
 583 static u32 tegra_i2c_func(struct i2c_adapter *adap)
 584 {
 585         /* FIXME: For now keep it simple and don't support protocol mangling
 586            features */
 587         return I2C_FUNC_I2C;
 588 }
 589
 590 static const struct i2c_algorithm tegra_i2c_algo = {
 591         .master_xfer    = tegra_i2c_xfer,
 592         .functionality  = tegra_i2c_func,
 593 };
 594
 595 static int tegra_i2c_probe(struct platform_device *pdev)
 596 {
 597         struct tegra_i2c_dev *i2c_dev;
 598         struct tegra_i2c_platform_data *plat = pdev->dev.platform_data;
 599         struct resource *res;
 600         struct resource *iomem;
 601         struct clk *clk;
 602         struct clk *i2c_clk;
 603         void *base;
 604         int irq;
 605         int nbus;
 606         int i = 0;
 607         int ret = 0;
 608
 609         if (!plat) {
 610                 dev_err(&pdev->dev, "no platform data?\n");
 611                 return -ENODEV;
 612         }
 613
 614         if (plat->bus_count <= 0 || plat->adapter_nr < 0) {
 615                 dev_err(&pdev->dev, "invalid platform data?\n");
 616                 return -ENODEV;
 617         }
 618
 619         WARN_ON(plat->bus_count > TEGRA_I2C_MAX_BUS);
 620         nbus = min(TEGRA_I2C_MAX_BUS, plat->bus_count);
 621
 622         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 623         if (!res) {
 624                 dev_err(&pdev->dev, "no mem resource?\n");
 625                 return -ENODEV;
 626         }
 627         iomem = request_mem_region(res->start, resource_size(res), pdev->name);
 628         if (!iomem) {
 629                 dev_err(&pdev->dev, "I2C region already claimed\n");
 630                 return -EBUSY;
 631         }
 632
 633         base = ioremap(iomem->start, resource_size(iomem));
 634         if (!base) {
 635                 dev_err(&pdev->dev, "Can't ioremap I2C region\n");
 636                 return -ENOMEM;
 637         }
 638
 639         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 640         if (!res) {
 641                 dev_err(&pdev->dev, "no irq resource?\n");
 642                 ret = -ENODEV;
 643                 goto err_iounmap;
 644         }
 645         irq = res->start;
 646
 647         clk = clk_get(&pdev->dev, NULL);
 648         if (!clk) {
 649                 ret = -ENOMEM;
 650                 goto err_release_region;
 651         }
 652
 653         i2c_clk = clk_get(&pdev->dev, "i2c");
 654         if (!i2c_clk) {
 655                 ret = -ENOMEM;
 656                 goto err_clk_put;
 657         }
 658
 659         i2c_dev = kzalloc(sizeof(struct tegra_i2c_dev) +
 660                           (nbus-1) * sizeof(struct tegra_i2c_bus), GFP_KERNEL);
 661         if (!i2c_dev) {
 662                 ret = -ENOMEM;
 663                 goto err_i2c_clk_put;
 664         }
 665
 666         i2c_dev->base = base;
 667         i2c_dev->clk = clk;
 668         i2c_dev->i2c_clk = i2c_clk;
 669         i2c_dev->iomem = iomem;
 670         i2c_dev->irq = irq;
 671         i2c_dev->cont_id = pdev->id;
 672         i2c_dev->dev = &pdev->dev;
 673         i2c_dev->last_bus_clk = plat->bus_clk_rate[0] ?: 100000;
 674         rt_mutex_init(&i2c_dev->dev_lock);
 675
 676         i2c_dev->is_dvc = plat->is_dvc;
 677         init_completion(&i2c_dev->msg_complete);
 678
 679         platform_set_drvdata(pdev, i2c_dev);
 680
 681         ret = tegra_i2c_init(i2c_dev);
 682         if (ret)
 683                 goto err_free;
 684
 685         ret = request_irq(i2c_dev->irq, tegra_i2c_isr, IRQF_DISABLED,
 686                 pdev->name, i2c_dev);
 687         if (ret) {
 688                 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
 689                 goto err_free;
 690         }
 691
 692         clk_enable(i2c_dev->i2c_clk);
 693
 694         for (i = 0; i < nbus; i++) {
 695                 struct tegra_i2c_bus *i2c_bus = &i2c_dev->busses[i];
 696
 697                 i2c_bus->dev = i2c_dev;
 698                 i2c_bus->mux = plat->bus_mux[i];
 699                 i2c_bus->mux_len = plat->bus_mux_len[i];
 700                 i2c_bus->bus_clk_rate = plat->bus_clk_rate[i] ?: 100000;
 701
 702                 i2c_bus->adapter.algo = &tegra_i2c_algo;
 703                 i2c_set_adapdata(&i2c_bus->adapter, i2c_bus);
 704                 i2c_bus->adapter.owner = THIS_MODULE;
 705                 i2c_bus->adapter.class = I2C_CLASS_HWMON;
 706                 strlcpy(i2c_bus->adapter.name, "Tegra I2C adapter",
 707                         sizeof(i2c_bus->adapter.name));
 708                 i2c_bus->adapter.dev.parent = &pdev->dev;
 709                 i2c_bus->adapter.nr = plat->adapter_nr + i;
 710                 ret = i2c_add_numbered_adapter(&i2c_bus->adapter);
 711                 if (ret) {
 712                         dev_err(&pdev->dev, "Failed to add I2C adapter\n");
 713                         goto err_del_bus;
 714                 }
 715                 i2c_dev->bus_count++;
 716         }
 717
 718         return 0;
 719
 720 err_del_bus:
 721         while (i2c_dev->bus_count--)
 722                 i2c_del_adapter(&i2c_dev->busses[i2c_dev->bus_count].adapter);
 723         free_irq(i2c_dev->irq, i2c_dev);
 724 err_free:
 725         kfree(i2c_dev);
 726 err_i2c_clk_put:
 727         clk_put(i2c_clk);
 728 err_clk_put:
 729         clk_put(clk);
 730 err_release_region:
 731         release_mem_region(iomem->start, resource_size(iomem));
 732 err_iounmap:
 733         iounmap(base);
 734         return ret;
 735 }
 736
 737 static int tegra_i2c_remove(struct platform_device *pdev)
 738 {
 739         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 740         while (i2c_dev->bus_count--)
 741                 i2c_del_adapter(&i2c_dev->busses[i2c_dev->bus_count].adapter);
 742
 743         free_irq(i2c_dev->irq, i2c_dev);
 744         clk_put(i2c_dev->i2c_clk);
 745         clk_put(i2c_dev->clk);
 746         release_mem_region(i2c_dev->iomem->start,
 747                 resource_size(i2c_dev->iomem));
 748         iounmap(i2c_dev->base);
 749         kfree(i2c_dev);
 750         return 0;
 751 }
 752
 753 #ifdef CONFIG_PM
 754 static int tegra_i2c_suspend(struct platform_device *pdev, pm_message_t state)
 755 {
 756         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 757
 758         rt_mutex_lock(&i2c_dev->dev_lock);
 759         i2c_dev->is_suspended = true;
 760         rt_mutex_unlock(&i2c_dev->dev_lock);
 761
 762         return 0;
 763 }
 764
 765 static int tegra_i2c_resume(struct platform_device *pdev)
 766 {
 767         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 768         int ret;
 769
 770         rt_mutex_lock(&i2c_dev->dev_lock);
 771
 772         ret = tegra_i2c_init(i2c_dev);
 773
 774         if (ret) {
 775                 rt_mutex_unlock(&i2c_dev->dev_lock);
 776                 return ret;
 777         }
 778
 779         i2c_dev->is_suspended = false;
 780
 781         rt_mutex_unlock(&i2c_dev->dev_lock);
 782
 783         return 0;
 784 }
 785 #endif
 786
 787 static struct platform_driver tegra_i2c_driver = {
 788         .probe   = tegra_i2c_probe,
 789         .remove  = tegra_i2c_remove,
 790 #ifdef CONFIG_PM
 791         .suspend = tegra_i2c_suspend,
 792         .resume  = tegra_i2c_resume,
 793 #endif
 794         .driver  = {
 795                 .name  = "tegra-i2c",
 796                 .owner = THIS_MODULE,
 797         },
 798 };
 799
 800 static int __init tegra_i2c_init_driver(void)
 801 {
 802         return platform_driver_register(&tegra_i2c_driver);
 803 }
 804 /*
 805  * Some drivers (hdmi) depend on i2c busses already being present,
 806  * so init at subsys time.
 807  */
 808 subsys_initcall(tegra_i2c_init_driver);
 809
 810 static void __exit tegra_i2c_exit_driver(void)
 811 {
 812         platform_driver_unregister(&tegra_i2c_driver);
 813 }
 814 module_exit(tegra_i2c_exit_driver);