2 * drivers/i2c/busses/i2c-tegra.c
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Colin Cross <ccross@android.com>
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
22 #include <linux/err.h>
23 #include <linux/i2c.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/i2c-tegra.h>
29 #include <linux/of_i2c.h>
30 #include <linux/module.h>
32 #include <asm/unaligned.h>
36 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
37 #define BYTES_PER_FIFO_WORD 4
39 #define I2C_CNFG 0x000
40 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12
41 #define I2C_CNFG_PACKET_MODE_EN (1<<10)
42 #define I2C_CNFG_NEW_MASTER_FSM (1<<11)
43 #define I2C_STATUS 0x01C
44 #define I2C_SL_CNFG 0x020
45 #define I2C_SL_CNFG_NACK (1<<1)
46 #define I2C_SL_CNFG_NEWSL (1<<2)
47 #define I2C_SL_ADDR1 0x02c
48 #define I2C_SL_ADDR2 0x030
49 #define I2C_TX_FIFO 0x050
50 #define I2C_RX_FIFO 0x054
51 #define I2C_PACKET_TRANSFER_STATUS 0x058
52 #define I2C_FIFO_CONTROL 0x05c
53 #define I2C_FIFO_CONTROL_TX_FLUSH (1<<1)
54 #define I2C_FIFO_CONTROL_RX_FLUSH (1<<0)
55 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5
56 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2
57 #define I2C_FIFO_STATUS 0x060
58 #define I2C_FIFO_STATUS_TX_MASK 0xF0
59 #define I2C_FIFO_STATUS_TX_SHIFT 4
60 #define I2C_FIFO_STATUS_RX_MASK 0x0F
61 #define I2C_FIFO_STATUS_RX_SHIFT 0
62 #define I2C_INT_MASK 0x064
63 #define I2C_INT_STATUS 0x068
64 #define I2C_INT_PACKET_XFER_COMPLETE (1<<7)
65 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE (1<<6)
66 #define I2C_INT_TX_FIFO_OVERFLOW (1<<5)
67 #define I2C_INT_RX_FIFO_UNDERFLOW (1<<4)
68 #define I2C_INT_NO_ACK (1<<3)
69 #define I2C_INT_ARBITRATION_LOST (1<<2)
70 #define I2C_INT_TX_FIFO_DATA_REQ (1<<1)
71 #define I2C_INT_RX_FIFO_DATA_REQ (1<<0)
72 #define I2C_CLK_DIVISOR 0x06c
74 #define DVC_CTRL_REG1 0x000
75 #define DVC_CTRL_REG1_INTR_EN (1<<10)
76 #define DVC_CTRL_REG2 0x004
77 #define DVC_CTRL_REG3 0x008
78 #define DVC_CTRL_REG3_SW_PROG (1<<26)
79 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN (1<<30)
80 #define DVC_STATUS 0x00c
81 #define DVC_STATUS_I2C_DONE_INTR (1<<30)
83 #define I2C_ERR_NONE 0x00
84 #define I2C_ERR_NO_ACK 0x01
85 #define I2C_ERR_ARBITRATION_LOST 0x02
86 #define I2C_ERR_UNKNOWN_INTERRUPT 0x04
88 #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28
89 #define PACKET_HEADER0_PACKET_ID_SHIFT 16
90 #define PACKET_HEADER0_CONT_ID_SHIFT 12
91 #define PACKET_HEADER0_PROTOCOL_I2C (1<<4)
93 #define I2C_HEADER_HIGHSPEED_MODE (1<<22)
94 #define I2C_HEADER_CONT_ON_NAK (1<<21)
95 #define I2C_HEADER_SEND_START_BYTE (1<<20)
96 #define I2C_HEADER_READ (1<<19)
97 #define I2C_HEADER_10BIT_ADDR (1<<18)
98 #define I2C_HEADER_IE_ENABLE (1<<17)
99 #define I2C_HEADER_REPEAT_START (1<<16)
100 #define I2C_HEADER_CONTINUE_XFER (1<<15)
101 #define I2C_HEADER_MASTER_ADDR_SHIFT 12
102 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1
104 * msg_end_type: The bus control which need to be send at end of transfer.
105 * @MSG_END_STOP: Send stop pulse at end of transfer.
106 * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
107 * @MSG_END_CONTINUE: The following on message is coming and so do not send
108 * stop or repeat start.
112 MSG_END_REPEAT_START,
117 * struct tegra_i2c_dev - per device i2c context
118 * @dev: device reference for power management
119 * @adapter: core i2c layer adapter information
120 * @clk: clock reference for i2c controller
121 * @i2c_clk: clock reference for i2c bus
122 * @base: ioremapped registers cookie
123 * @cont_id: i2c controller id, used for for packet header
124 * @irq: irq number of transfer complete interrupt
125 * @is_dvc: identifies the DVC i2c controller, has a different register layout
126 * @msg_complete: transfer completion notifier
127 * @msg_err: error code for completed message
128 * @msg_buf: pointer to current message data
129 * @msg_buf_remaining: size of unsent data in the message buffer
130 * @msg_read: identifies read transfers
131 * @bus_clk_rate: current i2c bus clock rate
132 * @is_suspended: prevents i2c controller accesses after suspend is called
134 struct tegra_i2c_dev {
136 struct i2c_adapter adapter;
144 struct completion msg_complete;
147 size_t msg_buf_remaining;
149 unsigned long bus_clk_rate;
153 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
155 writel(val, i2c_dev->base + reg);
158 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
160 return readl(i2c_dev->base + reg);
164 * i2c_writel and i2c_readl will offset the register if necessary to talk
165 * to the I2C block inside the DVC block
167 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
171 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
175 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
178 writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
180 /* Read back register to make sure that register writes completed */
181 if (reg != I2C_TX_FIFO)
182 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
185 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
187 return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
190 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
191 unsigned long reg, int len)
193 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
196 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
197 unsigned long reg, int len)
199 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
202 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
204 u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
206 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
209 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
211 u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
213 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
216 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
218 unsigned long timeout = jiffies + HZ;
219 u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
220 val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
221 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
223 while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
224 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
225 if (time_after(jiffies, timeout)) {
226 dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
234 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
238 u8 *buf = i2c_dev->msg_buf;
239 size_t buf_remaining = i2c_dev->msg_buf_remaining;
240 int words_to_transfer;
242 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
243 rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
244 I2C_FIFO_STATUS_RX_SHIFT;
246 /* Rounds down to not include partial word at the end of buf */
247 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
248 if (words_to_transfer > rx_fifo_avail)
249 words_to_transfer = rx_fifo_avail;
251 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
253 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
254 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
255 rx_fifo_avail -= words_to_transfer;
258 * If there is a partial word at the end of buf, handle it manually to
259 * prevent overwriting past the end of buf
261 if (rx_fifo_avail > 0 && buf_remaining > 0) {
262 BUG_ON(buf_remaining > 3);
263 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
264 memcpy(buf, &val, buf_remaining);
269 BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
270 i2c_dev->msg_buf_remaining = buf_remaining;
271 i2c_dev->msg_buf = buf;
275 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
279 u8 *buf = i2c_dev->msg_buf;
280 size_t buf_remaining = i2c_dev->msg_buf_remaining;
281 int words_to_transfer;
283 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
284 tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
285 I2C_FIFO_STATUS_TX_SHIFT;
287 /* Rounds down to not include partial word at the end of buf */
288 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
290 /* It's very common to have < 4 bytes, so optimize that case. */
291 if (words_to_transfer) {
292 if (words_to_transfer > tx_fifo_avail)
293 words_to_transfer = tx_fifo_avail;
296 * Update state before writing to FIFO. If this casues us
297 * to finish writing all bytes (AKA buf_remaining goes to 0) we
298 * have a potential for an interrupt (PACKET_XFER_COMPLETE is
299 * not maskable). We need to make sure that the isr sees
300 * buf_remaining as 0 and doesn't call us back re-entrantly.
302 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
303 tx_fifo_avail -= words_to_transfer;
304 i2c_dev->msg_buf_remaining = buf_remaining;
305 i2c_dev->msg_buf = buf +
306 words_to_transfer * BYTES_PER_FIFO_WORD;
309 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
311 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
315 * If there is a partial word at the end of buf, handle it manually to
316 * prevent reading past the end of buf, which could cross a page
317 * boundary and fault.
319 if (tx_fifo_avail > 0 && buf_remaining > 0) {
320 BUG_ON(buf_remaining > 3);
321 memcpy(&val, buf, buf_remaining);
323 /* Again update before writing to FIFO to make sure isr sees. */
324 i2c_dev->msg_buf_remaining = 0;
325 i2c_dev->msg_buf = NULL;
328 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
335 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
336 * block. This block is identical to the rest of the I2C blocks, except that
337 * it only supports master mode, it has registers moved around, and it needs
338 * some extra init to get it into I2C mode. The register moves are handled
339 * by i2c_readl and i2c_writel
341 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
344 val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
345 val |= DVC_CTRL_REG3_SW_PROG;
346 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
347 dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
349 val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
350 val |= DVC_CTRL_REG1_INTR_EN;
351 dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
354 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
359 clk_prepare_enable(i2c_dev->clk);
361 tegra_periph_reset_assert(i2c_dev->clk);
363 tegra_periph_reset_deassert(i2c_dev->clk);
366 tegra_dvc_init(i2c_dev);
368 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
369 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
370 i2c_writel(i2c_dev, val, I2C_CNFG);
371 i2c_writel(i2c_dev, 0, I2C_INT_MASK);
372 clk_set_rate(i2c_dev->clk, i2c_dev->bus_clk_rate * 8);
374 if (!i2c_dev->is_dvc) {
375 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
376 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
377 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
378 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
379 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
383 val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
384 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
385 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
387 if (tegra_i2c_flush_fifos(i2c_dev))
390 clk_disable_unprepare(i2c_dev->clk);
392 if (i2c_dev->irq_disabled) {
393 i2c_dev->irq_disabled = 0;
394 enable_irq(i2c_dev->irq);
400 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
403 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
404 struct tegra_i2c_dev *i2c_dev = dev_id;
406 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
409 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
410 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
411 i2c_readl(i2c_dev, I2C_STATUS),
412 i2c_readl(i2c_dev, I2C_CNFG));
413 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
415 if (!i2c_dev->irq_disabled) {
416 disable_irq_nosync(i2c_dev->irq);
417 i2c_dev->irq_disabled = 1;
422 if (unlikely(status & status_err)) {
423 if (status & I2C_INT_NO_ACK)
424 i2c_dev->msg_err |= I2C_ERR_NO_ACK;
425 if (status & I2C_INT_ARBITRATION_LOST)
426 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
430 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
431 if (i2c_dev->msg_buf_remaining)
432 tegra_i2c_empty_rx_fifo(i2c_dev);
437 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
438 if (i2c_dev->msg_buf_remaining)
439 tegra_i2c_fill_tx_fifo(i2c_dev);
441 tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
444 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
446 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
448 if (status & I2C_INT_PACKET_XFER_COMPLETE) {
449 BUG_ON(i2c_dev->msg_buf_remaining);
450 complete(&i2c_dev->msg_complete);
454 /* An error occurred, mask all interrupts */
455 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
456 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
457 I2C_INT_RX_FIFO_DATA_REQ);
458 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
460 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
462 complete(&i2c_dev->msg_complete);
466 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
467 struct i2c_msg *msg, enum msg_end_type end_state)
473 tegra_i2c_flush_fifos(i2c_dev);
478 i2c_dev->msg_buf = msg->buf;
479 i2c_dev->msg_buf_remaining = msg->len;
480 i2c_dev->msg_err = I2C_ERR_NONE;
481 i2c_dev->msg_read = (msg->flags & I2C_M_RD);
482 INIT_COMPLETION(i2c_dev->msg_complete);
484 packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
485 PACKET_HEADER0_PROTOCOL_I2C |
486 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
487 (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
488 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
490 packet_header = msg->len - 1;
491 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
493 packet_header = I2C_HEADER_IE_ENABLE;
494 if (end_state == MSG_END_CONTINUE)
495 packet_header |= I2C_HEADER_CONTINUE_XFER;
496 else if (end_state == MSG_END_REPEAT_START)
497 packet_header |= I2C_HEADER_REPEAT_START;
498 if (msg->flags & I2C_M_TEN) {
499 packet_header |= msg->addr;
500 packet_header |= I2C_HEADER_10BIT_ADDR;
502 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
504 if (msg->flags & I2C_M_IGNORE_NAK)
505 packet_header |= I2C_HEADER_CONT_ON_NAK;
506 if (msg->flags & I2C_M_RD)
507 packet_header |= I2C_HEADER_READ;
508 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
510 if (!(msg->flags & I2C_M_RD))
511 tegra_i2c_fill_tx_fifo(i2c_dev);
513 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
514 if (msg->flags & I2C_M_RD)
515 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
516 else if (i2c_dev->msg_buf_remaining)
517 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
518 tegra_i2c_unmask_irq(i2c_dev, int_mask);
519 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
520 i2c_readl(i2c_dev, I2C_INT_MASK));
522 ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT);
523 tegra_i2c_mask_irq(i2c_dev, int_mask);
525 if (WARN_ON(ret == 0)) {
526 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
528 tegra_i2c_init(i2c_dev);
532 dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n",
533 ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
535 if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
539 * NACK interrupt is generated before the I2C controller generates the
540 * STOP condition on the bus. So wait for 2 clock periods before resetting
541 * the controller so that STOP condition has been delivered properly.
543 if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
544 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
546 tegra_i2c_init(i2c_dev);
547 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
548 if (msg->flags & I2C_M_IGNORE_NAK)
556 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
559 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
563 if (i2c_dev->is_suspended)
566 clk_prepare_enable(i2c_dev->clk);
567 for (i = 0; i < num; i++) {
568 enum msg_end_type end_type = MSG_END_STOP;
570 if (msgs[i + 1].flags & I2C_M_NOSTART)
571 end_type = MSG_END_CONTINUE;
573 end_type = MSG_END_REPEAT_START;
575 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
579 clk_disable_unprepare(i2c_dev->clk);
583 static u32 tegra_i2c_func(struct i2c_adapter *adap)
585 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR |
586 I2C_FUNC_PROTOCOL_MANGLING | I2C_FUNC_NOSTART;
589 static const struct i2c_algorithm tegra_i2c_algo = {
590 .master_xfer = tegra_i2c_xfer,
591 .functionality = tegra_i2c_func,
594 static int __devinit tegra_i2c_probe(struct platform_device *pdev)
596 struct tegra_i2c_dev *i2c_dev;
597 struct tegra_i2c_platform_data *pdata = pdev->dev.platform_data;
598 struct resource *res;
601 const unsigned int *prop;
606 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
608 dev_err(&pdev->dev, "no mem resource\n");
612 base = devm_request_and_ioremap(&pdev->dev, res);
614 dev_err(&pdev->dev, "Cannot request/ioremap I2C registers\n");
615 return -EADDRNOTAVAIL;
618 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
620 dev_err(&pdev->dev, "no irq resource\n");
625 clk = devm_clk_get(&pdev->dev, NULL);
627 dev_err(&pdev->dev, "missing controller clock");
631 i2c_clk = devm_clk_get(&pdev->dev, "i2c");
632 if (IS_ERR(i2c_clk)) {
633 dev_err(&pdev->dev, "missing bus clock");
634 return PTR_ERR(i2c_clk);
637 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
639 dev_err(&pdev->dev, "Could not allocate struct tegra_i2c_dev");
643 i2c_dev->base = base;
645 i2c_dev->i2c_clk = i2c_clk;
646 i2c_dev->adapter.algo = &tegra_i2c_algo;
648 i2c_dev->cont_id = pdev->id;
649 i2c_dev->dev = &pdev->dev;
651 i2c_dev->bus_clk_rate = 100000; /* default clock rate */
653 i2c_dev->bus_clk_rate = pdata->bus_clk_rate;
655 } else if (i2c_dev->dev->of_node) { /* if there is a device tree node ... */
656 prop = of_get_property(i2c_dev->dev->of_node,
657 "clock-frequency", NULL);
659 i2c_dev->bus_clk_rate = be32_to_cpup(prop);
662 if (pdev->dev.of_node)
663 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
664 "nvidia,tegra20-i2c-dvc");
665 else if (pdev->id == 3)
667 init_completion(&i2c_dev->msg_complete);
669 platform_set_drvdata(pdev, i2c_dev);
671 ret = tegra_i2c_init(i2c_dev);
673 dev_err(&pdev->dev, "Failed to initialize i2c controller");
677 ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
678 tegra_i2c_isr, 0, pdev->name, i2c_dev);
680 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
684 clk_prepare_enable(i2c_dev->i2c_clk);
686 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
687 i2c_dev->adapter.owner = THIS_MODULE;
688 i2c_dev->adapter.class = I2C_CLASS_HWMON;
689 strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",
690 sizeof(i2c_dev->adapter.name));
691 i2c_dev->adapter.algo = &tegra_i2c_algo;
692 i2c_dev->adapter.dev.parent = &pdev->dev;
693 i2c_dev->adapter.nr = pdev->id;
694 i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
696 ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
698 dev_err(&pdev->dev, "Failed to add I2C adapter\n");
699 clk_disable_unprepare(i2c_dev->i2c_clk);
703 of_i2c_register_devices(&i2c_dev->adapter);
708 static int __devexit tegra_i2c_remove(struct platform_device *pdev)
710 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
711 i2c_del_adapter(&i2c_dev->adapter);
716 static int tegra_i2c_suspend(struct device *dev)
718 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
720 i2c_lock_adapter(&i2c_dev->adapter);
721 i2c_dev->is_suspended = true;
722 i2c_unlock_adapter(&i2c_dev->adapter);
727 static int tegra_i2c_resume(struct device *dev)
729 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
732 i2c_lock_adapter(&i2c_dev->adapter);
734 ret = tegra_i2c_init(i2c_dev);
737 i2c_unlock_adapter(&i2c_dev->adapter);
741 i2c_dev->is_suspended = false;
743 i2c_unlock_adapter(&i2c_dev->adapter);
748 static SIMPLE_DEV_PM_OPS(tegra_i2c_pm, tegra_i2c_suspend, tegra_i2c_resume);
749 #define TEGRA_I2C_PM (&tegra_i2c_pm)
751 #define TEGRA_I2C_PM NULL
754 #if defined(CONFIG_OF)
755 /* Match table for of_platform binding */
756 static const struct of_device_id tegra_i2c_of_match[] __devinitconst = {
757 { .compatible = "nvidia,tegra20-i2c", },
758 { .compatible = "nvidia,tegra20-i2c-dvc", },
761 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
764 static struct platform_driver tegra_i2c_driver = {
765 .probe = tegra_i2c_probe,
766 .remove = __devexit_p(tegra_i2c_remove),
769 .owner = THIS_MODULE,
770 .of_match_table = of_match_ptr(tegra_i2c_of_match),
775 static int __init tegra_i2c_init_driver(void)
777 return platform_driver_register(&tegra_i2c_driver);
780 static void __exit tegra_i2c_exit_driver(void)
782 platform_driver_unregister(&tegra_i2c_driver);
785 subsys_initcall(tegra_i2c_init_driver);
786 module_exit(tegra_i2c_exit_driver);
788 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
789 MODULE_AUTHOR("Colin Cross");
790 MODULE_LICENSE("GPL v2");