1 /* linux/drivers/i2c/busses/i2c-s3c2410.c
3 * Copyright (C) 2004,2005,2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2410 I2C Controller
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/module.h>
22 #include <linux/i2c.h>
23 #include <linux/init.h>
24 #include <linux/time.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/errno.h>
28 #include <linux/err.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/clk.h>
32 #include <linux/cpufreq.h>
33 #include <linux/slab.h>
36 #include <linux/of_gpio.h>
37 #include <linux/pinctrl/consumer.h>
41 #include <linux/platform_data/i2c-s3c2410.h>
43 /* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
45 #define S3C2410_IICCON 0x00
46 #define S3C2410_IICSTAT 0x04
47 #define S3C2410_IICADD 0x08
48 #define S3C2410_IICDS 0x0C
49 #define S3C2440_IICLC 0x10
51 #define S3C2410_IICCON_ACKEN (1 << 7)
52 #define S3C2410_IICCON_TXDIV_16 (0 << 6)
53 #define S3C2410_IICCON_TXDIV_512 (1 << 6)
54 #define S3C2410_IICCON_IRQEN (1 << 5)
55 #define S3C2410_IICCON_IRQPEND (1 << 4)
56 #define S3C2410_IICCON_SCALE(x) ((x) & 0xf)
57 #define S3C2410_IICCON_SCALEMASK (0xf)
59 #define S3C2410_IICSTAT_MASTER_RX (2 << 6)
60 #define S3C2410_IICSTAT_MASTER_TX (3 << 6)
61 #define S3C2410_IICSTAT_SLAVE_RX (0 << 6)
62 #define S3C2410_IICSTAT_SLAVE_TX (1 << 6)
63 #define S3C2410_IICSTAT_MODEMASK (3 << 6)
65 #define S3C2410_IICSTAT_START (1 << 5)
66 #define S3C2410_IICSTAT_BUSBUSY (1 << 5)
67 #define S3C2410_IICSTAT_TXRXEN (1 << 4)
68 #define S3C2410_IICSTAT_ARBITR (1 << 3)
69 #define S3C2410_IICSTAT_ASSLAVE (1 << 2)
70 #define S3C2410_IICSTAT_ADDR0 (1 << 1)
71 #define S3C2410_IICSTAT_LASTBIT (1 << 0)
73 #define S3C2410_IICLC_SDA_DELAY0 (0 << 0)
74 #define S3C2410_IICLC_SDA_DELAY5 (1 << 0)
75 #define S3C2410_IICLC_SDA_DELAY10 (2 << 0)
76 #define S3C2410_IICLC_SDA_DELAY15 (3 << 0)
77 #define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0)
79 #define S3C2410_IICLC_FILTER_ON (1 << 2)
81 /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */
82 #define QUIRK_S3C2440 (1 << 0)
83 #define QUIRK_HDMIPHY (1 << 1)
84 #define QUIRK_NO_GPIO (1 << 2)
85 #define QUIRK_POLL (1 << 3)
87 /* Max time to wait for bus to become idle after a xfer (in us) */
88 #define S3C2410_IDLE_TIMEOUT 5000
90 /* i2c controller state */
91 enum s3c24xx_i2c_state {
100 wait_queue_head_t wait;
101 kernel_ulong_t quirks;
102 unsigned int suspended:1;
105 unsigned int msg_num;
106 unsigned int msg_idx;
107 unsigned int msg_ptr;
109 unsigned int tx_setup;
112 enum s3c24xx_i2c_state state;
113 unsigned long clkrate;
118 struct i2c_adapter adap;
120 struct s3c2410_platform_i2c *pdata;
122 struct pinctrl *pctrl;
123 #if defined(CONFIG_ARM_S3C24XX_CPUFREQ)
124 struct notifier_block freq_transition;
128 static struct platform_device_id s3c24xx_driver_ids[] = {
130 .name = "s3c2410-i2c",
133 .name = "s3c2440-i2c",
134 .driver_data = QUIRK_S3C2440,
136 .name = "s3c2440-hdmiphy-i2c",
137 .driver_data = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO,
140 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
142 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat);
145 static const struct of_device_id s3c24xx_i2c_match[] = {
146 { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
147 { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 },
148 { .compatible = "samsung,s3c2440-hdmiphy-i2c",
149 .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) },
150 { .compatible = "samsung,exynos5440-i2c",
151 .data = (void *)(QUIRK_S3C2440 | QUIRK_NO_GPIO) },
152 { .compatible = "samsung,exynos5-sata-phy-i2c",
153 .data = (void *)(QUIRK_S3C2440 | QUIRK_POLL | QUIRK_NO_GPIO) },
156 MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match);
159 /* s3c24xx_get_device_quirks
161 * Get controller type either from device tree or platform device variant.
164 static inline kernel_ulong_t s3c24xx_get_device_quirks(struct platform_device *pdev)
166 if (pdev->dev.of_node) {
167 const struct of_device_id *match;
168 match = of_match_node(s3c24xx_i2c_match, pdev->dev.of_node);
169 return (kernel_ulong_t)match->data;
172 return platform_get_device_id(pdev)->driver_data;
175 /* s3c24xx_i2c_master_complete
177 * complete the message and wake up the caller, using the given return code,
178 * or zero to mean ok.
181 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
183 dev_dbg(i2c->dev, "master_complete %d\n", ret);
192 if (!(i2c->quirks & QUIRK_POLL))
196 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
200 tmp = readl(i2c->regs + S3C2410_IICCON);
201 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
204 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
208 tmp = readl(i2c->regs + S3C2410_IICCON);
209 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
212 /* irq enable/disable functions */
214 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
218 tmp = readl(i2c->regs + S3C2410_IICCON);
219 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
222 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
226 tmp = readl(i2c->regs + S3C2410_IICCON);
227 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
230 static bool is_ack(struct s3c24xx_i2c *i2c)
234 for (tries = 50; tries; --tries) {
235 if (readl(i2c->regs + S3C2410_IICCON)
236 & S3C2410_IICCON_IRQPEND) {
237 if (!(readl(i2c->regs + S3C2410_IICSTAT)
238 & S3C2410_IICSTAT_LASTBIT))
241 usleep_range(1000, 2000);
243 dev_err(i2c->dev, "ack was not received\n");
247 /* s3c24xx_i2c_message_start
249 * put the start of a message onto the bus
252 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
255 unsigned int addr = (msg->addr & 0x7f) << 1;
257 unsigned long iiccon;
260 stat |= S3C2410_IICSTAT_TXRXEN;
262 if (msg->flags & I2C_M_RD) {
263 stat |= S3C2410_IICSTAT_MASTER_RX;
266 stat |= S3C2410_IICSTAT_MASTER_TX;
268 if (msg->flags & I2C_M_REV_DIR_ADDR)
271 /* todo - check for whether ack wanted or not */
272 s3c24xx_i2c_enable_ack(i2c);
274 iiccon = readl(i2c->regs + S3C2410_IICCON);
275 writel(stat, i2c->regs + S3C2410_IICSTAT);
277 dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
278 writeb(addr, i2c->regs + S3C2410_IICDS);
280 /* delay here to ensure the data byte has gotten onto the bus
281 * before the transaction is started */
283 ndelay(i2c->tx_setup);
285 dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
286 writel(iiccon, i2c->regs + S3C2410_IICCON);
288 stat |= S3C2410_IICSTAT_START;
289 writel(stat, i2c->regs + S3C2410_IICSTAT);
291 if (i2c->quirks & QUIRK_POLL) {
292 while ((i2c->msg_num != 0) && is_ack(i2c)) {
293 i2c_s3c_irq_nextbyte(i2c, stat);
294 stat = readl(i2c->regs + S3C2410_IICSTAT);
296 if (stat & S3C2410_IICSTAT_ARBITR)
297 dev_err(i2c->dev, "deal with arbitration loss\n");
302 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
304 unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
306 dev_dbg(i2c->dev, "STOP\n");
309 * The datasheet says that the STOP sequence should be:
310 * 1) I2CSTAT.5 = 0 - Clear BUSY (or 'generate STOP')
311 * 2) I2CCON.4 = 0 - Clear IRQPEND
312 * 3) Wait until the stop condition takes effect.
313 * 4*) I2CSTAT.4 = 0 - Clear TXRXEN
315 * Where, step "4*" is only for buses with the "HDMIPHY" quirk.
317 * However, after much experimentation, it appears that:
318 * a) normal buses automatically clear BUSY and transition from
319 * Master->Slave when they complete generating a STOP condition.
320 * Therefore, step (3) can be done in doxfer() by polling I2CCON.4
321 * after starting the STOP generation here.
322 * b) HDMIPHY bus does neither, so there is no way to do step 3.
323 * There is no indication when this bus has finished generating
326 * In fact, we have found that as soon as the IRQPEND bit is cleared in
327 * step 2, the HDMIPHY bus generates the STOP condition, and then
328 * immediately starts transferring another data byte, even though the
329 * bus is supposedly stopped. This is presumably because the bus is
330 * still in "Master" mode, and its BUSY bit is still set.
332 * To avoid these extra post-STOP transactions on HDMI phy devices, we
333 * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly,
334 * instead of first generating a proper STOP condition. This should
335 * float SDA & SCK terminating the transfer. Subsequent transfers
336 * start with a proper START condition, and proceed normally.
338 * The HDMIPHY bus is an internal bus that always has exactly two
339 * devices, the host as Master and the HDMIPHY device as the slave.
340 * Skipping the STOP condition has been tested on this bus and works.
342 if (i2c->quirks & QUIRK_HDMIPHY) {
343 /* Stop driving the I2C pins */
344 iicstat &= ~S3C2410_IICSTAT_TXRXEN;
346 /* stop the transfer */
347 iicstat &= ~S3C2410_IICSTAT_START;
349 writel(iicstat, i2c->regs + S3C2410_IICSTAT);
351 i2c->state = STATE_STOP;
353 s3c24xx_i2c_master_complete(i2c, ret);
354 s3c24xx_i2c_disable_irq(i2c);
357 /* helper functions to determine the current state in the set of
358 * messages we are sending */
362 * returns TRUE if the current message is the last in the set
365 static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
367 return i2c->msg_idx >= (i2c->msg_num - 1);
372 * returns TRUE if we this is the last byte in the current message
375 static inline int is_msglast(struct s3c24xx_i2c *i2c)
377 /* msg->len is always 1 for the first byte of smbus block read.
378 * Actual length will be read from slave. More bytes will be
379 * read according to the length then. */
380 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
383 return i2c->msg_ptr == i2c->msg->len-1;
388 * returns TRUE if we reached the end of the current message
391 static inline int is_msgend(struct s3c24xx_i2c *i2c)
393 return i2c->msg_ptr >= i2c->msg->len;
396 /* i2c_s3c_irq_nextbyte
398 * process an interrupt and work out what to do
401 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
407 switch (i2c->state) {
410 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
414 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
415 s3c24xx_i2c_disable_irq(i2c);
419 /* last thing we did was send a start condition on the
420 * bus, or started a new i2c message
423 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
424 !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
425 /* ack was not received... */
427 dev_dbg(i2c->dev, "ack was not received\n");
428 s3c24xx_i2c_stop(i2c, -ENXIO);
432 if (i2c->msg->flags & I2C_M_RD)
433 i2c->state = STATE_READ;
435 i2c->state = STATE_WRITE;
437 /* terminate the transfer if there is nothing to do
438 * as this is used by the i2c probe to find devices. */
440 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
441 s3c24xx_i2c_stop(i2c, 0);
445 if (i2c->state == STATE_READ)
448 /* fall through to the write state, as we will need to
449 * send a byte as well */
452 /* we are writing data to the device... check for the
453 * end of the message, and if so, work out what to do
456 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
457 if (iicstat & S3C2410_IICSTAT_LASTBIT) {
458 dev_dbg(i2c->dev, "WRITE: No Ack\n");
460 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
467 if (!is_msgend(i2c)) {
468 byte = i2c->msg->buf[i2c->msg_ptr++];
469 writeb(byte, i2c->regs + S3C2410_IICDS);
471 /* delay after writing the byte to allow the
472 * data setup time on the bus, as writing the
473 * data to the register causes the first bit
474 * to appear on SDA, and SCL will change as
475 * soon as the interrupt is acknowledged */
477 ndelay(i2c->tx_setup);
479 } else if (!is_lastmsg(i2c)) {
480 /* we need to go to the next i2c message */
482 dev_dbg(i2c->dev, "WRITE: Next Message\n");
488 /* check to see if we need to do another message */
489 if (i2c->msg->flags & I2C_M_NOSTART) {
491 if (i2c->msg->flags & I2C_M_RD) {
492 /* cannot do this, the controller
493 * forces us to send a new START
494 * when we change direction */
496 s3c24xx_i2c_stop(i2c, -EINVAL);
501 /* send the new start */
502 s3c24xx_i2c_message_start(i2c, i2c->msg);
503 i2c->state = STATE_START;
509 s3c24xx_i2c_stop(i2c, 0);
514 /* we have a byte of data in the data register, do
515 * something with it, and then work out whether we are
516 * going to do any more read/write
519 byte = readb(i2c->regs + S3C2410_IICDS);
520 i2c->msg->buf[i2c->msg_ptr++] = byte;
522 /* Add actual length to read for smbus block read */
523 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
524 i2c->msg->len += byte;
526 if (is_msglast(i2c)) {
527 /* last byte of buffer */
530 s3c24xx_i2c_disable_ack(i2c);
532 } else if (is_msgend(i2c)) {
533 /* ok, we've read the entire buffer, see if there
534 * is anything else we need to do */
536 if (is_lastmsg(i2c)) {
537 /* last message, send stop and complete */
538 dev_dbg(i2c->dev, "READ: Send Stop\n");
540 s3c24xx_i2c_stop(i2c, 0);
542 /* go to the next transfer */
543 dev_dbg(i2c->dev, "READ: Next Transfer\n");
554 /* acknowlegde the IRQ and get back on with the work */
557 tmp = readl(i2c->regs + S3C2410_IICCON);
558 tmp &= ~S3C2410_IICCON_IRQPEND;
559 writel(tmp, i2c->regs + S3C2410_IICCON);
566 * top level IRQ servicing routine
569 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
571 struct s3c24xx_i2c *i2c = dev_id;
572 unsigned long status;
575 status = readl(i2c->regs + S3C2410_IICSTAT);
577 if (status & S3C2410_IICSTAT_ARBITR) {
578 /* deal with arbitration loss */
579 dev_err(i2c->dev, "deal with arbitration loss\n");
582 if (i2c->state == STATE_IDLE) {
583 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
585 tmp = readl(i2c->regs + S3C2410_IICCON);
586 tmp &= ~S3C2410_IICCON_IRQPEND;
587 writel(tmp, i2c->regs + S3C2410_IICCON);
591 /* pretty much this leaves us with the fact that we've
592 * transmitted or received whatever byte we last sent */
594 i2c_s3c_irq_nextbyte(i2c, status);
601 * Disable the bus so that we won't get any interrupts from now on, or try
602 * to drive any lines. This is the default state when we don't have
603 * anything to send/receive.
605 * If there is an event on the bus, or we have a pre-existing event at
606 * kernel boot time, we may not notice the event and the I2C controller
607 * will lock the bus with the I2C clock line low indefinitely.
609 static inline void s3c24xx_i2c_disable_bus(struct s3c24xx_i2c *i2c)
613 /* Stop driving the I2C pins */
614 tmp = readl(i2c->regs + S3C2410_IICSTAT);
615 tmp &= ~S3C2410_IICSTAT_TXRXEN;
616 writel(tmp, i2c->regs + S3C2410_IICSTAT);
618 /* We don't expect any interrupts now, and don't want send acks */
619 tmp = readl(i2c->regs + S3C2410_IICCON);
620 tmp &= ~(S3C2410_IICCON_IRQEN | S3C2410_IICCON_IRQPEND |
621 S3C2410_IICCON_ACKEN);
622 writel(tmp, i2c->regs + S3C2410_IICCON);
626 /* s3c24xx_i2c_set_master
628 * get the i2c bus for a master transaction
631 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
633 unsigned long iicstat;
636 while (timeout-- > 0) {
637 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
639 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
648 /* s3c24xx_i2c_wait_idle
650 * wait for the i2c bus to become idle.
653 static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c)
655 unsigned long iicstat;
660 /* ensure the stop has been through the bus */
662 dev_dbg(i2c->dev, "waiting for bus idle\n");
664 start = now = ktime_get();
667 * Most of the time, the bus is already idle within a few usec of the
668 * end of a transaction. However, really slow i2c devices can stretch
669 * the clock, delaying STOP generation.
671 * On slower SoCs this typically happens within a very small number of
672 * instructions so busy wait briefly to avoid scheduling overhead.
675 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
676 while ((iicstat & S3C2410_IICSTAT_START) && --spins) {
678 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
682 * If we do get an appreciable delay as a compromise between idle
683 * detection latency for the normal, fast case, and system load in the
684 * slow device case, use an exponential back off in the polling loop,
685 * up to 1/10th of the total timeout, then continue to poll at a
686 * constant rate up to the timeout.
689 while ((iicstat & S3C2410_IICSTAT_START) &&
690 ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) {
691 usleep_range(delay, 2 * delay);
692 if (delay < S3C2410_IDLE_TIMEOUT / 10)
695 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
698 if (iicstat & S3C2410_IICSTAT_START)
699 dev_warn(i2c->dev, "timeout waiting for bus idle\n");
702 /* s3c24xx_i2c_doxfer
704 * this starts an i2c transfer
707 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
708 struct i2c_msg *msgs, int num)
710 unsigned long timeout;
716 ret = s3c24xx_i2c_set_master(i2c);
718 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
727 i2c->state = STATE_START;
729 s3c24xx_i2c_enable_irq(i2c);
730 s3c24xx_i2c_message_start(i2c, msgs);
732 if (i2c->quirks & QUIRK_POLL) {
736 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
741 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
745 /* having these next two as dev_err() makes life very
746 * noisy when doing an i2cdetect */
749 dev_dbg(i2c->dev, "timeout\n");
751 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
753 /* For QUIRK_HDMIPHY, bus is already disabled */
754 if (i2c->quirks & QUIRK_HDMIPHY)
757 s3c24xx_i2c_wait_idle(i2c);
759 s3c24xx_i2c_disable_bus(i2c);
762 i2c->state = STATE_IDLE;
769 * first port of call from the i2c bus code when an message needs
770 * transferring across the i2c bus.
773 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
774 struct i2c_msg *msgs, int num)
776 struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
780 pm_runtime_get_sync(&adap->dev);
781 clk_prepare_enable(i2c->clk);
783 for (retry = 0; retry < adap->retries; retry++) {
785 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
787 if (ret != -EAGAIN) {
788 clk_disable_unprepare(i2c->clk);
789 pm_runtime_put(&adap->dev);
793 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
798 clk_disable_unprepare(i2c->clk);
799 pm_runtime_put(&adap->dev);
803 /* declare our i2c functionality */
804 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
806 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART |
807 I2C_FUNC_PROTOCOL_MANGLING;
810 /* i2c bus registration info */
812 static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
813 .master_xfer = s3c24xx_i2c_xfer,
814 .functionality = s3c24xx_i2c_func,
817 /* s3c24xx_i2c_calcdivisor
819 * return the divisor settings for a given frequency
822 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
823 unsigned int *div1, unsigned int *divs)
825 unsigned int calc_divs = clkin / wanted;
826 unsigned int calc_div1;
828 if (calc_divs > (16*16))
833 calc_divs += calc_div1-1;
834 calc_divs /= calc_div1;
844 return clkin / (calc_divs * calc_div1);
847 /* s3c24xx_i2c_clockrate
849 * work out a divisor for the user requested frequency setting,
850 * either by the requested frequency, or scanning the acceptable
851 * range of frequencies until something is found
854 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
856 struct s3c2410_platform_i2c *pdata = i2c->pdata;
857 unsigned long clkin = clk_get_rate(i2c->clk);
858 unsigned int divs, div1;
859 unsigned long target_frequency;
863 i2c->clkrate = clkin;
864 clkin /= 1000; /* clkin now in KHz */
866 dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency);
868 target_frequency = pdata->frequency ? pdata->frequency : 100000;
870 target_frequency /= 1000; /* Target frequency now in KHz */
872 freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs);
874 if (freq > target_frequency) {
876 "Unable to achieve desired frequency %luKHz." \
877 " Lowest achievable %dKHz\n", target_frequency, freq);
883 iiccon = readl(i2c->regs + S3C2410_IICCON);
884 iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
888 iiccon |= S3C2410_IICCON_TXDIV_512;
890 if (i2c->quirks & QUIRK_POLL)
891 iiccon |= S3C2410_IICCON_SCALE(2);
893 writel(iiccon, i2c->regs + S3C2410_IICCON);
895 if (i2c->quirks & QUIRK_S3C2440) {
896 unsigned long sda_delay;
898 if (pdata->sda_delay) {
899 sda_delay = clkin * pdata->sda_delay;
900 sda_delay = DIV_ROUND_UP(sda_delay, 1000000);
901 sda_delay = DIV_ROUND_UP(sda_delay, 5);
904 sda_delay |= S3C2410_IICLC_FILTER_ON;
908 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay);
909 writel(sda_delay, i2c->regs + S3C2440_IICLC);
915 #if defined(CONFIG_ARM_S3C24XX_CPUFREQ)
917 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
919 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
920 unsigned long val, void *data)
922 struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
927 delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
929 /* if we're post-change and the input clock has slowed down
930 * or at pre-change and the clock is about to speed up, then
931 * adjust our clock rate. <0 is slow, >0 speedup.
934 if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
935 (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
936 i2c_lock_adapter(&i2c->adap);
937 ret = s3c24xx_i2c_clockrate(i2c, &got);
938 i2c_unlock_adapter(&i2c->adap);
941 dev_err(i2c->dev, "cannot find frequency\n");
943 dev_info(i2c->dev, "setting freq %d\n", got);
949 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
951 i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
953 return cpufreq_register_notifier(&i2c->freq_transition,
954 CPUFREQ_TRANSITION_NOTIFIER);
957 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
959 cpufreq_unregister_notifier(&i2c->freq_transition,
960 CPUFREQ_TRANSITION_NOTIFIER);
964 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
969 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
975 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
979 if (i2c->quirks & QUIRK_NO_GPIO)
982 for (idx = 0; idx < 2; idx++) {
983 gpio = of_get_gpio(i2c->dev->of_node, idx);
984 if (!gpio_is_valid(gpio)) {
985 dev_err(i2c->dev, "invalid gpio[%d]: %d\n", idx, gpio);
988 i2c->gpios[idx] = gpio;
990 ret = gpio_request(gpio, "i2c-bus");
992 dev_err(i2c->dev, "gpio [%d] request failed\n", gpio);
1000 gpio_free(i2c->gpios[idx]);
1004 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c)
1008 if (i2c->quirks & QUIRK_NO_GPIO)
1011 for (idx = 0; idx < 2; idx++)
1012 gpio_free(i2c->gpios[idx]);
1015 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
1020 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c)
1027 * initialise the controller, set the IO lines and frequency
1030 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
1032 struct s3c2410_platform_i2c *pdata;
1035 /* get the plafrom data */
1039 /* write slave address */
1041 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
1043 dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
1045 writel(0, i2c->regs + S3C2410_IICCON);
1046 writel(0, i2c->regs + S3C2410_IICSTAT);
1048 /* we need to work out the divisors for the clock... */
1050 if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
1051 dev_err(i2c->dev, "cannot meet bus frequency required\n");
1055 /* todo - check that the i2c lines aren't being dragged anywhere */
1057 dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
1058 dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02x\n",
1059 readl(i2c->regs + S3C2410_IICCON));
1065 /* s3c24xx_i2c_parse_dt
1067 * Parse the device tree node and retreive the platform data.
1071 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
1073 struct s3c2410_platform_i2c *pdata = i2c->pdata;
1078 pdata->bus_num = -1; /* i2c bus number is dynamically assigned */
1079 of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay);
1080 of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr);
1081 of_property_read_u32(np, "samsung,i2c-max-bus-freq",
1082 (u32 *)&pdata->frequency);
1086 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
1092 /* s3c24xx_i2c_probe
1094 * called by the bus driver when a suitable device is found
1097 static int s3c24xx_i2c_probe(struct platform_device *pdev)
1099 struct s3c24xx_i2c *i2c;
1100 struct s3c2410_platform_i2c *pdata = NULL;
1101 struct resource *res;
1104 if (!pdev->dev.of_node) {
1105 pdata = dev_get_platdata(&pdev->dev);
1107 dev_err(&pdev->dev, "no platform data\n");
1112 i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL);
1116 i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1120 i2c->quirks = s3c24xx_get_device_quirks(pdev);
1122 memcpy(i2c->pdata, pdata, sizeof(*pdata));
1124 s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c);
1126 strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
1127 i2c->adap.owner = THIS_MODULE;
1128 i2c->adap.algo = &s3c24xx_i2c_algorithm;
1129 i2c->adap.retries = 2;
1130 i2c->adap.class = I2C_CLASS_DEPRECATED;
1133 init_waitqueue_head(&i2c->wait);
1135 /* find the clock and enable it */
1137 i2c->dev = &pdev->dev;
1138 i2c->clk = devm_clk_get(&pdev->dev, "i2c");
1139 if (IS_ERR(i2c->clk)) {
1140 dev_err(&pdev->dev, "cannot get clock\n");
1144 dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
1147 /* map the registers */
1149 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1150 i2c->regs = devm_ioremap_resource(&pdev->dev, res);
1152 if (IS_ERR(i2c->regs))
1153 return PTR_ERR(i2c->regs);
1155 dev_dbg(&pdev->dev, "registers %p (%p)\n",
1158 /* setup info block for the i2c core */
1160 i2c->adap.algo_data = i2c;
1161 i2c->adap.dev.parent = &pdev->dev;
1163 i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev);
1165 /* inititalise the i2c gpio lines */
1167 if (i2c->pdata->cfg_gpio) {
1168 i2c->pdata->cfg_gpio(to_platform_device(i2c->dev));
1169 } else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c)) {
1173 /* initialise the i2c controller */
1175 clk_prepare_enable(i2c->clk);
1176 ret = s3c24xx_i2c_init(i2c);
1177 clk_disable_unprepare(i2c->clk);
1179 dev_err(&pdev->dev, "I2C controller init failed\n");
1182 /* find the IRQ for this unit (note, this relies on the init call to
1183 * ensure no current IRQs pending
1186 if (!(i2c->quirks & QUIRK_POLL)) {
1187 i2c->irq = ret = platform_get_irq(pdev, 0);
1189 dev_err(&pdev->dev, "cannot find IRQ\n");
1193 ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq, 0,
1194 dev_name(&pdev->dev), i2c);
1197 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
1202 ret = s3c24xx_i2c_register_cpufreq(i2c);
1204 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
1208 /* Note, previous versions of the driver used i2c_add_adapter()
1209 * to add the bus at any number. We now pass the bus number via
1210 * the platform data, so if unset it will now default to always
1214 i2c->adap.nr = i2c->pdata->bus_num;
1215 i2c->adap.dev.of_node = pdev->dev.of_node;
1217 ret = i2c_add_numbered_adapter(&i2c->adap);
1219 dev_err(&pdev->dev, "failed to add bus to i2c core\n");
1220 s3c24xx_i2c_deregister_cpufreq(i2c);
1224 platform_set_drvdata(pdev, i2c);
1226 pm_runtime_enable(&pdev->dev);
1227 pm_runtime_enable(&i2c->adap.dev);
1229 dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
1233 /* s3c24xx_i2c_remove
1235 * called when device is removed from the bus
1238 static int s3c24xx_i2c_remove(struct platform_device *pdev)
1240 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1242 pm_runtime_disable(&i2c->adap.dev);
1243 pm_runtime_disable(&pdev->dev);
1245 s3c24xx_i2c_deregister_cpufreq(i2c);
1247 i2c_del_adapter(&i2c->adap);
1249 if (pdev->dev.of_node && IS_ERR(i2c->pctrl))
1250 s3c24xx_i2c_dt_gpio_free(i2c);
1255 #ifdef CONFIG_PM_SLEEP
1256 static int s3c24xx_i2c_suspend_noirq(struct device *dev)
1258 struct platform_device *pdev = to_platform_device(dev);
1259 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1266 static int s3c24xx_i2c_resume_noirq(struct device *dev)
1268 struct platform_device *pdev = to_platform_device(dev);
1269 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1271 clk_prepare_enable(i2c->clk);
1272 s3c24xx_i2c_init(i2c);
1273 clk_disable_unprepare(i2c->clk);
1281 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {
1282 #ifdef CONFIG_PM_SLEEP
1283 .suspend_noirq = s3c24xx_i2c_suspend_noirq,
1284 .resume_noirq = s3c24xx_i2c_resume_noirq,
1285 .freeze_noirq = s3c24xx_i2c_suspend_noirq,
1286 .thaw_noirq = s3c24xx_i2c_resume_noirq,
1287 .poweroff_noirq = s3c24xx_i2c_suspend_noirq,
1288 .restore_noirq = s3c24xx_i2c_resume_noirq,
1292 #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops)
1294 #define S3C24XX_DEV_PM_OPS NULL
1297 /* device driver for platform bus bits */
1299 static struct platform_driver s3c24xx_i2c_driver = {
1300 .probe = s3c24xx_i2c_probe,
1301 .remove = s3c24xx_i2c_remove,
1302 .id_table = s3c24xx_driver_ids,
1304 .owner = THIS_MODULE,
1306 .pm = S3C24XX_DEV_PM_OPS,
1307 .of_match_table = of_match_ptr(s3c24xx_i2c_match),
1311 static int __init i2c_adap_s3c_init(void)
1313 return platform_driver_register(&s3c24xx_i2c_driver);
1315 subsys_initcall(i2c_adap_s3c_init);
1317 static void __exit i2c_adap_s3c_exit(void)
1319 platform_driver_unregister(&s3c24xx_i2c_driver);
1321 module_exit(i2c_adap_s3c_exit);
1323 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1324 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
1325 MODULE_LICENSE("GPL");