2 * Copyright (C) 2012-2014 ROCKCHIP, Inc.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
15 #include <linux/uaccess.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/wakelock.h>
20 #include <linux/i2c.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_i2c.h>
23 #include <linux/init.h>
24 #include <linux/time.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/errno.h>
28 #include <linux/err.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/slab.h>
33 #include <linux/mutex.h>
34 #include <linux/miscdevice.h>
35 #include <linux/gpio.h>
39 #define i2c_dbg(dev, format, arg...) \
40 dev_printk(KERN_INFO , dev , format , ## arg)
42 #define i2c_dbg(dev, format, arg...)
52 #define i2c_writel writel_relaxed
53 #define i2c_readl readl_relaxed
55 #define I2C_WAIT_TIMEOUT 200 //200ms
57 #define rockchip_set_bit(p, v, b) (((p) & ~(1 << (b))) | ((v) << (b)))
58 #define rockchip_get_bit(p, b) (((p) & (1 << (b))) >> (b))
60 #define rockchip_set_bits(p, v, b, m) (((p) & ~(m)) | ((v) << (b)))
61 #define rockchip_get_bits(p, b, m) (((p) & (m)) >> (b))
63 #define rockchip_ceil(x, y) \
64 ({ unsigned long __x = (x), __y = (y); (__x + __y - 1) / __y; })
66 enum rockchip_i2c_state {
76 wait_queue_head_t wait;
77 unsigned int suspended:1;
86 enum rockchip_i2c_state state;
87 unsigned int complete_what;
88 unsigned long clkrate;
93 struct resource *ioarea;
94 struct i2c_adapter adap;
95 struct mutex suspend_lock;
97 unsigned long scl_rate;
98 unsigned long i2c_rate;
100 unsigned char addr_1st, addr_2nd;
104 unsigned int check_idle;
105 int sda_gpio, scl_gpio;
106 struct pinctrl_state *gpio_state;
109 #define COMPLETE_READ (1<<STATE_START | 1<<STATE_READ | 1<<STATE_STOP)
110 #define COMPLETE_WRITE (1<<STATE_START | 1<<STATE_WRITE | 1<<STATE_STOP)
112 /* Control register */
113 #define I2C_CON 0x000
114 #define I2C_CON_EN (1 << 0)
115 #define I2C_CON_MOD(mod) ((mod) << 1)
116 #define I2C_CON_MASK (3 << 1)
125 #define I2C_CON_START (1 << 3)
126 #define I2C_CON_STOP (1 << 4)
127 #define I2C_CON_LASTACK (1 << 5)
128 #define I2C_CON_ACTACK (1 << 6)
130 /* Clock dividor register */
131 #define I2C_CLKDIV 0x004
132 #define I2C_CLKDIV_VAL(divl, divh) (((divl) & 0xffff) | (((divh) << 16) & 0xffff0000))
134 /* the slave address accessed for master rx mode */
135 #define I2C_MRXADDR 0x008
136 #define I2C_MRXADDR_LOW (1 << 24)
137 #define I2C_MRXADDR_MID (1 << 25)
138 #define I2C_MRXADDR_HIGH (1 << 26)
140 /* the slave register address accessed for master rx mode */
141 #define I2C_MRXRADDR 0x00c
142 #define I2C_MRXRADDR_LOW (1 << 24)
143 #define I2C_MRXRADDR_MID (1 << 25)
144 #define I2C_MRXRADDR_HIGH (1 << 26)
146 /* master tx count */
147 #define I2C_MTXCNT 0x010
149 /* master rx count */
150 #define I2C_MRXCNT 0x014
152 /* interrupt enable register */
153 #define I2C_IEN 0x018
154 #define I2C_BTFIEN (1 << 0)
155 #define I2C_BRFIEN (1 << 1)
156 #define I2C_MBTFIEN (1 << 2)
157 #define I2C_MBRFIEN (1 << 3)
158 #define I2C_STARTIEN (1 << 4)
159 #define I2C_STOPIEN (1 << 5)
160 #define I2C_NAKRCVIEN (1 << 6)
161 #define IRQ_MST_ENABLE (I2C_MBTFIEN | I2C_MBRFIEN | I2C_NAKRCVIEN | I2C_STARTIEN | I2C_STOPIEN)
162 #define IRQ_ALL_DISABLE 0
164 /* interrupt pending register */
165 #define I2C_IPD 0x01c
166 #define I2C_BTFIPD (1 << 0)
167 #define I2C_BRFIPD (1 << 1)
168 #define I2C_MBTFIPD (1 << 2)
169 #define I2C_MBRFIPD (1 << 3)
170 #define I2C_STARTIPD (1 << 4)
171 #define I2C_STOPIPD (1 << 5)
172 #define I2C_NAKRCVIPD (1 << 6)
174 #define I2C_HOLD_SCL (1 << 7)
175 #define I2C_IPD_ALL_CLEAN 0x7f
178 #define I2C_FCNT 0x020
180 /* I2C tx data register */
181 #define I2C_TXDATA_BASE 0X100
183 /* I2C rx data register */
184 #define I2C_RXDATA_BASE 0x200
186 static void rockchip_show_regs(struct rockchip_i2c *i2c)
190 dev_info(i2c->dev, "i2c->clk = %lu\n", clk_get_rate(i2c->clk));
191 dev_info(i2c->dev, "i2c->state = %d\n", i2c->state);
192 dev_info(i2c->dev, "I2C_CON: 0x%08x\n", i2c_readl(i2c->regs + I2C_CON));
193 dev_info(i2c->dev, "I2C_CLKDIV: 0x%08x\n", i2c_readl(i2c->regs + I2C_CLKDIV));
194 dev_info(i2c->dev, "I2C_MRXADDR: 0x%08x\n", i2c_readl(i2c->regs + I2C_MRXADDR));
195 dev_info(i2c->dev, "I2C_MRXRADDR: 0x%08x\n", i2c_readl(i2c->regs + I2C_MRXRADDR));
196 dev_info(i2c->dev, "I2C_MTXCNT: 0x%08x\n", i2c_readl(i2c->regs + I2C_MTXCNT));
197 dev_info(i2c->dev, "I2C_MRXCNT: 0x%08x\n", i2c_readl(i2c->regs + I2C_MRXCNT));
198 dev_info(i2c->dev, "I2C_IEN: 0x%08x\n", i2c_readl(i2c->regs + I2C_IEN));
199 dev_info(i2c->dev, "I2C_IPD: 0x%08x\n", i2c_readl(i2c->regs + I2C_IPD));
200 dev_info(i2c->dev, "I2C_FCNT: 0x%08x\n", i2c_readl(i2c->regs + I2C_FCNT));
201 for (i = 0; i < 8; i++)
202 dev_info(i2c->dev, "I2C_TXDATA%d: 0x%08x\n", i, i2c_readl(i2c->regs + I2C_TXDATA_BASE + i * 4));
203 for (i = 0; i < 8; i++)
204 dev_info(i2c->dev, "I2C_RXDATA%d: 0x%08x\n", i, i2c_readl(i2c->regs + I2C_RXDATA_BASE + i * 4));
207 static int rockchip_i2c_check_idle(struct rockchip_i2c *i2c)
210 int sda_lev, scl_lev;
212 if (!gpio_is_valid(i2c->sda_gpio))
215 if (pinctrl_select_state(i2c->dev->pins->p, i2c->gpio_state))
218 sda_lev = gpio_get_value(i2c->sda_gpio);
219 scl_lev = gpio_get_value(i2c->scl_gpio);
221 pinctrl_select_state(i2c->dev->pins->p, i2c->dev->pins->default_state);
223 if (sda_lev == 1 && scl_lev == 1)
225 else if (sda_lev == 0 && scl_lev == 1)
227 else if (sda_lev == 1 && scl_lev == 0)
233 static inline void rockchip_i2c_enable(struct rockchip_i2c *i2c, unsigned int lastnak)
235 unsigned int con = 0;
238 con |= I2C_CON_MOD(i2c->mode);
240 con |= I2C_CON_LASTACK;
241 con |= I2C_CON_START;
242 i2c_writel(con, i2c->regs + I2C_CON);
245 static inline void rockchip_i2c_disable(struct rockchip_i2c *i2c)
247 i2c_writel(0, i2c->regs + I2C_CON);
250 static inline void rockchip_i2c_clean_start(struct rockchip_i2c *i2c)
252 unsigned int con = i2c_readl(i2c->regs + I2C_CON);
254 con &= ~I2C_CON_START;
255 i2c_writel(con, i2c->regs + I2C_CON);
258 static inline void rockchip_i2c_send_start(struct rockchip_i2c *i2c)
260 unsigned int con = i2c_readl(i2c->regs + I2C_CON);
262 con |= I2C_CON_START;
263 if (con & I2C_CON_STOP)
264 dev_warn(i2c->dev, "I2C_CON: stop bit is set\n");
266 i2c_writel(con, i2c->regs + I2C_CON);
269 static inline void rockchip_i2c_send_stop(struct rockchip_i2c *i2c)
271 unsigned int con = i2c_readl(i2c->regs + I2C_CON);
274 if (con & I2C_CON_START)
275 dev_warn(i2c->dev, "I2C_CON: start bit is set\n");
277 i2c_writel(con, i2c->regs + I2C_CON);
280 static inline void rockchip_i2c_clean_stop(struct rockchip_i2c *i2c)
282 unsigned int con = i2c_readl(i2c->regs + I2C_CON);
284 con &= ~I2C_CON_STOP;
285 i2c_writel(con, i2c->regs + I2C_CON);
288 static inline void rockchip_i2c_disable_irq(struct rockchip_i2c *i2c)
290 i2c_writel(IRQ_ALL_DISABLE, i2c->regs + I2C_IEN);
293 static inline void rockchip_i2c_enable_irq(struct rockchip_i2c *i2c)
295 i2c_writel(IRQ_MST_ENABLE, i2c->regs + I2C_IEN);
298 static void rockchip_get_div(int div, int *divh, int *divl)
304 *divh = rockchip_ceil(div, 2);
309 /* SCL Divisor = 8 * (CLKDIVL+1 + CLKDIVH+1)
310 * SCL = i2c_rate/ SCLK Divisor
312 static void rockchip_i2c_set_clk(struct rockchip_i2c *i2c, unsigned long scl_rate)
314 unsigned long i2c_rate = i2c->i2c_rate;
317 if (scl_rate == i2c->scl_rate)
319 i2c->scl_rate = scl_rate;
320 div = rockchip_ceil(i2c_rate, (scl_rate * 8)) - 2;
321 if (unlikely(div < 0)) {
322 dev_warn(i2c->dev, "Divisor(%d) is negative, set divl = divh = 0\n", div);
325 rockchip_get_div(div, &divh, &divl);
327 i2c_writel(I2C_CLKDIV_VAL(divl, divh), i2c->regs + I2C_CLKDIV);
328 i2c_dbg(i2c->dev, "set clk(I2C_CLKDIV: 0x%08x)\n", i2c_readl(i2c->regs + I2C_CLKDIV));
331 static void rockchip_i2c_init_hw(struct rockchip_i2c *i2c, unsigned long scl_rate)
334 clk_enable(i2c->clk);
335 rockchip_i2c_set_clk(i2c, scl_rate);
336 clk_disable(i2c->clk);
339 /* returns TRUE if we this is the last byte in the current message */
340 static inline int is_msglast(struct rockchip_i2c *i2c)
342 return i2c->msg_ptr == i2c->msg->len - 1;
345 /* returns TRUE if we reached the end of the current message */
346 static inline int is_msgend(struct rockchip_i2c *i2c)
348 return i2c->msg_ptr >= i2c->msg->len;
351 static void rockchip_i2c_stop(struct rockchip_i2c *i2c, int ret)
356 if (ret == -EAGAIN) {
357 i2c->state = STATE_IDLE;
363 i2c_writel(I2C_STOPIEN, i2c->regs + I2C_IEN);
364 i2c->state = STATE_STOP;
365 rockchip_i2c_send_stop(i2c);
368 static inline void rockchip_set_rx_mode(struct rockchip_i2c *i2c, unsigned int lastnak)
370 unsigned long con = i2c_readl(i2c->regs + I2C_CON);
372 con &= (~I2C_CON_MASK);
373 con |= (I2C_CON_MOD_RX << 1);
375 con |= I2C_CON_LASTACK;
376 i2c_writel(con, i2c->regs + I2C_CON);
379 static void rockchip_irq_read_prepare(struct rockchip_i2c *i2c)
381 unsigned int cnt, len = i2c->msg->len - i2c->msg_ptr;
383 if (len <= 32 && i2c->msg_ptr != 0)
384 rockchip_set_rx_mode(i2c, 1);
385 else if (i2c->msg_ptr != 0)
386 rockchip_set_rx_mode(i2c, 0);
388 if (is_msgend(i2c)) {
389 rockchip_i2c_stop(i2c, i2c->error);
396 i2c_writel(cnt, i2c->regs + I2C_MRXCNT);
399 static void rockchip_irq_read_get_data(struct rockchip_i2c *i2c)
401 unsigned int i, len = i2c->msg->len - i2c->msg_ptr;
404 len = (len >= 32) ? 32 : len;
406 for (i = 0; i < len; i++) {
408 p = i2c_readl(i2c->regs + I2C_RXDATA_BASE + (i / 4) * 4);
409 i2c->msg->buf[i2c->msg_ptr++] = (p >> ((i % 4) * 8)) & 0xff;
413 static void rockchip_irq_write_prepare(struct rockchip_i2c *i2c)
415 unsigned int data = 0, cnt = 0, i, j;
418 if (is_msgend(i2c)) {
419 rockchip_i2c_stop(i2c, i2c->error);
422 for (i = 0; i < 8; i++) {
424 for (j = 0; j < 4; j++) {
427 if ((i2c->msg_ptr == 0) && (cnt == 0))
428 byte = (i2c->addr_1st & 0x7f) << 1;
429 else if ((i2c->msg_ptr == 0) && (cnt == 1) && (i2c->msg->flags & I2C_M_TEN))
430 byte = i2c->addr_2nd;
432 byte = i2c->msg->buf[i2c->msg_ptr++];
434 data |= (byte << (j * 8));
436 i2c_writel(data, i2c->regs + I2C_TXDATA_BASE + 4 * i);
440 i2c_writel(cnt, i2c->regs + I2C_MTXCNT);
443 static void rockchip_i2c_irq_nextblock(struct rockchip_i2c *i2c, unsigned int ipd)
445 switch (i2c->state) {
447 if (!(ipd & I2C_STARTIPD)) {
448 rockchip_i2c_stop(i2c, -ENXIO);
449 dev_err(i2c->dev, "Addr[0x%04x] no start irq in STATE_START\n", i2c->addr);
450 rockchip_show_regs(i2c);
451 i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
454 i2c->complete_what |= 1 << i2c->state;
455 i2c_writel(I2C_STARTIPD, i2c->regs + I2C_IPD);
456 rockchip_i2c_clean_start(i2c);
457 if (i2c->mode == I2C_CON_MOD_TX) {
458 i2c_writel(I2C_MBTFIEN | I2C_NAKRCVIEN, i2c->regs + I2C_IEN);
459 i2c->state = STATE_WRITE;
462 i2c_writel(I2C_MBRFIEN | I2C_NAKRCVIEN, i2c->regs + I2C_IEN);
463 i2c->state = STATE_READ;
467 if (!(ipd & I2C_MBTFIPD)) {
468 rockchip_i2c_stop(i2c, -ENXIO);
469 dev_err(i2c->dev, "Addr[0x%04x] no mbtf irq in STATE_WRITE\n", i2c->addr);
470 rockchip_show_regs(i2c);
471 i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
474 i2c->complete_what |= 1 << i2c->state;
475 i2c_writel(I2C_MBTFIPD, i2c->regs + I2C_IPD);
477 rockchip_irq_write_prepare(i2c);
480 if (!(ipd & I2C_MBRFIPD)) {
481 rockchip_i2c_stop(i2c, -ENXIO);
482 dev_err(i2c->dev, "Addr[0x%04x] no mbrf irq in STATE_READ, ipd = 0x%x\n", i2c->addr, ipd);
483 rockchip_show_regs(i2c);
484 i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
487 i2c->complete_what |= 1 << i2c->state;
488 i2c_writel(I2C_MBRFIPD, i2c->regs + I2C_IPD);
489 rockchip_irq_read_get_data(i2c);
491 rockchip_irq_read_prepare(i2c);
494 if (!(ipd & I2C_STOPIPD)) {
495 rockchip_i2c_stop(i2c, -ENXIO);
496 dev_err(i2c->dev, "Addr[0x%04x] no stop irq in STATE_STOP\n", i2c->addr);
497 rockchip_show_regs(i2c);
498 i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
501 rockchip_i2c_clean_stop(i2c);
502 i2c_writel(I2C_STOPIPD, i2c->regs + I2C_IPD);
504 i2c->complete_what |= 1 << i2c->state;
505 i2c->state = STATE_IDLE;
515 static irqreturn_t rockchip_i2c_irq(int irq, void *dev_id)
517 struct rockchip_i2c *i2c = dev_id;
520 spin_lock(&i2c->lock);
521 ipd = i2c_readl(i2c->regs + I2C_IPD);
522 if (i2c->state == STATE_IDLE) {
523 dev_info(i2c->dev, "Addr[0x%04x] irq in STATE_IDLE, ipd = 0x%x\n", i2c->addr, ipd);
524 i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
528 if (ipd & I2C_NAKRCVIPD) {
529 i2c_writel(I2C_NAKRCVIPD, i2c->regs + I2C_IPD);
530 i2c->error = -EAGAIN;
533 rockchip_i2c_irq_nextblock(i2c, ipd);
535 spin_unlock(&i2c->lock);
539 static int rockchip_i2c_set_master(struct rockchip_i2c *i2c, struct i2c_msg *msgs, int num)
541 unsigned int reg_valid_bits = 0;
542 unsigned int reg_addr = 0;
543 unsigned int addr = (i2c->addr_1st << 1) | 1;
546 i2c->count = msgs[0].len;
547 if (!(msgs[0].flags & I2C_M_RD)) {
549 i2c->mode = I2C_CON_MOD_TX;
552 i2c_writel(addr | I2C_MRXADDR_LOW,
553 i2c->regs + I2C_MRXADDR);
554 i2c_writel(0, i2c->regs + I2C_MRXRADDR);
555 i2c->mode = I2C_CON_MOD_TRX;
556 //i2c->mode = I2C_CON_MOD_RX;
558 } else if (num == 2) {
559 i2c->count = msgs[1].len;
561 if (msgs[0].flags & I2C_M_TEN) {
562 switch (msgs[0].len) {
564 reg_addr = i2c->addr_2nd | (msgs[0].buf[0] << 8);
565 reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID;
568 reg_addr = i2c->addr_2nd | (msgs[0].buf[0] << 8) | (msgs[0].buf[1] << 16);
569 reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID | I2C_MRXADDR_HIGH;
575 switch (msgs[0].len) {
577 reg_addr = msgs[0].buf[0];
578 reg_valid_bits |= I2C_MRXADDR_LOW;
581 reg_addr = msgs[0].buf[0] | (msgs[0].buf[1] << 8);
582 reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID;
585 reg_addr = msgs[0].buf[0] | (msgs[0].buf[1] << 8) | (msgs[0].buf[2] << 16);
586 reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID | I2C_MRXADDR_HIGH;
592 if ((msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
594 i2c_writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
595 i2c_writel(reg_addr | reg_valid_bits, i2c->regs + I2C_MRXRADDR);
596 i2c->mode = I2C_CON_MOD_RRX;
597 } else if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
599 i2c_writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
600 i2c_writel(reg_addr | reg_valid_bits, i2c->regs + I2C_MRXRADDR);
601 i2c->mode = I2C_CON_MOD_TRX;
605 dev_err(i2c->dev, "This case(num > 2) has not been support now\n");
612 /* rockchip_i2c_doxfer
614 * this starts an i2c transfer
616 static int rockchip_i2c_doxfer(struct rockchip_i2c *i2c,
617 struct i2c_msg *msgs, int num)
619 unsigned long timeout, flags;
621 /* 32 -- max transfer bytes
622 * 2 -- addr bytes * 2
623 * 3 -- max reg addr bytes
624 * 9 -- cycles per bytes
625 * max cycles: (32 + 2 + 3) * 9 --> 400 cycles
627 int msleep_time = 400 * 1000 / i2c->scl_rate; // ms
628 int can_sleep = !(in_atomic() || irqs_disabled());
630 spin_lock_irqsave(&i2c->lock, flags);
631 i2c->addr = msgs[0].addr;
632 if (msgs[0].flags & I2C_M_TEN) {
633 i2c->addr_1st = ((i2c->addr & 0x0300) >> 8) | 0x78;
634 i2c->addr_2nd = i2c->addr & 0x00ff;
636 i2c->addr_1st = i2c->addr & 0x007f;
639 i2c_dbg(i2c->dev, "addr: 0x%04x, addr_1st: 0x%02x, addr_2nd: 0x%02x\n",
640 i2c->addr, i2c->addr_1st, i2c->addr_2nd);
642 if (rockchip_i2c_set_master(i2c, msgs, num) < 0) {
643 spin_unlock_irqrestore(&i2c->lock, flags);
644 dev_err(i2c->dev, "addr[0x%04x] set master error\n", msgs[0].addr);
650 i2c->state = STATE_START;
651 i2c->complete_what = 0;
652 i2c_writel(I2C_STARTIEN, i2c->regs + I2C_IEN);
654 rockchip_i2c_enable(i2c, (i2c->count > 32) ? 0 : 1); //if count > 32, byte(32) send ack
657 long ret = msecs_to_jiffies(I2C_WAIT_TIMEOUT);
661 prepare_to_wait(&i2c->wait, &wait, TASK_UNINTERRUPTIBLE);
662 if (i2c->is_busy == 0)
664 spin_unlock_irqrestore(&i2c->lock, flags);
665 ret = schedule_timeout(ret);
666 spin_lock_irqsave(&i2c->lock, flags);
670 if (!ret && (i2c->is_busy == 0))
672 finish_wait(&i2c->wait, &wait);
676 int cpu = raw_smp_processor_id();
677 int tmo = I2C_WAIT_TIMEOUT * USEC_PER_MSEC;
678 while (tmo-- && i2c->is_busy != 0) {
679 spin_unlock_irqrestore(&i2c->lock, flags);
681 if (cpu == 0 && irqs_disabled()
682 && (i2c_readl(i2c->regs + I2C_IPD)
683 & i2c_readl(i2c->regs + I2C_IEN))) {
684 rockchip_i2c_irq(i2c->irq, i2c);
686 spin_lock_irqsave(&i2c->lock, flags);
688 timeout = (tmo <= 0) ? 0 : 1;
694 unsigned int ipd = i2c_readl(i2c->regs + I2C_IPD);
696 i2c_dbg(i2c->dev, "error = %d\n", error);
697 else if (i2c->complete_what != COMPLETE_READ && i2c->complete_what != COMPLETE_WRITE) {
698 if (ipd & I2C_HOLD_SCL)
699 dev_err(i2c->dev, "SCL was hold by slave\n");
700 dev_err(i2c->dev, "Addr[0x%04x] wait event timeout, state: %d, is_busy: %d, error: %d, complete_what: 0x%x, ipd: 0x%x\n",
701 msgs[0].addr, i2c->state, i2c->is_busy, error, i2c->complete_what, ipd);
702 //rockchip_show_regs(i2c);
705 rockchip_i2c_send_stop(i2c);
708 i2c_dbg(i2c->dev, "Addr[0x%02x] wait event timeout, but transfer complete\n", i2c->addr);
711 i2c->state = STATE_IDLE;
713 i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
714 rockchip_i2c_disable_irq(i2c);
715 rockchip_i2c_disable(i2c);
716 spin_unlock_irqrestore(&i2c->lock, flags);
718 if (error == -EAGAIN)
719 i2c_dbg(i2c->dev, "No ack(complete_what: 0x%x), Maybe slave(addr: 0x%04x) not exist or abnormal power-on\n",
720 i2c->complete_what, i2c->addr);
727 * first port of call from the i2c bus code when an message needs
728 * transferring across the i2c bus.
731 static int rockchip_i2c_xfer(struct i2c_adapter *adap,
732 struct i2c_msg *msgs, int num)
735 struct rockchip_i2c *i2c = i2c_get_adapdata(adap);
736 unsigned long scl_rate = i2c->scl_rate;
737 int can_sleep = !(in_atomic() || irqs_disabled());
740 mutex_lock(&i2c->suspend_lock);
741 if (i2c->suspended) {
742 dev_err(i2c->dev, "i2c is suspended\n");
743 mutex_unlock(&i2c->suspend_lock);
748 clk_enable(i2c->clk);
749 if (i2c->check_idle) {
750 int state, retry = 10;
752 state = rockchip_i2c_check_idle(i2c);
753 if (state == I2C_IDLE)
762 dev_err(i2c->dev, "i2c is not in idle(state = %d)\n", state);
768 #ifdef CONFIG_I2C_ROCKCHIP_COMPAT
769 if (msgs[0].scl_rate <= 400000 && msgs[0].scl_rate >= 10000)
770 scl_rate = msgs[0].scl_rate;
771 else if (msgs[0].scl_rate > 400000) {
772 dev_warn_ratelimited(i2c->dev, "Warning: addr[0x%04x] msg[0].scl_rate( = %dKhz) is too high!",
773 msgs[0].addr, msgs[0].scl_rate/1000);
776 dev_warn_ratelimited(i2c->dev, "Warning: addr[0x%04x] msg[0].scl_rate( = %dKhz) is too low!",
777 msgs[0].addr, msgs[0].scl_rate/1000);
781 rockchip_i2c_set_clk(i2c, scl_rate);
784 i2c_dbg(i2c->dev, "i2c transfer start: addr: 0x%04x, scl_reate: %ldKhz, len: %d\n", msgs[0].addr, scl_rate/1000, num);
785 ret = rockchip_i2c_doxfer(i2c, msgs, num);
786 i2c_dbg(i2c->dev, "i2c transfer stop: addr: 0x%04x, state: %d, ret: %d\n", msgs[0].addr, ret, i2c->state);
789 clk_disable(i2c->clk);
791 mutex_unlock(&i2c->suspend_lock);
793 return (ret < 0) ? ret : num;
796 /* declare our i2c functionality */
797 static u32 rockchip_i2c_func(struct i2c_adapter *adap)
799 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
802 /* i2c bus registration info */
804 static const struct i2c_algorithm rockchip_i2c_algorithm = {
805 .master_xfer = rockchip_i2c_xfer,
806 .functionality = rockchip_i2c_func,
809 /* rockchip_i2c_probe
811 * called by the bus driver when a suitable device is found
814 static int rockchip_i2c_probe(struct platform_device *pdev)
816 struct rockchip_i2c *i2c = NULL;
817 struct resource *res;
818 struct device_node *np = pdev->dev.of_node;
822 dev_err(&pdev->dev, "Missing device tree node.\n");
826 i2c = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_i2c), GFP_KERNEL);
828 dev_err(&pdev->dev, "no memory for state\n");
832 strlcpy(i2c->adap.name, "rockchip_i2c", sizeof(i2c->adap.name));
833 i2c->dev = &pdev->dev;
834 i2c->adap.owner = THIS_MODULE;
835 i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
836 i2c->adap.retries = 2;
837 i2c->adap.timeout = msecs_to_jiffies(100);
838 i2c->adap.algo = &rockchip_i2c_algorithm;
839 i2c_set_adapdata(&i2c->adap, i2c);
840 i2c->adap.dev.parent = &pdev->dev;
841 i2c->adap.dev.of_node = np;
843 spin_lock_init(&i2c->lock);
844 init_waitqueue_head(&i2c->wait);
846 /* map the registers */
847 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
848 i2c->regs = devm_ioremap_resource(&pdev->dev, res);
849 if (IS_ERR(i2c->regs))
850 return PTR_ERR(i2c->regs);
852 i2c_dbg(&pdev->dev, "registers %p (%p, %p)\n",
853 i2c->regs, i2c->ioarea, res);
855 i2c->check_idle = true;
856 of_property_read_u32(np, "rockchip,check-idle", &i2c->check_idle);
857 if (i2c->check_idle) {
858 i2c->sda_gpio = of_get_gpio(np, 0);
859 if (!gpio_is_valid(i2c->sda_gpio)) {
860 dev_err(&pdev->dev, "sda gpio is invalid\n");
863 ret = devm_gpio_request(&pdev->dev, i2c->sda_gpio, dev_name(&i2c->adap.dev));
865 dev_err(&pdev->dev, "failed to request sda gpio\n");
868 i2c->scl_gpio = of_get_gpio(np, 1);
869 if (!gpio_is_valid(i2c->scl_gpio)) {
870 dev_err(&pdev->dev, "scl gpio is invalid\n");
873 ret = devm_gpio_request(&pdev->dev, i2c->scl_gpio, dev_name(&i2c->adap.dev));
875 dev_err(&pdev->dev, "failed to request scl gpio\n");
878 i2c->gpio_state = pinctrl_lookup_state(i2c->dev->pins->p, "gpio");
879 if (IS_ERR(i2c->gpio_state)) {
880 dev_err(&pdev->dev, "no gpio pinctrl state\n");
881 return PTR_ERR(i2c->gpio_state);
883 pinctrl_select_state(i2c->dev->pins->p, i2c->gpio_state);
884 gpio_direction_input(i2c->sda_gpio);
885 gpio_direction_input(i2c->scl_gpio);
886 pinctrl_select_state(i2c->dev->pins->p, i2c->dev->pins->default_state);
889 /* setup info block for the i2c core */
890 ret = i2c_add_adapter(&i2c->adap);
892 dev_err(&pdev->dev, "failed to add adapter\n");
896 platform_set_drvdata(pdev, i2c);
898 /* find the clock and enable it */
899 i2c->clk = devm_clk_get(&pdev->dev, NULL);
900 if (IS_ERR(i2c->clk)) {
901 dev_err(&pdev->dev, "cannot get clock\n");
902 return PTR_ERR(i2c->clk);
905 i2c_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
907 /* find the IRQ for this unit (note, this relies on the init call to
908 * ensure no current IRQs pending
910 i2c->irq = ret = platform_get_irq(pdev, 0);
912 dev_err(&pdev->dev, "cannot find IRQ\n");
916 ret = devm_request_irq(&pdev->dev, i2c->irq, rockchip_i2c_irq, 0,
917 dev_name(&i2c->adap.dev), i2c);
919 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
923 ret = clk_prepare(i2c->clk);
925 dev_err(&pdev->dev, "Could not prepare clock\n");
929 i2c->i2c_rate = clk_get_rate(i2c->clk);
931 rockchip_i2c_init_hw(i2c, 100 * 1000);
932 dev_info(&pdev->dev, "%s: Rockchip I2C adapter\n", dev_name(&i2c->adap.dev));
934 of_i2c_register_devices(&i2c->adap);
935 mutex_init(&i2c->suspend_lock);
940 /* rockchip_i2c_remove
942 * called when device is removed from the bus
945 static int rockchip_i2c_remove(struct platform_device *pdev)
947 struct rockchip_i2c *i2c = platform_get_drvdata(pdev);
949 mutex_lock(&i2c->suspend_lock);
951 i2c_del_adapter(&i2c->adap);
952 clk_unprepare(i2c->clk);
953 mutex_unlock(&i2c->suspend_lock);
958 /* rockchip_i2c_shutdown
960 * called when device is shutdown from the bus
962 static void rockchip_i2c_shutdown(struct platform_device *pdev)
964 struct rockchip_i2c *i2c = platform_get_drvdata(pdev);
966 mutex_lock(&i2c->suspend_lock);
968 mutex_unlock(&i2c->suspend_lock);
972 static int rockchip_i2c_suspend_noirq(struct device *dev)
974 struct platform_device *pdev = to_platform_device(dev);
975 struct rockchip_i2c *i2c = platform_get_drvdata(pdev);
977 mutex_lock(&i2c->suspend_lock);
979 pinctrl_pm_select_sleep_state(dev);
980 mutex_unlock(&i2c->suspend_lock);
985 static int rockchip_i2c_resume_noirq(struct device *dev)
987 struct platform_device *pdev = to_platform_device(dev);
988 struct rockchip_i2c *i2c = platform_get_drvdata(pdev);
990 mutex_lock(&i2c->suspend_lock);
991 pinctrl_pm_select_default_state(dev);
992 rockchip_i2c_init_hw(i2c, i2c->scl_rate);
994 mutex_unlock(&i2c->suspend_lock);
999 static const struct dev_pm_ops rockchip_i2c_dev_pm_ops = {
1000 .suspend_noirq = rockchip_i2c_suspend_noirq,
1001 .resume_noirq = rockchip_i2c_resume_noirq,
1004 #define ROCKCHIP_I2C_PM_OPS (&rockchip_i2c_dev_pm_ops)
1006 #define ROCKCHIP_I2C_PM_OPS NULL
1009 static const struct of_device_id rockchip_i2c_of_match[] = {
1010 { .compatible = "rockchip,rk30-i2c", .data = NULL, },
1013 MODULE_DEVICE_TABLE(of, rockchip_i2c_of_match);
1015 static struct platform_driver rockchip_i2c_driver = {
1016 .probe = rockchip_i2c_probe,
1017 .remove = rockchip_i2c_remove,
1018 .shutdown = rockchip_i2c_shutdown,
1020 .owner = THIS_MODULE,
1021 .name = "rockchip_i2c",
1022 .pm = ROCKCHIP_I2C_PM_OPS,
1023 .of_match_table = of_match_ptr(rockchip_i2c_of_match),
1027 static int __init rockchip_i2c_init_driver(void)
1029 return platform_driver_register(&rockchip_i2c_driver);
1032 subsys_initcall(rockchip_i2c_init_driver);
1034 static void __exit rockchip_i2c_exit_driver(void)
1036 platform_driver_unregister(&rockchip_i2c_driver);
1039 module_exit(rockchip_i2c_exit_driver);
1041 static int detect_read(struct i2c_client *client, char *buf, int len)
1045 msg.addr = client->addr;
1046 msg.flags = client->flags | I2C_M_RD;
1049 #ifdef CONFIG_I2C_ROCKCHIP_COMPAT
1050 msg.scl_rate = 100 * 1000;
1053 return i2c_transfer(client->adapter, &msg, 1);
1056 static void detect_set_client(struct i2c_client *client, __u16 addr, int nr)
1059 client->addr = addr;
1060 client->adapter = i2c_get_adapter(nr);
1063 static void slave_detect(int nr)
1066 unsigned short addr;
1068 char buf[6 * 0x80 + 20];
1069 struct i2c_client client;
1071 memset(buf, 0, 6 * 0x80 + 20);
1073 sprintf(buf, "I2c%d slave list: ", nr);
1075 for (addr = 0x01; addr < 0x80; addr++) {
1076 detect_set_client(&client, addr, nr);
1077 ret = detect_read(&client, val, 1);
1079 sprintf(buf, "%s 0x%02x", buf, addr);
1081 printk("%s\n", buf);
1086 static ssize_t i2c_detect_write(struct file *file,
1087 const char __user *buf, size_t count, loff_t *offset)
1094 ret = copy_from_user(nr_buf, buf, count);
1098 sscanf(nr_buf, "%d", &nr);
1099 if (nr >= 5 || nr < 0)
1107 static const struct file_operations i2c_detect_fops = {
1108 .write = i2c_detect_write,
1111 static struct miscdevice i2c_detect_device = {
1112 .minor = MISC_DYNAMIC_MINOR,
1113 .name = "i2c_detect",
1114 .fops = &i2c_detect_fops,
1117 static int __init i2c_detect_init(void)
1119 return misc_register(&i2c_detect_device);
1122 static void __exit i2c_detect_exit(void)
1124 misc_deregister(&i2c_detect_device);
1127 module_init(i2c_detect_init);
1128 module_exit(i2c_detect_exit);
1130 MODULE_DESCRIPTION("Driver for Rockchip I2C Bus");
1131 MODULE_AUTHOR("kfx, kfx@rock-chips.com");
1132 MODULE_LICENSE("GPL");