drivers/i2c/busses/i2c-rk30-adapter.c

   1 /* drivers/i2c/busses/i2c-rk30-adapter.c
   2  *
   3  * Copyright (C) 2012 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15 #include "i2c-rk30.h"
  16
  17 #define COMPLETE_READ     (1<<STATE_START|1<<STATE_READ|1<<STATE_STOP)
  18 #define COMPLETE_WRITE     (1<<STATE_START|1<<STATE_WRITE|1<<STATE_STOP)
  19
  20 /* Control register */
  21 #define I2C_CON                 0x000
  22 #define I2C_CON_EN              (1 << 0)
  23 #define I2C_CON_MOD(mod)        ((mod) << 1)
  24 #define I2C_CON_MASK            (3 << 1)
  25 enum{
  26         I2C_CON_MOD_TX = 0,
  27         I2C_CON_MOD_TRX,
  28         I2C_CON_MOD_RX,
  29         I2C_CON_MOD_RRX,
  30 };
  31 #define I2C_CON_START           (1 << 3)
  32 #define I2C_CON_STOP            (1 << 4)
  33 #define I2C_CON_LASTACK         (1 << 5)
  34 #define I2C_CON_ACTACK          (1 << 6)
  35
  36 /* Clock dividor register */
  37 #define I2C_CLKDIV              0x004
  38 #define I2C_CLKDIV_VAL(divl, divh) (((divl) & 0xffff) | (((divh) << 16) & 0xffff0000))
  39
  40 /* the slave address accessed  for master rx mode */
  41 #define I2C_MRXADDR             0x008
  42 #define I2C_MRXADDR_LOW         (1 << 24)
  43 #define I2C_MRXADDR_MID         (1 << 25)
  44 #define I2C_MRXADDR_HIGH        (1 << 26)
  45
  46 /* the slave register address accessed  for master rx mode */
  47 #define I2C_MRXRADDR            0x00c
  48 #define I2C_MRXRADDR_LOW        (1 << 24)
  49 #define I2C_MRXRADDR_MID        (1 << 25)
  50 #define I2C_MRXRADDR_HIGH       (1 << 26)
  51
  52 /* master tx count */
  53 #define I2C_MTXCNT              0x010
  54
  55 /* master rx count */
  56 #define I2C_MRXCNT              0x014
  57
  58 /* interrupt enable register */
  59 #define I2C_IEN                 0x018
  60 #define I2C_BTFIEN              (1 << 0)
  61 #define I2C_BRFIEN              (1 << 1)
  62 #define I2C_MBTFIEN             (1 << 2)
  63 #define I2C_MBRFIEN             (1 << 3)
  64 #define I2C_STARTIEN            (1 << 4)
  65 #define I2C_STOPIEN             (1 << 5)
  66 #define I2C_NAKRCVIEN           (1 << 6)
  67 #define IRQ_MST_ENABLE          (I2C_MBTFIEN | I2C_MBRFIEN | I2C_NAKRCVIEN | I2C_STARTIEN | I2C_STOPIEN)
  68 #define IRQ_ALL_DISABLE         0
  69
  70 /* interrupt pending register */
  71 #define I2C_IPD                 0x01c
  72 #define I2C_BTFIPD              (1 << 0)
  73 #define I2C_BRFIPD              (1 << 1)
  74 #define I2C_MBTFIPD             (1 << 2)
  75 #define I2C_MBRFIPD             (1 << 3)
  76 #define I2C_STARTIPD            (1 << 4)
  77 #define I2C_STOPIPD             (1 << 5)
  78 #define I2C_NAKRCVIPD           (1 << 6)
  79
  80 #define I2C_HOLD_SCL            (1 << 7)
  81 #define I2C_IPD_ALL_CLEAN       0x7f
  82
  83 /* finished count */
  84 #define I2C_FCNT                0x020
  85
  86 /* I2C tx data register */
  87 #define I2C_TXDATA_BASE         0X100
  88
  89 /* I2C rx data register */
  90 #define I2C_RXDATA_BASE         0x200
  91
  92
  93 static void rk30_show_regs(struct rk30_i2c *i2c)
  94 {
  95         int i;
  96         dev_info(i2c->dev, "i2c->clk = %lu\n", clk_get_rate(i2c->clk));
  97         dev_info(i2c->dev, "i2c->start = %d\n", i2c->state);
  98         dev_info(i2c->dev, "I2C_CON: 0x%08x\n", i2c_readl(i2c->regs + I2C_CON));
  99         dev_info(i2c->dev, "I2C_CLKDIV: 0x%08x\n", i2c_readl(i2c->regs + I2C_CLKDIV));
 100         dev_info(i2c->dev, "I2C_MRXADDR: 0x%08x\n", i2c_readl(i2c->regs + I2C_MRXADDR));
 101         dev_info(i2c->dev, "I2C_MRXRADDR: 0x%08x\n", i2c_readl(i2c->regs + I2C_MRXRADDR));
 102         dev_info(i2c->dev, "I2C_MTXCNT: 0x%08x\n", i2c_readl(i2c->regs + I2C_MTXCNT));
 103         dev_info(i2c->dev, "I2C_MRXCNT: 0x%08x\n", i2c_readl(i2c->regs + I2C_MRXCNT));
 104         dev_info(i2c->dev, "I2C_IEN: 0x%08x\n", i2c_readl(i2c->regs + I2C_IEN));
 105         dev_info(i2c->dev, "I2C_IPD: 0x%08x\n", i2c_readl(i2c->regs + I2C_IPD));
 106         dev_info(i2c->dev, "I2C_FCNT: 0x%08x\n", i2c_readl(i2c->regs + I2C_FCNT));
 107         for( i = 0; i < 8; i ++)
 108                 dev_info(i2c->dev, "I2C_TXDATA%d: 0x%08x\n", i, i2c_readl(i2c->regs + I2C_TXDATA_BASE + i * 4));
 109         for( i = 0; i < 8; i ++)
 110                 dev_info(i2c->dev, "I2C_RXDATA%d: 0x%08x\n", i, i2c_readl(i2c->regs + I2C_RXDATA_BASE + i * 4));
 111 }
 112
 113 static int rk30_i2c_check_idle(struct rk30_i2c *i2c)
 114 {
 115         int ret = 0;
 116         int sda_io, scl_io;
 117         int sda_lev, scl_lev;
 118
 119         sda_io = iomux_mode_to_gpio(i2c->sda_mode);
 120         scl_io = iomux_mode_to_gpio(i2c->scl_mode);
 121
 122         ret = gpio_request(sda_io, NULL);
 123         if(unlikely(ret < 0)){
 124                 dev_err(i2c->dev, "Failed to request gpio: SDA_GPIO\n");
 125                 return ret;
 126         }
 127         ret = gpio_request(scl_io, NULL);
 128         if(unlikely(ret < 0)){
 129                 dev_err(i2c->dev, "Failed to request gpio: SCL_GPIO\n");
 130                 gpio_free(sda_io);
 131                 return ret;
 132         }
 133         gpio_direction_input(sda_io);
 134         gpio_direction_input(scl_io);
 135
 136         sda_lev = gpio_get_value(sda_io);
 137         scl_lev = gpio_get_value(scl_io);
 138
 139         gpio_free(sda_io);
 140         gpio_free(scl_io);
 141
 142         iomux_set(i2c->sda_mode);
 143         iomux_set(i2c->scl_mode);
 144
 145         if(sda_lev == 1 && scl_lev == 1)
 146                 return I2C_IDLE;
 147         else if(sda_lev == 0 && scl_lev == 1)
 148                 return I2C_SDA_LOW;
 149         else if(sda_lev == 1 && scl_lev == 0)
 150                 return I2C_SCL_LOW;
 151         else
 152                 return BOTH_LOW;
 153 }
 154 static inline void rk30_i2c_enable(struct rk30_i2c *i2c, unsigned int lastnak)
 155 {
 156         unsigned int con = 0;
 157
 158         con |= I2C_CON_EN;
 159         con |= I2C_CON_MOD(i2c->mode);
 160         if(lastnak)
 161                 con |= I2C_CON_LASTACK;
 162         con |= I2C_CON_START;
 163         i2c_writel(con, i2c->regs + I2C_CON);
 164 }
 165 static inline void rk30_i2c_disable(struct rk30_i2c *i2c)
 166 {
 167         i2c_writel( 0, i2c->regs + I2C_CON);
 168 }
 169
 170 static inline void rk30_i2c_clean_start(struct rk30_i2c *i2c)
 171 {
 172         unsigned int con = i2c_readl(i2c->regs + I2C_CON);
 173
 174         con &= ~I2C_CON_START;
 175         i2c_writel(con, i2c->regs + I2C_CON);
 176 }
 177 static inline void rk30_i2c_send_start(struct rk30_i2c *i2c)
 178 {
 179         unsigned int con = i2c_readl(i2c->regs + I2C_CON);
 180
 181         con |= I2C_CON_START;
 182         if(con & I2C_CON_STOP)
 183                 dev_warn(i2c->dev, "I2C_CON: stop bit is set\n");
 184
 185         i2c_writel(con, i2c->regs + I2C_CON);
 186 }
 187 static inline void rk30_i2c_send_stop(struct rk30_i2c *i2c)
 188 {
 189         unsigned int con = i2c_readl(i2c->regs + I2C_CON);
 190
 191         con |= I2C_CON_STOP;
 192         if(con & I2C_CON_START)
 193                 dev_warn(i2c->dev, "I2C_CON: start bit is set\n");
 194
 195         i2c_writel(con, i2c->regs + I2C_CON);
 196 }
 197 static inline void rk30_i2c_clean_stop(struct rk30_i2c *i2c)
 198 {
 199         unsigned int con = i2c_readl(i2c->regs + I2C_CON);
 200
 201         con &= ~I2C_CON_STOP;
 202         i2c_writel(con, i2c->regs + I2C_CON);
 203 }
 204
 205 static inline void rk30_i2c_disable_irq(struct rk30_i2c *i2c)
 206 {
 207         i2c_writel(IRQ_ALL_DISABLE, i2c->regs + I2C_IEN);
 208 }
 209
 210 static inline void rk30_i2c_enable_irq(struct rk30_i2c *i2c)
 211 {
 212         i2c_writel(IRQ_MST_ENABLE, i2c->regs + I2C_IEN);
 213 }
 214 static void rk30_get_div(int div, int *divh, int *divl)
 215 {
 216         if(div % 2 == 0){
 217                 *divh = div/2;
 218                 *divl = div/2;
 219         }else{
 220                 *divh = rk30_ceil(div, 2);
 221                 *divl = div/2;
 222         }
 223 }
 224 /* SCL Divisor = 8 * (CLKDIVL+1 + CLKDIVH+1)
 225  * SCL = i2c_rate/ SCLK Divisor
 226 */
 227 static void  rk30_i2c_set_clk(struct rk30_i2c *i2c, unsigned long scl_rate)
 228 {
 229         unsigned long i2c_rate = clk_get_rate(i2c->clk);
 230
 231         int div, divl, divh;
 232
 233         if((scl_rate == i2c->scl_rate) && (i2c_rate == i2c->i2c_rate))
 234                 return;
 235         i2c->i2c_rate = i2c_rate;
 236         i2c->scl_rate = scl_rate;
 237         div = rk30_ceil(i2c_rate, (scl_rate * 8)) - 2;
 238         if(unlikely(div < 0)){
 239                 dev_warn(i2c->dev, "Divisor(%d) is negative, set divl = divh = 0\n", div);
 240                 divh =divl = 0;
 241         }else{
 242                 rk30_get_div(div, &divh, &divl);
 243         }
 244         i2c_writel(I2C_CLKDIV_VAL(divl, divh), i2c->regs + I2C_CLKDIV);
 245         i2c_dbg(i2c->dev, "set clk(I2C_CLKDIV: 0x%08x)\n", i2c_readl(i2c->regs + I2C_CLKDIV));
 246         return;
 247 }
 248 static void rk30_i2c_init_hw(struct rk30_i2c *i2c, unsigned long scl_rate)
 249 {
 250         i2c->scl_rate = 0;
 251         rk30_i2c_set_clk(i2c, scl_rate);
 252         return;
 253 }
 254 /* returns TRUE if we this is the last byte in the current message */
 255 static inline int is_msglast(struct rk30_i2c *i2c)
 256 {
 257         return i2c->msg_ptr == i2c->msg->len-1;
 258 }
 259
 260 /* returns TRUE if we reached the end of the current message */
 261 static inline int is_msgend(struct rk30_i2c *i2c)
 262 {
 263         return i2c->msg_ptr >= i2c->msg->len;
 264 }
 265
 266 static void rk30_i2c_stop(struct rk30_i2c *i2c, int ret)
 267 {
 268
 269         i2c->msg_ptr = 0;
 270         i2c->msg = NULL;
 271         if(ret == -EAGAIN){
 272                 i2c->state = STATE_IDLE;
 273                 i2c->is_busy = 0;
 274                 wake_up(&i2c->wait);
 275                 return;
 276         }
 277         i2c->error = ret;
 278         i2c_writel(I2C_STOPIEN, i2c->regs + I2C_IEN);
 279         i2c->state = STATE_STOP;
 280         rk30_i2c_send_stop(i2c);
 281         return;
 282 }
 283 static inline void rk30_set_rx_mode(struct rk30_i2c *i2c, unsigned int lastnak)
 284 {
 285         unsigned long con = i2c_readl(i2c->regs + I2C_CON);
 286
 287         con &= (~I2C_CON_MASK);
 288         con |= (I2C_CON_MOD_RX << 1);
 289         if(lastnak)
 290                 con |= I2C_CON_LASTACK;
 291         i2c_writel(con, i2c->regs + I2C_CON);
 292 }
 293 static void rk30_irq_read_prepare(struct rk30_i2c *i2c)
 294 {
 295     unsigned int cnt, len = i2c->msg->len - i2c->msg_ptr;
 296
 297     if(len <= 32 && i2c->msg_ptr != 0)
 298             rk30_set_rx_mode(i2c, 1);
 299     else if(i2c->msg_ptr != 0)
 300             rk30_set_rx_mode(i2c, 0);
 301
 302     if(is_msgend(i2c)) {
 303         rk30_i2c_stop(i2c, i2c->error);
 304         return;
 305     }
 306     if(len > 32)
 307         cnt = 32;
 308     else
 309         cnt = len;
 310     i2c_writel(cnt, i2c->regs + I2C_MRXCNT);
 311 }
 312 static void rk30_irq_read_get_data(struct rk30_i2c *i2c)
 313 {
 314      unsigned int i, len = i2c->msg->len - i2c->msg_ptr;
 315      unsigned int p = 0;
 316
 317      len = (len >= 32)?32:len;
 318
 319      for(i = 0; i < len; i++){
 320          if(i%4 == 0)
 321              p = i2c_readl(i2c->regs + I2C_RXDATA_BASE +  (i/4) * 4);
 322          i2c->msg->buf[i2c->msg_ptr++] = (p >>((i%4) * 8)) & 0xff;
 323     }
 324
 325      return;
 326 }
 327 static void rk30_irq_write_prepare(struct rk30_i2c *i2c)
 328 {
 329     unsigned int data = 0, cnt = 0, i, j;
 330     unsigned char byte;
 331
 332     if(is_msgend(i2c)) {
 333         rk30_i2c_stop(i2c, i2c->error);
 334         return;
 335     }
 336     for(i = 0; i < 8; i++){
 337         data = 0;
 338         for(j = 0; j < 4; j++) {
 339             if(is_msgend(i2c))
 340                 break;
 341             if((i2c->msg_ptr == 0) && (cnt == 0))
 342                 byte = (i2c->addr_1st & 0x7f) << 1;
 343             else if((i2c->msg_ptr == 0) && (cnt == 1) && (i2c->msg->flags & I2C_M_TEN))
 344                 byte = i2c->addr_2nd;
 345             else
 346                 byte =  i2c->msg->buf[i2c->msg_ptr++];
 347             cnt++;
 348             data |= (byte << (j * 8));
 349         }
 350         i2c_writel(data, i2c->regs + I2C_TXDATA_BASE + 4 * i);
 351         if(is_msgend(i2c))
 352             break;
 353     }
 354     i2c_writel(cnt, i2c->regs + I2C_MTXCNT);
 355 }
 356 static void rk30_i2c_irq_nextblock(struct rk30_i2c *i2c, unsigned int ipd)
 357 {
 358         switch (i2c->state) {
 359         case STATE_START:
 360                 if(!(ipd & I2C_STARTIPD)){
 361                         rk30_i2c_stop(i2c, -ENXIO);
 362                         dev_err(i2c->dev, "Addr[0x%04x] no start irq in STATE_START\n", i2c->addr);
 363                         rk30_show_regs(i2c);
 364                         i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
 365                         goto out;
 366                 }
 367                 i2c->complete_what |= 1<<i2c->state;
 368                 i2c_writel(I2C_STARTIPD, i2c->regs + I2C_IPD);
 369                 rk30_i2c_clean_start(i2c);
 370                 if(i2c->mode ==  I2C_CON_MOD_TX){
 371                         i2c_writel(I2C_MBTFIEN  | I2C_NAKRCVIEN, i2c->regs + I2C_IEN);
 372                         i2c->state = STATE_WRITE;
 373                         goto prepare_write;
 374                 } else {
 375                         i2c_writel(I2C_MBRFIEN | I2C_NAKRCVIEN, i2c->regs + I2C_IEN);
 376                         i2c->state = STATE_READ;
 377                         goto prepare_read;
 378                 }
 379         case STATE_WRITE:
 380                 if(!(ipd & I2C_MBTFIPD)){
 381                         rk30_i2c_stop(i2c, -ENXIO);
 382                         dev_err(i2c->dev, "Addr[0x%04x] no mbtf irq in STATE_WRITE\n", i2c->addr);
 383                         rk30_show_regs(i2c);
 384                         i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
 385                         goto out;
 386                 }
 387                 i2c->complete_what |= 1<<i2c->state;
 388                 i2c_writel(I2C_MBTFIPD, i2c->regs + I2C_IPD);
 389 prepare_write:
 390                 rk30_irq_write_prepare(i2c);
 391                 break;
 392         case STATE_READ:
 393                 if(!(ipd & I2C_MBRFIPD)){
 394                         rk30_i2c_stop(i2c, -ENXIO);
 395                         dev_err(i2c->dev, "Addr[0x%04x] no mbrf irq in STATE_READ, ipd = 0x%x\n", i2c->addr, ipd);
 396                         rk30_show_regs(i2c);
 397                         i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
 398                         goto out;
 399                 }
 400                 i2c->complete_what |= 1<<i2c->state;
 401                 i2c_writel(I2C_MBRFIPD, i2c->regs + I2C_IPD);
 402                 rk30_irq_read_get_data(i2c);
 403 prepare_read:
 404                 rk30_irq_read_prepare(i2c);
 405                 break;
 406         case STATE_STOP:
 407                 if(!(ipd & I2C_STOPIPD)){
 408                         rk30_i2c_stop(i2c, -ENXIO);
 409                         dev_err(i2c->dev, "Addr[0x%04x] no stop irq in STATE_STOP\n", i2c->addr);
 410                         rk30_show_regs(i2c);
 411                         i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
 412                         goto out;
 413                 }
 414                 rk30_i2c_clean_stop(i2c);
 415                 i2c_writel(I2C_STOPIPD, i2c->regs + I2C_IPD);
 416                 i2c->is_busy = 0;
 417                 i2c->complete_what |= 1<<i2c->state;
 418                 i2c->state = STATE_IDLE;
 419                 wake_up(&i2c->wait);
 420                 break;
 421         default:
 422                 break;
 423         }
 424 out:
 425         return;
 426 }
 427 static irqreturn_t rk30_i2c_irq(int irq, void *dev_id)
 428 {
 429         struct rk30_i2c *i2c = dev_id;
 430         unsigned int ipd;
 431
 432         spin_lock(&i2c->lock);
 433         ipd = i2c_readl(i2c->regs + I2C_IPD);
 434         if(i2c->state == STATE_IDLE){
 435                 dev_info(i2c->dev, "Addr[0x%04x]  irq in STATE_IDLE, ipd = 0x%x\n", i2c->addr, ipd);
 436                 i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
 437                 goto out;
 438         }
 439
 440         if(ipd & I2C_NAKRCVIPD){
 441                 i2c_writel(I2C_NAKRCVIPD, i2c->regs + I2C_IPD);
 442                 i2c->error = -EAGAIN;
 443                 goto out;
 444         }
 445         rk30_i2c_irq_nextblock(i2c, ipd);
 446 out:
 447         spin_unlock(&i2c->lock);
 448         return IRQ_HANDLED;
 449 }
 450
 451
 452 static int rk30_i2c_set_master(struct rk30_i2c *i2c, struct i2c_msg *msgs, int num)
 453 {
 454         unsigned int reg_valid_bits = 0;
 455         unsigned int reg_addr = 0;
 456         unsigned int addr = (i2c->addr_1st << 1) | 1;
 457
 458         if(num == 1) {
 459                 i2c->count = msgs[0].len;
 460                 if(!(msgs[0].flags & I2C_M_RD)){
 461                         i2c->msg = &msgs[0];
 462                         i2c->mode = I2C_CON_MOD_TX;
 463                 }
 464                 else {
 465                         i2c->msg = &msgs[0];
 466                         i2c_writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
 467                         i2c_writel(0, i2c->regs + I2C_MRXRADDR);
 468                         i2c->mode = I2C_CON_MOD_TRX;
 469                         //i2c->mode = I2C_CON_MOD_RX;
 470                 }
 471         }
 472         else if(num == 2) {
 473                 i2c->count = msgs[1].len;
 474
 475                 if(msgs[0].flags & I2C_M_TEN){
 476                         switch(msgs[0].len){
 477                         case 1:
 478                                 reg_addr = i2c->addr_2nd | (msgs[0].buf[0] << 8);
 479                                 reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID;
 480                                 break;
 481                         case 2:
 482                                 reg_addr = i2c->addr_2nd | (msgs[0].buf[0] << 8) | (msgs[0].buf[1] << 16);
 483                                 reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID | I2C_MRXADDR_HIGH;
 484                                 break;
 485                         default:
 486                                 return -EIO;
 487                         }
 488                 }else{
 489                         switch(msgs[0].len){
 490                         case 1:
 491                                 reg_addr = msgs[0].buf[0];
 492                                 reg_valid_bits |= I2C_MRXADDR_LOW;
 493                         break;
 494                         case 2:
 495                                 reg_addr = msgs[0].buf[0] | (msgs[0].buf[1] << 8);
 496                                 reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID;
 497                                 break;
 498                         case 3:
 499                                 reg_addr = msgs[0].buf[0] | (msgs[0].buf[1] << 8) | (msgs[0].buf[2] << 16);
 500                                 reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID | I2C_MRXADDR_HIGH;
 501                                 break;
 502                         default:
 503                                 return -EIO;
 504                         }
 505                 }
 506                 if((msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
 507                         i2c->msg = &msgs[1];
 508                         i2c_writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
 509                         i2c_writel(reg_addr | reg_valid_bits, i2c->regs + I2C_MRXRADDR);
 510                         i2c->mode = I2C_CON_MOD_RRX;
 511                 }
 512                 else if(!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
 513                         i2c->msg = &msgs[1];
 514                         i2c_writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
 515                         i2c_writel(reg_addr | reg_valid_bits, i2c->regs + I2C_MRXRADDR);
 516                         i2c->mode = I2C_CON_MOD_TRX;
 517                 }
 518                 else
 519                         return -EIO;
 520         }
 521         else {
 522                 dev_err(i2c->dev, "This case(num > 2) has not been support now\n");
 523                 return -EIO;
 524         }
 525
 526         return 0;
 527 }
 528 /* rk30_i2c_doxfer
 529  *
 530  * this starts an i2c transfer
 531 */
 532 static int rk30_i2c_doxfer(struct rk30_i2c *i2c,
 533                               struct i2c_msg *msgs, int num)
 534 {
 535         unsigned long timeout, flags;
 536         int error = 0;
 537         /* 32 -- max transfer bytes
 538          * 2 -- addr bytes * 2
 539          * 3 -- max reg addr bytes
 540          * 9 -- cycles per bytes
 541          * max cycles: (32 + 2 + 3) * 9 --> 400 cycles
 542          */
 543         int msleep_time = 400 * 1000/ i2c->scl_rate; // ms
 544
 545         if (i2c->suspended){
 546                 dev_err(i2c->dev, "i2c is suspended\n");
 547                 return -EIO;
 548         }
 549
 550         spin_lock_irqsave(&i2c->lock, flags);
 551         i2c->addr = msgs[0].addr;
 552         if(msgs[0].flags & I2C_M_TEN){
 553                 i2c->addr_1st = ((i2c->addr & 0x0300)>>8) | 0x78;
 554                 i2c->addr_2nd = i2c->addr & 0x00ff;
 555         }else{
 556                 i2c->addr_1st = i2c->addr & 0x007f;
 557                 i2c->addr_2nd = 0;
 558         }
 559         i2c_dbg(i2c->dev, "addr: 0x%04x, addr_1st: 0x%02x, addr_2nd: 0x%02x\n",
 560                         i2c->addr, i2c->addr_1st, i2c->addr_2nd);
 561
 562         if(rk30_i2c_set_master(i2c, msgs, num) < 0){
 563                 spin_unlock_irqrestore(&i2c->lock, flags);
 564                 dev_err(i2c->dev, "addr[0x%04x] set master error\n", msgs[0].addr);
 565                 return -EIO;
 566         }
 567         i2c->msg_ptr = 0;
 568         i2c->error = 0;
 569         i2c->is_busy = 1;
 570         i2c->state = STATE_START;
 571         i2c->complete_what = 0;
 572         i2c_writel(I2C_STARTIEN, i2c->regs + I2C_IEN);
 573         spin_unlock_irqrestore(&i2c->lock, flags);
 574
 575         rk30_i2c_enable(i2c, (i2c->count > 32)?0:1); //if count > 32,  byte(32) send ack
 576
 577         if (in_atomic()){
 578                 int tmo = I2C_WAIT_TIMEOUT * USEC_PER_MSEC;
 579                 while(tmo-- && i2c->is_busy != 0)
 580                         udelay(1);
 581                 timeout = (tmo <= 0)?0:1;
 582         }else
 583                 timeout = wait_event_timeout(i2c->wait, (i2c->is_busy == 0), msecs_to_jiffies(I2C_WAIT_TIMEOUT));
 584
 585         spin_lock_irqsave(&i2c->lock, flags);
 586         i2c->state = STATE_IDLE;
 587         error = i2c->error;
 588         spin_unlock_irqrestore(&i2c->lock, flags);
 589
 590         if (timeout == 0){
 591                 unsigned int ipd = i2c_readl(i2c->regs + I2C_IPD);
 592                 if(error < 0)
 593                         i2c_dbg(i2c->dev, "error = %d\n", error);
 594                 else if((i2c->complete_what !=COMPLETE_READ  && i2c->complete_what != COMPLETE_WRITE)){
 595                         if(ipd & I2C_HOLD_SCL)
 596                                 dev_err(i2c->dev, "SCL was hold by slave\n");
 597                         dev_err(i2c->dev, "Addr[0x%04x] wait event timeout, state: %d, is_busy: %d, error: %d, complete_what: 0x%x, ipd: 0x%x\n",
 598                                 msgs[0].addr, i2c->state, i2c->is_busy, error, i2c->complete_what, ipd);
 599                         //rk30_show_regs(i2c);
 600                         error = -ETIMEDOUT;
 601                         if(in_atomic())
 602                                 mdelay(msleep_time);
 603                         else
 604                                 msleep(msleep_time);
 605                         rk30_i2c_send_stop(i2c);
 606                         if(in_atomic())
 607                                 mdelay(1);
 608                         else
 609                                 msleep(1);
 610                 }
 611                 else
 612                         i2c_dbg(i2c->dev, "Addr[0x%02x] wait event timeout, but transfer complete\n", i2c->addr);
 613         }
 614         i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
 615         rk30_i2c_disable_irq(i2c);
 616         rk30_i2c_disable(i2c);
 617
 618         if(error == -EAGAIN)
 619                 i2c_dbg(i2c->dev, "No ack(complete_what: 0x%x), Maybe slave(addr: 0x%04x) not exist or abnormal power-on\n",
 620                                 i2c->complete_what, i2c->addr);
 621         return error;
 622 }
 623
 624 /* rk30_i2c_xfer
 625  *
 626  * first port of call from the i2c bus code when an message needs
 627  * transferring across the i2c bus.
 628 */
 629
 630 static int rk30_i2c_xfer(struct i2c_adapter *adap,
 631                         struct i2c_msg *msgs, int num)
 632 {
 633         int ret = 0, state, retry = 10;
 634         unsigned long scl_rate;
 635         struct rk30_i2c *i2c = (struct rk30_i2c *)adap->algo_data;
 636
 637         clk_enable(i2c->clk);
 638 #ifdef I2C_CHECK_IDLE
 639         while(retry-- && ((state = rk30_i2c_check_idle(i2c)) != I2C_IDLE)){
 640                 if(in_atomic())
 641                         mdelay(10);
 642                 else
 643                         msleep(10);
 644         }
 645         if(retry == 0){
 646                 dev_err(i2c->dev, "i2c is not in idle(state = %d)\n", state);
 647                 return -EIO;
 648         }
 649 #endif
 650
 651         if(msgs[0].scl_rate <= 400000 && msgs[0].scl_rate >= 10000)
 652                 scl_rate = msgs[0].scl_rate;
 653         else if(msgs[0].scl_rate > 400000){
 654                 dev_warn(i2c->dev, "Warning: addr[0x%04x] msg[0].scl_rate( = %dKhz) is too high!",
 655                         msgs[0].addr, msgs[0].scl_rate/1000);
 656                 scl_rate = 400000;
 657         }
 658         else{
 659                 dev_warn(i2c->dev, "Warning: addr[0x%04x] msg[0].scl_rate( = %dKhz) is too low!",
 660                         msgs[0].addr, msgs[0].scl_rate/1000);
 661                 scl_rate = 10000;
 662         }
 663         if(i2c->is_div_from_arm[i2c->adap.nr]){
 664                 mutex_lock(&i2c->m_lock);
 665         }
 666
 667         rk30_i2c_set_clk(i2c, scl_rate);
 668         i2c_dbg(i2c->dev, "i2c transfer start: addr: 0x%04x, scl_reate: %ldKhz, len: %d\n", msgs[0].addr, scl_rate/1000, num);
 669         ret = rk30_i2c_doxfer(i2c, msgs, num);
 670         i2c_dbg(i2c->dev, "i2c transfer stop: addr: 0x%04x, state: %d, ret: %d\n", msgs[0].addr, ret, i2c->state);
 671
 672         if(i2c->is_div_from_arm[i2c->adap.nr]){
 673                 mutex_unlock(&i2c->m_lock);
 674         }
 675
 676         clk_disable(i2c->clk);
 677         return (ret < 0)?ret:num;
 678 }
 679
 680 /* declare our i2c functionality */
 681 static u32 rk30_i2c_func(struct i2c_adapter *adap)
 682 {
 683         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
 684 }
 685
 686 /* i2c bus registration info */
 687
 688 static const struct i2c_algorithm rk30_i2c_algorithm = {
 689         .master_xfer            = rk30_i2c_xfer,
 690         .functionality          = rk30_i2c_func,
 691 };
 692
 693 int i2c_add_rk30_adapter(struct i2c_adapter *adap)
 694 {
 695         int ret = 0;
 696         struct rk30_i2c *i2c = (struct rk30_i2c *)adap->algo_data;
 697
 698         adap->algo = &rk30_i2c_algorithm;
 699
 700         i2c->i2c_init_hw = &rk30_i2c_init_hw;
 701         i2c->i2c_set_clk = &rk30_i2c_set_clk;
 702         i2c->i2c_irq = &rk30_i2c_irq;
 703
 704         ret = i2c_add_numbered_adapter(adap);
 705
 706         return ret;
 707 }
 708