drivers/i2c/busses/i2c-ocores.c

   1 /*
   2  * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
   3  * (http://www.opencores.org/projects.cgi/web/i2c/overview).
   4  *
   5  * Peter Korsgaard <jacmet@sunsite.dk>
   6  *
   7  * Support for the GRLIB port of the controller by
   8  * Andreas Larsson <andreas@gaisler.com>
   9  *
  10  * This file is licensed under the terms of the GNU General Public License
  11  * version 2.  This program is licensed "as is" without any warranty of any
  12  * kind, whether express or implied.
  13  */
  14
  15 #include <linux/err.h>
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/init.h>
  19 #include <linux/errno.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/i2c.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/wait.h>
  24 #include <linux/i2c-ocores.h>
  25 #include <linux/slab.h>
  26 #include <linux/io.h>
  27 #include <linux/of_i2c.h>
  28 #include <linux/log2.h>
  29
  30 struct ocores_i2c {
  31         void __iomem *base;
  32         u32 reg_shift;
  33         u32 reg_io_width;
  34         wait_queue_head_t wait;
  35         struct i2c_adapter adap;
  36         struct i2c_msg *msg;
  37         int pos;
  38         int nmsgs;
  39         int state; /* see STATE_ */
  40         int clock_khz;
  41         void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value);
  42         u8 (*getreg)(struct ocores_i2c *i2c, int reg);
  43 };
  44
  45 /* registers */
  46 #define OCI2C_PRELOW            0
  47 #define OCI2C_PREHIGH           1
  48 #define OCI2C_CONTROL           2
  49 #define OCI2C_DATA              3
  50 #define OCI2C_CMD               4 /* write only */
  51 #define OCI2C_STATUS            4 /* read only, same address as OCI2C_CMD */
  52
  53 #define OCI2C_CTRL_IEN          0x40
  54 #define OCI2C_CTRL_EN           0x80
  55
  56 #define OCI2C_CMD_START         0x91
  57 #define OCI2C_CMD_STOP          0x41
  58 #define OCI2C_CMD_READ          0x21
  59 #define OCI2C_CMD_WRITE         0x11
  60 #define OCI2C_CMD_READ_ACK      0x21
  61 #define OCI2C_CMD_READ_NACK     0x29
  62 #define OCI2C_CMD_IACK          0x01
  63
  64 #define OCI2C_STAT_IF           0x01
  65 #define OCI2C_STAT_TIP          0x02
  66 #define OCI2C_STAT_ARBLOST      0x20
  67 #define OCI2C_STAT_BUSY         0x40
  68 #define OCI2C_STAT_NACK         0x80
  69
  70 #define STATE_DONE              0
  71 #define STATE_START             1
  72 #define STATE_WRITE             2
  73 #define STATE_READ              3
  74 #define STATE_ERROR             4
  75
  76 #define TYPE_OCORES             0
  77 #define TYPE_GRLIB              1
  78
  79 static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value)
  80 {
  81         iowrite8(value, i2c->base + (reg << i2c->reg_shift));
  82 }
  83
  84 static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value)
  85 {
  86         iowrite16(value, i2c->base + (reg << i2c->reg_shift));
  87 }
  88
  89 static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value)
  90 {
  91         iowrite32(value, i2c->base + (reg << i2c->reg_shift));
  92 }
  93
  94 static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg)
  95 {
  96         return ioread8(i2c->base + (reg << i2c->reg_shift));
  97 }
  98
  99 static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg)
 100 {
 101         return ioread16(i2c->base + (reg << i2c->reg_shift));
 102 }
 103
 104 static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg)
 105 {
 106         return ioread32(i2c->base + (reg << i2c->reg_shift));
 107 }
 108
 109 static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
 110 {
 111         i2c->setreg(i2c, reg, value);
 112 }
 113
 114 static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
 115 {
 116         return i2c->getreg(i2c, reg);
 117 }
 118
 119 static void ocores_process(struct ocores_i2c *i2c)
 120 {
 121         struct i2c_msg *msg = i2c->msg;
 122         u8 stat = oc_getreg(i2c, OCI2C_STATUS);
 123
 124         if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) {
 125                 /* stop has been sent */
 126                 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
 127                 wake_up(&i2c->wait);
 128                 return;
 129         }
 130
 131         /* error? */
 132         if (stat & OCI2C_STAT_ARBLOST) {
 133                 i2c->state = STATE_ERROR;
 134                 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
 135                 return;
 136         }
 137
 138         if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) {
 139                 i2c->state =
 140                         (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
 141
 142                 if (stat & OCI2C_STAT_NACK) {
 143                         i2c->state = STATE_ERROR;
 144                         oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
 145                         return;
 146                 }
 147         } else
 148                 msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
 149
 150         /* end of msg? */
 151         if (i2c->pos == msg->len) {
 152                 i2c->nmsgs--;
 153                 i2c->msg++;
 154                 i2c->pos = 0;
 155                 msg = i2c->msg;
 156
 157                 if (i2c->nmsgs) {       /* end? */
 158                         /* send start? */
 159                         if (!(msg->flags & I2C_M_NOSTART)) {
 160                                 u8 addr = (msg->addr << 1);
 161
 162                                 if (msg->flags & I2C_M_RD)
 163                                         addr |= 1;
 164
 165                                 i2c->state = STATE_START;
 166
 167                                 oc_setreg(i2c, OCI2C_DATA, addr);
 168                                 oc_setreg(i2c, OCI2C_CMD,  OCI2C_CMD_START);
 169                                 return;
 170                         } else
 171                                 i2c->state = (msg->flags & I2C_M_RD)
 172                                         ? STATE_READ : STATE_WRITE;
 173                 } else {
 174                         i2c->state = STATE_DONE;
 175                         oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
 176                         return;
 177                 }
 178         }
 179
 180         if (i2c->state == STATE_READ) {
 181                 oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
 182                           OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
 183         } else {
 184                 oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
 185                 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
 186         }
 187 }
 188
 189 static irqreturn_t ocores_isr(int irq, void *dev_id)
 190 {
 191         struct ocores_i2c *i2c = dev_id;
 192
 193         ocores_process(i2c);
 194
 195         return IRQ_HANDLED;
 196 }
 197
 198 static int ocores_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 199 {
 200         struct ocores_i2c *i2c = i2c_get_adapdata(adap);
 201
 202         i2c->msg = msgs;
 203         i2c->pos = 0;
 204         i2c->nmsgs = num;
 205         i2c->state = STATE_START;
 206
 207         oc_setreg(i2c, OCI2C_DATA,
 208                         (i2c->msg->addr << 1) |
 209                         ((i2c->msg->flags & I2C_M_RD) ? 1:0));
 210
 211         oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
 212
 213         if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
 214                                (i2c->state == STATE_DONE), HZ))
 215                 return (i2c->state == STATE_DONE) ? num : -EIO;
 216         else
 217                 return -ETIMEDOUT;
 218 }
 219
 220 static void ocores_init(struct ocores_i2c *i2c)
 221 {
 222         int prescale;
 223         u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
 224
 225         /* make sure the device is disabled */
 226         oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
 227
 228         prescale = (i2c->clock_khz / (5*100)) - 1;
 229         oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
 230         oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);
 231
 232         /* Init the device */
 233         oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
 234         oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN | OCI2C_CTRL_EN);
 235 }
 236
 237
 238 static u32 ocores_func(struct i2c_adapter *adap)
 239 {
 240         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 241 }
 242
 243 static const struct i2c_algorithm ocores_algorithm = {
 244         .master_xfer    = ocores_xfer,
 245         .functionality  = ocores_func,
 246 };
 247
 248 static struct i2c_adapter ocores_adapter = {
 249         .owner          = THIS_MODULE,
 250         .name           = "i2c-ocores",
 251         .class          = I2C_CLASS_HWMON | I2C_CLASS_SPD,
 252         .algo           = &ocores_algorithm,
 253 };
 254
 255 static struct of_device_id ocores_i2c_match[] = {
 256         {
 257                 .compatible = "opencores,i2c-ocores",
 258                 .data = (void *)TYPE_OCORES,
 259         },
 260         {
 261                 .compatible = "aeroflexgaisler,i2cmst",
 262                 .data = (void *)TYPE_GRLIB,
 263         },
 264         {},
 265 };
 266 MODULE_DEVICE_TABLE(of, ocores_i2c_match);
 267
 268 #ifdef CONFIG_OF
 269 /* Read and write functions for the GRLIB port of the controller. Registers are
 270  * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
 271  * register. The subsequent registers has their offset decreased accordingly. */
 272 static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
 273 {
 274         u32 rd;
 275         int rreg = reg;
 276         if (reg != OCI2C_PRELOW)
 277                 rreg--;
 278         rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
 279         if (reg == OCI2C_PREHIGH)
 280                 return (u8)(rd >> 8);
 281         else
 282                 return (u8)rd;
 283 }
 284
 285 static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
 286 {
 287         u32 curr, wr;
 288         int rreg = reg;
 289         if (reg != OCI2C_PRELOW)
 290                 rreg--;
 291         if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
 292                 curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
 293                 if (reg == OCI2C_PRELOW)
 294                         wr = (curr & 0xff00) | value;
 295                 else
 296                         wr = (((u32)value) << 8) | (curr & 0xff);
 297         } else {
 298                 wr = value;
 299         }
 300         iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
 301 }
 302
 303 static int ocores_i2c_of_probe(struct platform_device *pdev,
 304                                 struct ocores_i2c *i2c)
 305 {
 306         struct device_node *np = pdev->dev.of_node;
 307         const struct of_device_id *match;
 308         u32 val;
 309
 310         if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) {
 311                 /* no 'reg-shift', check for deprecated 'regstep' */
 312                 if (!of_property_read_u32(np, "regstep", &val)) {
 313                         if (!is_power_of_2(val)) {
 314                                 dev_err(&pdev->dev, "invalid regstep %d\n",
 315                                         val);
 316                                 return -EINVAL;
 317                         }
 318                         i2c->reg_shift = ilog2(val);
 319                         dev_warn(&pdev->dev,
 320                                 "regstep property deprecated, use reg-shift\n");
 321                 }
 322         }
 323
 324         if (of_property_read_u32(np, "clock-frequency", &val)) {
 325                 dev_err(&pdev->dev,
 326                         "Missing required parameter 'clock-frequency'\n");
 327                 return -ENODEV;
 328         }
 329         i2c->clock_khz = val / 1000;
 330
 331         of_property_read_u32(pdev->dev.of_node, "reg-io-width",
 332                                 &i2c->reg_io_width);
 333
 334         match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
 335         if (match && (long)match->data == TYPE_GRLIB) {
 336                 dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n");
 337                 i2c->setreg = oc_setreg_grlib;
 338                 i2c->getreg = oc_getreg_grlib;
 339         }
 340
 341         return 0;
 342 }
 343 #else
 344 #define ocores_i2c_of_probe(pdev,i2c) -ENODEV
 345 #endif
 346
 347 static int ocores_i2c_probe(struct platform_device *pdev)
 348 {
 349         struct ocores_i2c *i2c;
 350         struct ocores_i2c_platform_data *pdata;
 351         struct resource *res;
 352         int irq;
 353         int ret;
 354         int i;
 355
 356         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 357         if (!res)
 358                 return -ENODEV;
 359
 360         irq = platform_get_irq(pdev, 0);
 361         if (irq < 0)
 362                 return irq;
 363
 364         i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
 365         if (!i2c)
 366                 return -ENOMEM;
 367
 368         i2c->base = devm_ioremap_resource(&pdev->dev, res);
 369         if (IS_ERR(i2c->base))
 370                 return PTR_ERR(i2c->base);
 371
 372         pdata = pdev->dev.platform_data;
 373         if (pdata) {
 374                 i2c->reg_shift = pdata->reg_shift;
 375                 i2c->reg_io_width = pdata->reg_io_width;
 376                 i2c->clock_khz = pdata->clock_khz;
 377         } else {
 378                 ret = ocores_i2c_of_probe(pdev, i2c);
 379                 if (ret)
 380                         return ret;
 381         }
 382
 383         if (i2c->reg_io_width == 0)
 384                 i2c->reg_io_width = 1; /* Set to default value */
 385
 386         if (!i2c->setreg || !i2c->getreg) {
 387                 switch (i2c->reg_io_width) {
 388                 case 1:
 389                         i2c->setreg = oc_setreg_8;
 390                         i2c->getreg = oc_getreg_8;
 391                         break;
 392
 393                 case 2:
 394                         i2c->setreg = oc_setreg_16;
 395                         i2c->getreg = oc_getreg_16;
 396                         break;
 397
 398                 case 4:
 399                         i2c->setreg = oc_setreg_32;
 400                         i2c->getreg = oc_getreg_32;
 401                         break;
 402
 403                 default:
 404                         dev_err(&pdev->dev, "Unsupported I/O width (%d)\n",
 405                                 i2c->reg_io_width);
 406                         return -EINVAL;
 407                 }
 408         }
 409
 410         ocores_init(i2c);
 411
 412         init_waitqueue_head(&i2c->wait);
 413         ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0,
 414                                pdev->name, i2c);
 415         if (ret) {
 416                 dev_err(&pdev->dev, "Cannot claim IRQ\n");
 417                 return ret;
 418         }
 419
 420         /* hook up driver to tree */
 421         platform_set_drvdata(pdev, i2c);
 422         i2c->adap = ocores_adapter;
 423         i2c_set_adapdata(&i2c->adap, i2c);
 424         i2c->adap.dev.parent = &pdev->dev;
 425         i2c->adap.dev.of_node = pdev->dev.of_node;
 426
 427         /* add i2c adapter to i2c tree */
 428         ret = i2c_add_adapter(&i2c->adap);
 429         if (ret) {
 430                 dev_err(&pdev->dev, "Failed to add adapter\n");
 431                 return ret;
 432         }
 433
 434         /* add in known devices to the bus */
 435         if (pdata) {
 436                 for (i = 0; i < pdata->num_devices; i++)
 437                         i2c_new_device(&i2c->adap, pdata->devices + i);
 438         } else {
 439                 of_i2c_register_devices(&i2c->adap);
 440         }
 441
 442         return 0;
 443 }
 444
 445 static int ocores_i2c_remove(struct platform_device *pdev)
 446 {
 447         struct ocores_i2c *i2c = platform_get_drvdata(pdev);
 448
 449         /* disable i2c logic */
 450         oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL)
 451                   & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
 452
 453         /* remove adapter & data */
 454         i2c_del_adapter(&i2c->adap);
 455
 456         return 0;
 457 }
 458
 459 #ifdef CONFIG_PM
 460 static int ocores_i2c_suspend(struct device *dev)
 461 {
 462         struct ocores_i2c *i2c = dev_get_drvdata(dev);
 463         u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
 464
 465         /* make sure the device is disabled */
 466         oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
 467
 468         return 0;
 469 }
 470
 471 static int ocores_i2c_resume(struct device *dev)
 472 {
 473         struct ocores_i2c *i2c = dev_get_drvdata(dev);
 474
 475         ocores_init(i2c);
 476
 477         return 0;
 478 }
 479
 480 static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume);
 481 #define OCORES_I2C_PM   (&ocores_i2c_pm)
 482 #else
 483 #define OCORES_I2C_PM   NULL
 484 #endif
 485
 486 static struct platform_driver ocores_i2c_driver = {
 487         .probe   = ocores_i2c_probe,
 488         .remove  = ocores_i2c_remove,
 489         .driver  = {
 490                 .owner = THIS_MODULE,
 491                 .name = "ocores-i2c",
 492                 .of_match_table = ocores_i2c_match,
 493                 .pm = OCORES_I2C_PM,
 494         },
 495 };
 496
 497 module_platform_driver(ocores_i2c_driver);
 498
 499 MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
 500 MODULE_DESCRIPTION("OpenCores I2C bus driver");
 501 MODULE_LICENSE("GPL");
 502 MODULE_ALIAS("platform:ocores-i2c");