2 * Copyright (C) 2009 ST-Ericsson SA
3 * Copyright (C) 2009 STMicroelectronics
5 * I2C master mode controller driver, used in Nomadik 8815
8 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
9 * Author: Sachin Verma <sachin.verma@st.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2, as
13 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/amba/bus.h>
18 #include <linux/atomic.h>
19 #include <linux/slab.h>
20 #include <linux/interrupt.h>
21 #include <linux/i2c.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/platform_data/i2c-nomadik.h>
28 #include <linux/of_i2c.h>
30 #define DRIVER_NAME "nmk-i2c"
32 /* I2C Controller register offsets */
33 #define I2C_CR (0x000)
34 #define I2C_SCR (0x004)
35 #define I2C_HSMCR (0x008)
36 #define I2C_MCR (0x00C)
37 #define I2C_TFR (0x010)
38 #define I2C_SR (0x014)
39 #define I2C_RFR (0x018)
40 #define I2C_TFTR (0x01C)
41 #define I2C_RFTR (0x020)
42 #define I2C_DMAR (0x024)
43 #define I2C_BRCR (0x028)
44 #define I2C_IMSCR (0x02C)
45 #define I2C_RISR (0x030)
46 #define I2C_MISR (0x034)
47 #define I2C_ICR (0x038)
49 /* Control registers */
50 #define I2C_CR_PE (0x1 << 0) /* Peripheral Enable */
51 #define I2C_CR_OM (0x3 << 1) /* Operating mode */
52 #define I2C_CR_SAM (0x1 << 3) /* Slave addressing mode */
53 #define I2C_CR_SM (0x3 << 4) /* Speed mode */
54 #define I2C_CR_SGCM (0x1 << 6) /* Slave general call mode */
55 #define I2C_CR_FTX (0x1 << 7) /* Flush Transmit */
56 #define I2C_CR_FRX (0x1 << 8) /* Flush Receive */
57 #define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */
58 #define I2C_CR_DMA_RX_EN (0x1 << 10) /* DMA Rx Enable */
59 #define I2C_CR_DMA_SLE (0x1 << 11) /* DMA sync. logic enable */
60 #define I2C_CR_LM (0x1 << 12) /* Loopback mode */
61 #define I2C_CR_FON (0x3 << 13) /* Filtering on */
62 #define I2C_CR_FS (0x3 << 15) /* Force stop enable */
64 /* Master controller (MCR) register */
65 #define I2C_MCR_OP (0x1 << 0) /* Operation */
66 #define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */
67 #define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */
68 #define I2C_MCR_SB (0x1 << 11) /* Extended address */
69 #define I2C_MCR_AM (0x3 << 12) /* Address type */
70 #define I2C_MCR_STOP (0x1 << 14) /* Stop condition */
71 #define I2C_MCR_LENGTH (0x7ff << 15) /* Transaction length */
73 /* Status register (SR) */
74 #define I2C_SR_OP (0x3 << 0) /* Operation */
75 #define I2C_SR_STATUS (0x3 << 2) /* controller status */
76 #define I2C_SR_CAUSE (0x7 << 4) /* Abort cause */
77 #define I2C_SR_TYPE (0x3 << 7) /* Receive type */
78 #define I2C_SR_LENGTH (0x7ff << 9) /* Transfer length */
80 /* Interrupt mask set/clear (IMSCR) bits */
81 #define I2C_IT_TXFE (0x1 << 0)
82 #define I2C_IT_TXFNE (0x1 << 1)
83 #define I2C_IT_TXFF (0x1 << 2)
84 #define I2C_IT_TXFOVR (0x1 << 3)
85 #define I2C_IT_RXFE (0x1 << 4)
86 #define I2C_IT_RXFNF (0x1 << 5)
87 #define I2C_IT_RXFF (0x1 << 6)
88 #define I2C_IT_RFSR (0x1 << 16)
89 #define I2C_IT_RFSE (0x1 << 17)
90 #define I2C_IT_WTSR (0x1 << 18)
91 #define I2C_IT_MTD (0x1 << 19)
92 #define I2C_IT_STD (0x1 << 20)
93 #define I2C_IT_MAL (0x1 << 24)
94 #define I2C_IT_BERR (0x1 << 25)
95 #define I2C_IT_MTDWS (0x1 << 28)
97 #define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask))
99 /* some bits in ICR are reserved */
100 #define I2C_CLEAR_ALL_INTS 0x131f007f
102 /* first three msb bits are reserved */
103 #define IRQ_MASK(mask) (mask & 0x1fffffff)
105 /* maximum threshold value */
106 #define MAX_I2C_FIFO_THRESHOLD 15
117 I2C_NO_OPERATION = 0xff,
123 * struct i2c_nmk_client - client specific data
124 * @slave_adr: 7-bit slave address
125 * @count: no. bytes to be transferred
126 * @buffer: client data buffer
127 * @xfer_bytes: bytes transferred till now
128 * @operation: current I2C operation
130 struct i2c_nmk_client {
131 unsigned short slave_adr;
133 unsigned char *buffer;
134 unsigned long xfer_bytes;
135 enum i2c_operation operation;
139 * struct nmk_i2c_dev - private data structure of the controller.
140 * @adev: parent amba device.
141 * @adap: corresponding I2C adapter.
142 * @irq: interrupt line for the controller.
143 * @virtbase: virtual io memory area.
144 * @clk: hardware i2c block clock.
145 * @cfg: machine provided controller configuration.
146 * @cli: holder of client specific data.
147 * @stop: stop condition.
148 * @xfer_complete: acknowledge completion for a I2C message.
149 * @result: controller propogated result.
150 * @busy: Busy doing transfer.
153 struct amba_device *adev;
154 struct i2c_adapter adap;
156 void __iomem *virtbase;
158 struct nmk_i2c_controller cfg;
159 struct i2c_nmk_client cli;
161 struct completion xfer_complete;
166 /* controller's abort causes */
167 static const char *abort_causes[] = {
168 "no ack received after address transmission",
169 "no ack received during data phase",
170 "ack received after xmission of master code",
171 "master lost arbitration",
174 "overflow, maxsize is 2047 bytes",
177 static inline void i2c_set_bit(void __iomem *reg, u32 mask)
179 writel(readl(reg) | mask, reg);
182 static inline void i2c_clr_bit(void __iomem *reg, u32 mask)
184 writel(readl(reg) & ~mask, reg);
188 * flush_i2c_fifo() - This function flushes the I2C FIFO
189 * @dev: private data of I2C Driver
191 * This function flushes the I2C Tx and Rx FIFOs. It returns
192 * 0 on successful flushing of FIFO
194 static int flush_i2c_fifo(struct nmk_i2c_dev *dev)
196 #define LOOP_ATTEMPTS 10
198 unsigned long timeout;
201 * flush the transmit and receive FIFO. The flushing
202 * operation takes several cycles before to be completed.
203 * On the completion, the I2C internal logic clears these
204 * bits, until then no one must access Tx, Rx FIFO and
205 * should poll on these bits waiting for the completion.
207 writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR);
209 for (i = 0; i < LOOP_ATTEMPTS; i++) {
210 timeout = jiffies + dev->adap.timeout;
212 while (!time_after(jiffies, timeout)) {
213 if ((readl(dev->virtbase + I2C_CR) &
214 (I2C_CR_FTX | I2C_CR_FRX)) == 0)
219 dev_err(&dev->adev->dev,
220 "flushing operation timed out giving up after %d attempts",
227 * disable_all_interrupts() - Disable all interrupts of this I2c Bus
228 * @dev: private data of I2C Driver
230 static void disable_all_interrupts(struct nmk_i2c_dev *dev)
232 u32 mask = IRQ_MASK(0);
233 writel(mask, dev->virtbase + I2C_IMSCR);
237 * clear_all_interrupts() - Clear all interrupts of I2C Controller
238 * @dev: private data of I2C Driver
240 static void clear_all_interrupts(struct nmk_i2c_dev *dev)
243 mask = IRQ_MASK(I2C_CLEAR_ALL_INTS);
244 writel(mask, dev->virtbase + I2C_ICR);
248 * init_hw() - initialize the I2C hardware
249 * @dev: private data of I2C Driver
251 static int init_hw(struct nmk_i2c_dev *dev)
255 stat = flush_i2c_fifo(dev);
259 /* disable the controller */
260 i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
262 disable_all_interrupts(dev);
264 clear_all_interrupts(dev);
266 dev->cli.operation = I2C_NO_OPERATION;
272 /* enable peripheral, master mode operation */
273 #define DEFAULT_I2C_REG_CR ((1 << 1) | I2C_CR_PE)
276 * load_i2c_mcr_reg() - load the MCR register
277 * @dev: private data of controller
278 * @flags: message flags
280 static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev, u16 flags)
283 unsigned short slave_adr_3msb_bits;
285 mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1);
287 if (unlikely(flags & I2C_M_TEN)) {
288 /* 10-bit address transaction */
289 mcr |= GEN_MASK(2, I2C_MCR_AM, 12);
291 * Get the top 3 bits.
292 * EA10 represents extended address in MCR. This includes
293 * the extension (MSB bits) of the 7 bit address loaded
296 slave_adr_3msb_bits = (dev->cli.slave_adr >> 7) & 0x7;
298 mcr |= GEN_MASK(slave_adr_3msb_bits, I2C_MCR_EA10, 8);
300 /* 7-bit address transaction */
301 mcr |= GEN_MASK(1, I2C_MCR_AM, 12);
304 /* start byte procedure not applied */
305 mcr |= GEN_MASK(0, I2C_MCR_SB, 11);
307 /* check the operation, master read/write? */
308 if (dev->cli.operation == I2C_WRITE)
309 mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0);
311 mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0);
313 /* stop or repeated start? */
315 mcr |= GEN_MASK(1, I2C_MCR_STOP, 14);
317 mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14));
319 mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15);
325 * setup_i2c_controller() - setup the controller
326 * @dev: private data of controller
328 static void setup_i2c_controller(struct nmk_i2c_dev *dev)
333 writel(0x0, dev->virtbase + I2C_CR);
334 writel(0x0, dev->virtbase + I2C_HSMCR);
335 writel(0x0, dev->virtbase + I2C_TFTR);
336 writel(0x0, dev->virtbase + I2C_RFTR);
337 writel(0x0, dev->virtbase + I2C_DMAR);
342 * slsu defines the data setup time after SCL clock
343 * stretching in terms of i2c clk cycles. The
344 * needed setup time for the three modes are 250ns,
345 * 100ns, 10ns respectively thus leading to the values
346 * of 14, 6, 2 for a 48 MHz i2c clk.
348 writel(dev->cfg.slsu << 16, dev->virtbase + I2C_SCR);
350 i2c_clk = clk_get_rate(dev->clk);
353 * The spec says, in case of std. mode the divider is
354 * 2 whereas it is 3 for fast and fastplus mode of
355 * operation. TODO - high speed support.
357 div = (dev->cfg.clk_freq > 100000) ? 3 : 2;
360 * generate the mask for baud rate counters. The controller
361 * has two baud rate counters. One is used for High speed
362 * operation, and the other is for std, fast mode, fast mode
363 * plus operation. Currently we do not supprt high speed mode
367 brcr2 = (i2c_clk/(dev->cfg.clk_freq * div)) & 0xffff;
369 /* set the baud rate counter register */
370 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
373 * set the speed mode. Currently we support
374 * only standard and fast mode of operation
375 * TODO - support for fast mode plus (up to 1Mb/s)
376 * and high speed (up to 3.4 Mb/s)
378 if (dev->cfg.sm > I2C_FREQ_MODE_FAST) {
379 dev_err(&dev->adev->dev,
380 "do not support this mode defaulting to std. mode\n");
381 brcr2 = i2c_clk/(100000 * 2) & 0xffff;
382 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
383 writel(I2C_FREQ_MODE_STANDARD << 4,
384 dev->virtbase + I2C_CR);
386 writel(dev->cfg.sm << 4, dev->virtbase + I2C_CR);
388 /* set the Tx and Rx FIFO threshold */
389 writel(dev->cfg.tft, dev->virtbase + I2C_TFTR);
390 writel(dev->cfg.rft, dev->virtbase + I2C_RFTR);
394 * read_i2c() - Read from I2C client device
395 * @dev: private data of I2C Driver
396 * @flags: message flags
398 * This function reads from i2c client device when controller is in
399 * master mode. There is a completion timeout. If there is no transfer
400 * before timeout error is returned.
402 static int read_i2c(struct nmk_i2c_dev *dev, u16 flags)
409 mcr = load_i2c_mcr_reg(dev, flags);
410 writel(mcr, dev->virtbase + I2C_MCR);
412 /* load the current CR value */
413 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
414 dev->virtbase + I2C_CR);
416 /* enable the controller */
417 i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
419 init_completion(&dev->xfer_complete);
421 /* enable interrupts by setting the mask */
422 irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF |
423 I2C_IT_MAL | I2C_IT_BERR);
426 irq_mask |= I2C_IT_MTD;
428 irq_mask |= I2C_IT_MTDWS;
430 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
432 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
433 dev->virtbase + I2C_IMSCR);
435 timeout = wait_for_completion_timeout(
436 &dev->xfer_complete, dev->adap.timeout);
439 dev_err(&dev->adev->dev,
440 "wait_for_completion_timeout "
441 "returned %d waiting for event\n", timeout);
446 /* Controller timed out */
447 dev_err(&dev->adev->dev, "read from slave 0x%x timed out\n",
454 static void fill_tx_fifo(struct nmk_i2c_dev *dev, int no_bytes)
458 for (count = (no_bytes - 2);
460 (dev->cli.count != 0);
462 /* write to the Tx FIFO */
463 writeb(*dev->cli.buffer,
464 dev->virtbase + I2C_TFR);
467 dev->cli.xfer_bytes++;
473 * write_i2c() - Write data to I2C client.
474 * @dev: private data of I2C Driver
475 * @flags: message flags
477 * This function writes data to I2C client
479 static int write_i2c(struct nmk_i2c_dev *dev, u16 flags)
486 mcr = load_i2c_mcr_reg(dev, flags);
488 writel(mcr, dev->virtbase + I2C_MCR);
490 /* load the current CR value */
491 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
492 dev->virtbase + I2C_CR);
494 /* enable the controller */
495 i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
497 init_completion(&dev->xfer_complete);
499 /* enable interrupts by settings the masks */
500 irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR);
502 /* Fill the TX FIFO with transmit data */
503 fill_tx_fifo(dev, MAX_I2C_FIFO_THRESHOLD);
505 if (dev->cli.count != 0)
506 irq_mask |= I2C_IT_TXFNE;
509 * check if we want to transfer a single or multiple bytes, if so
510 * set the MTDWS bit (Master Transaction Done Without Stop)
511 * to start repeated start operation
514 irq_mask |= I2C_IT_MTD;
516 irq_mask |= I2C_IT_MTDWS;
518 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
520 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
521 dev->virtbase + I2C_IMSCR);
523 timeout = wait_for_completion_timeout(
524 &dev->xfer_complete, dev->adap.timeout);
527 dev_err(&dev->adev->dev,
528 "wait_for_completion_timeout "
529 "returned %d waiting for event\n", timeout);
534 /* Controller timed out */
535 dev_err(&dev->adev->dev, "write to slave 0x%x timed out\n",
544 * nmk_i2c_xfer_one() - transmit a single I2C message
545 * @dev: device with a message encoded into it
546 * @flags: message flags
548 static int nmk_i2c_xfer_one(struct nmk_i2c_dev *dev, u16 flags)
552 if (flags & I2C_M_RD) {
554 dev->cli.operation = I2C_READ;
555 status = read_i2c(dev, flags);
557 /* write operation */
558 dev->cli.operation = I2C_WRITE;
559 status = write_i2c(dev, flags);
562 if (status || (dev->result)) {
566 i2c_sr = readl(dev->virtbase + I2C_SR);
568 * Check if the controller I2C operation status
569 * is set to ABORT(11b).
571 if (((i2c_sr >> 2) & 0x3) == 0x3) {
572 /* get the abort cause */
573 cause = (i2c_sr >> 4) & 0x7;
574 dev_err(&dev->adev->dev, "%s\n",
575 cause >= ARRAY_SIZE(abort_causes) ?
577 abort_causes[cause]);
582 status = status ? status : dev->result;
589 * nmk_i2c_xfer() - I2C transfer function used by kernel framework
590 * @i2c_adap: Adapter pointer to the controller
591 * @msgs: Pointer to data to be written.
592 * @num_msgs: Number of messages to be executed
594 * This is the function called by the generic kernel i2c_transfer()
595 * or i2c_smbus...() API calls. Note that this code is protected by the
596 * semaphore set in the kernel i2c_transfer() function.
599 * READ TRANSFER : We impose a restriction of the first message to be the
600 * index message for any read transaction.
601 * - a no index is coded as '0',
602 * - 2byte big endian index is coded as '3'
603 * !!! msg[0].buf holds the actual index.
604 * This is compatible with generic messages of smbus emulator
605 * that send a one byte index.
606 * eg. a I2C transation to read 2 bytes from index 0
608 * msg[0].addr = client->addr;
609 * msg[0].flags = 0x0;
613 * msg[1].addr = client->addr;
614 * msg[1].flags = I2C_M_RD;
616 * msg[1].buf = rd_buff
617 * i2c_transfer(adap, msg, 2);
619 * WRITE TRANSFER : The I2C standard interface interprets all data as payload.
620 * If you want to emulate an SMBUS write transaction put the
621 * index as first byte(or first and second) in the payload.
622 * eg. a I2C transation to write 2 bytes from index 1
626 * msg[0].flags = 0x0;
628 * msg[0].buf = wr_buff;
629 * i2c_transfer(adap, msg, 1);
631 * To read or write a block of data (multiple bytes) using SMBUS emulation
632 * please use the i2c_smbus_read_i2c_block_data()
633 * or i2c_smbus_write_i2c_block_data() API
635 static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap,
636 struct i2c_msg msgs[], int num_msgs)
640 struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap);
645 pm_runtime_get_sync(&dev->adev->dev);
647 status = clk_prepare_enable(dev->clk);
649 dev_err(&dev->adev->dev, "can't prepare_enable clock\n");
653 status = init_hw(dev);
657 /* Attempt three times to send the message queue */
658 for (j = 0; j < 3; j++) {
659 /* setup the i2c controller */
660 setup_i2c_controller(dev);
662 for (i = 0; i < num_msgs; i++) {
663 dev->cli.slave_adr = msgs[i].addr;
664 dev->cli.buffer = msgs[i].buf;
665 dev->cli.count = msgs[i].len;
666 dev->stop = (i < (num_msgs - 1)) ? 0 : 1;
669 status = nmk_i2c_xfer_one(dev, msgs[i].flags);
678 clk_disable_unprepare(dev->clk);
680 pm_runtime_put_sync(&dev->adev->dev);
684 /* return the no. messages processed */
692 * disable_interrupts() - disable the interrupts
693 * @dev: private data of controller
694 * @irq: interrupt number
696 static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq)
699 writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq),
700 dev->virtbase + I2C_IMSCR);
705 * i2c_irq_handler() - interrupt routine
706 * @irq: interrupt number
707 * @arg: data passed to the handler
709 * This is the interrupt handler for the i2c driver. Currently
710 * it handles the major interrupts like Rx & Tx FIFO management
711 * interrupts, master transaction interrupts, arbitration and
712 * bus error interrupts. The rest of the interrupts are treated as
715 static irqreturn_t i2c_irq_handler(int irq, void *arg)
717 struct nmk_i2c_dev *dev = arg;
723 /* load Tx FIFO and Rx FIFO threshold values */
724 tft = readl(dev->virtbase + I2C_TFTR);
725 rft = readl(dev->virtbase + I2C_RFTR);
727 /* read interrupt status register */
728 misr = readl(dev->virtbase + I2C_MISR);
731 switch ((1 << src)) {
733 /* Transmit FIFO nearly empty interrupt */
736 if (dev->cli.operation == I2C_READ) {
738 * in read operation why do we care for writing?
739 * so disable the Transmit FIFO interrupt
741 disable_interrupts(dev, I2C_IT_TXFNE);
743 fill_tx_fifo(dev, (MAX_I2C_FIFO_THRESHOLD - tft));
745 * if done, close the transfer by disabling the
746 * corresponding TXFNE interrupt
748 if (dev->cli.count == 0)
749 disable_interrupts(dev, I2C_IT_TXFNE);
755 * Rx FIFO nearly full interrupt.
756 * This is set when the numer of entries in Rx FIFO is
757 * greater or equal than the threshold value programmed
761 for (count = rft; count > 0; count--) {
762 /* Read the Rx FIFO */
763 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
766 dev->cli.count -= rft;
767 dev->cli.xfer_bytes += rft;
772 for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) {
773 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
776 dev->cli.count -= MAX_I2C_FIFO_THRESHOLD;
777 dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD;
780 /* Master Transaction Done with/without stop */
783 if (dev->cli.operation == I2C_READ) {
784 while (!(readl(dev->virtbase + I2C_RISR)
786 if (dev->cli.count == 0)
789 readb(dev->virtbase + I2C_RFR);
792 dev->cli.xfer_bytes++;
796 disable_all_interrupts(dev);
797 clear_all_interrupts(dev);
799 if (dev->cli.count) {
801 dev_err(&dev->adev->dev,
802 "%lu bytes still remain to be xfered\n",
806 complete(&dev->xfer_complete);
810 /* Master Arbitration lost interrupt */
815 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL);
816 complete(&dev->xfer_complete);
821 * Bus Error interrupt.
822 * This happens when an unexpected start/stop condition occurs
823 * during the transaction.
828 if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT)
831 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR);
832 complete(&dev->xfer_complete);
837 * Tx FIFO overrun interrupt.
838 * This is set when a write operation in Tx FIFO is performed and
839 * the Tx FIFO is full.
845 dev_err(&dev->adev->dev, "Tx Fifo Over run\n");
846 complete(&dev->xfer_complete);
850 /* unhandled interrupts by this driver - TODO*/
858 dev_err(&dev->adev->dev, "unhandled Interrupt\n");
861 dev_err(&dev->adev->dev, "spurious Interrupt..\n");
870 static int nmk_i2c_suspend(struct device *dev)
872 struct amba_device *adev = to_amba_device(dev);
873 struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev);
881 static int nmk_i2c_resume(struct device *dev)
886 #define nmk_i2c_suspend NULL
887 #define nmk_i2c_resume NULL
891 * We use noirq so that we suspend late and resume before the wakeup interrupt
892 * to ensure that we do the !pm_runtime_suspended() check in resume before
893 * there has been a regular pm runtime resume (via pm_runtime_get_sync()).
895 static const struct dev_pm_ops nmk_i2c_pm = {
896 .suspend_noirq = nmk_i2c_suspend,
897 .resume_noirq = nmk_i2c_resume,
900 static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap)
902 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
905 static const struct i2c_algorithm nmk_i2c_algo = {
906 .master_xfer = nmk_i2c_xfer,
907 .functionality = nmk_i2c_functionality
910 static struct nmk_i2c_controller u8500_i2c = {
912 * Slave data setup time; 250ns, 100ns, and 10ns, which
913 * is 14, 6 and 2 respectively for a 48Mhz i2c clock.
916 .tft = 1, /* Tx FIFO threshold */
917 .rft = 8, /* Rx FIFO threshold */
918 .clk_freq = 400000, /* fast mode operation */
919 .timeout = 200, /* Slave response timeout(ms) */
920 .sm = I2C_FREQ_MODE_FAST,
923 static void nmk_i2c_of_probe(struct device_node *np,
924 struct nmk_i2c_controller *pdata)
926 of_property_read_u32(np, "clock-frequency", &pdata->clk_freq);
928 /* This driver only supports 'standard' and 'fast' modes of operation. */
929 if (pdata->clk_freq <= 100000)
930 pdata->sm = I2C_FREQ_MODE_STANDARD;
932 pdata->sm = I2C_FREQ_MODE_FAST;
935 static atomic_t adapter_id = ATOMIC_INIT(0);
937 static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
940 struct nmk_i2c_controller *pdata = adev->dev.platform_data;
941 struct device_node *np = adev->dev.of_node;
942 struct nmk_i2c_dev *dev;
943 struct i2c_adapter *adap;
947 pdata = devm_kzalloc(&adev->dev, sizeof(*pdata), GFP_KERNEL);
952 /* Provide the default configuration as a base. */
953 memcpy(pdata, &u8500_i2c, sizeof(struct nmk_i2c_controller));
954 nmk_i2c_of_probe(np, pdata);
956 /* No i2c configuration found, using the default. */
960 dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL);
962 dev_err(&adev->dev, "cannot allocate memory\n");
968 amba_set_drvdata(adev, dev);
970 dev->virtbase = ioremap(adev->res.start, resource_size(&adev->res));
971 if (!dev->virtbase) {
976 dev->irq = adev->irq[0];
977 ret = request_irq(dev->irq, i2c_irq_handler, 0,
980 dev_err(&adev->dev, "cannot claim the irq %d\n", dev->irq);
984 pm_suspend_ignore_children(&adev->dev, true);
986 dev->clk = clk_get(&adev->dev, NULL);
987 if (IS_ERR(dev->clk)) {
988 dev_err(&adev->dev, "could not get i2c clock\n");
989 ret = PTR_ERR(dev->clk);
994 adap->dev.of_node = np;
995 adap->dev.parent = &adev->dev;
996 adap->owner = THIS_MODULE;
997 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
998 adap->algo = &nmk_i2c_algo;
999 adap->timeout = msecs_to_jiffies(pdata->timeout);
1000 adap->nr = atomic_read(&adapter_id);
1001 snprintf(adap->name, sizeof(adap->name),
1002 "Nomadik I2C%d at %pR", adap->nr, &adev->res);
1003 atomic_inc(&adapter_id);
1005 /* fetch the controller configuration from machine */
1006 dev->cfg.clk_freq = pdata->clk_freq;
1007 dev->cfg.slsu = pdata->slsu;
1008 dev->cfg.tft = pdata->tft;
1009 dev->cfg.rft = pdata->rft;
1010 dev->cfg.sm = pdata->sm;
1012 i2c_set_adapdata(adap, dev);
1014 dev_info(&adev->dev,
1015 "initialize %s on virtual base %p\n",
1016 adap->name, dev->virtbase);
1018 ret = i2c_add_numbered_adapter(adap);
1020 dev_err(&adev->dev, "failed to add adapter\n");
1024 of_i2c_register_devices(adap);
1026 pm_runtime_put(&adev->dev);
1033 free_irq(dev->irq, dev);
1035 iounmap(dev->virtbase);
1037 amba_set_drvdata(adev, NULL);
1044 static int nmk_i2c_remove(struct amba_device *adev)
1046 struct resource *res = &adev->res;
1047 struct nmk_i2c_dev *dev = amba_get_drvdata(adev);
1049 i2c_del_adapter(&dev->adap);
1050 flush_i2c_fifo(dev);
1051 disable_all_interrupts(dev);
1052 clear_all_interrupts(dev);
1053 /* disable the controller */
1054 i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
1055 free_irq(dev->irq, dev);
1056 iounmap(dev->virtbase);
1058 release_mem_region(res->start, resource_size(res));
1060 pm_runtime_disable(&adev->dev);
1061 amba_set_drvdata(adev, NULL);
1067 static struct amba_id nmk_i2c_ids[] = {
1079 MODULE_DEVICE_TABLE(amba, nmk_i2c_ids);
1081 static struct amba_driver nmk_i2c_driver = {
1083 .owner = THIS_MODULE,
1084 .name = DRIVER_NAME,
1087 .id_table = nmk_i2c_ids,
1088 .probe = nmk_i2c_probe,
1089 .remove = nmk_i2c_remove,
1092 static int __init nmk_i2c_init(void)
1094 return amba_driver_register(&nmk_i2c_driver);
1097 static void __exit nmk_i2c_exit(void)
1099 amba_driver_unregister(&nmk_i2c_driver);
1102 subsys_initcall(nmk_i2c_init);
1103 module_exit(nmk_i2c_exit);
1105 MODULE_AUTHOR("Sachin Verma, Srinidhi KASAGAR");
1106 MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver");
1107 MODULE_LICENSE("GPL");