2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
5 Copyright (C) 2007 - 2012 Jean Delvare <jdelvare@suse.de>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 * Supports the following Intel I/O Controller Hubs (ICH):
28 * region SMBus Block proc. block
29 * Chip name PCI ID size PEC buffer call read
30 * ---------------------------------------------------------------------------
31 * 82801AA (ICH) 0x2413 16 no no no no
32 * 82801AB (ICH0) 0x2423 16 no no no no
33 * 82801BA (ICH2) 0x2443 16 no no no no
34 * 82801CA (ICH3) 0x2483 32 soft no no no
35 * 82801DB (ICH4) 0x24c3 32 hard yes no no
36 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
37 * 6300ESB 0x25a4 32 hard yes yes yes
38 * 82801F (ICH6) 0x266a 32 hard yes yes yes
39 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
40 * 82801G (ICH7) 0x27da 32 hard yes yes yes
41 * 82801H (ICH8) 0x283e 32 hard yes yes yes
42 * 82801I (ICH9) 0x2930 32 hard yes yes yes
43 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
44 * ICH10 0x3a30 32 hard yes yes yes
45 * ICH10 0x3a60 32 hard yes yes yes
46 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
47 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
48 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
49 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
50 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
51 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
52 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
53 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
54 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
55 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
56 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
57 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
58 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
59 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
60 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
61 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
62 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
63 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
64 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
66 * Features supported by this driver:
70 * Block process call transaction no
71 * I2C block read transaction yes (doesn't use the block buffer)
73 * Interrupt processing yes
75 * See the file Documentation/i2c/busses/i2c-i801 for details.
78 #include <linux/interrupt.h>
79 #include <linux/module.h>
80 #include <linux/pci.h>
81 #include <linux/kernel.h>
82 #include <linux/stddef.h>
83 #include <linux/delay.h>
84 #include <linux/ioport.h>
85 #include <linux/init.h>
86 #include <linux/i2c.h>
87 #include <linux/acpi.h>
89 #include <linux/dmi.h>
90 #include <linux/slab.h>
91 #include <linux/wait.h>
92 #include <linux/err.h>
94 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
96 #include <linux/gpio.h>
97 #include <linux/i2c-mux-gpio.h>
98 #include <linux/platform_device.h>
101 /* I801 SMBus address offsets */
102 #define SMBHSTSTS(p) (0 + (p)->smba)
103 #define SMBHSTCNT(p) (2 + (p)->smba)
104 #define SMBHSTCMD(p) (3 + (p)->smba)
105 #define SMBHSTADD(p) (4 + (p)->smba)
106 #define SMBHSTDAT0(p) (5 + (p)->smba)
107 #define SMBHSTDAT1(p) (6 + (p)->smba)
108 #define SMBBLKDAT(p) (7 + (p)->smba)
109 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
110 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
111 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
113 /* PCI Address Constants */
115 #define SMBPCISTS 0x006
116 #define SMBHSTCFG 0x040
118 /* Host status bits for SMBPCISTS */
119 #define SMBPCISTS_INTS 0x08
121 /* Host configuration bits for SMBHSTCFG */
122 #define SMBHSTCFG_HST_EN 1
123 #define SMBHSTCFG_SMB_SMI_EN 2
124 #define SMBHSTCFG_I2C_EN 4
126 /* Auxiliary control register bits, ICH4+ only */
127 #define SMBAUXCTL_CRC 1
128 #define SMBAUXCTL_E32B 2
131 #define MAX_RETRIES 400
133 /* I801 command constants */
134 #define I801_QUICK 0x00
135 #define I801_BYTE 0x04
136 #define I801_BYTE_DATA 0x08
137 #define I801_WORD_DATA 0x0C
138 #define I801_PROC_CALL 0x10 /* unimplemented */
139 #define I801_BLOCK_DATA 0x14
140 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
142 /* I801 Host Control register bits */
143 #define SMBHSTCNT_INTREN 0x01
144 #define SMBHSTCNT_KILL 0x02
145 #define SMBHSTCNT_LAST_BYTE 0x20
146 #define SMBHSTCNT_START 0x40
147 #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */
149 /* I801 Hosts Status register bits */
150 #define SMBHSTSTS_BYTE_DONE 0x80
151 #define SMBHSTSTS_INUSE_STS 0x40
152 #define SMBHSTSTS_SMBALERT_STS 0x20
153 #define SMBHSTSTS_FAILED 0x10
154 #define SMBHSTSTS_BUS_ERR 0x08
155 #define SMBHSTSTS_DEV_ERR 0x04
156 #define SMBHSTSTS_INTR 0x02
157 #define SMBHSTSTS_HOST_BUSY 0x01
159 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
162 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
165 /* Older devices have their ID defined in <linux/pci_ids.h> */
166 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
167 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
168 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
169 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
170 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
171 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
172 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
173 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
174 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
175 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
176 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
177 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
178 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
179 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
180 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
181 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
182 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
183 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
184 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
185 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
187 struct i801_mux_config {
192 unsigned gpios[2]; /* Relative to gpio_chip->base */
197 struct i2c_adapter adapter;
199 unsigned char original_hstcfg;
200 struct pci_dev *pci_dev;
201 unsigned int features;
204 wait_queue_head_t waitq;
207 /* Command state used by isr for byte-by-byte block transactions */
214 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
216 const struct i801_mux_config *mux_drvdata;
217 struct platform_device *mux_pdev;
221 static struct pci_driver i801_driver;
223 #define FEATURE_SMBUS_PEC (1 << 0)
224 #define FEATURE_BLOCK_BUFFER (1 << 1)
225 #define FEATURE_BLOCK_PROC (1 << 2)
226 #define FEATURE_I2C_BLOCK_READ (1 << 3)
227 #define FEATURE_IRQ (1 << 4)
228 /* Not really a feature, but it's convenient to handle it as such */
229 #define FEATURE_IDF (1 << 15)
231 static const char *i801_feature_names[] = {
234 "Block process call",
239 static unsigned int disable_features;
240 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
241 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
242 "\t\t 0x01 disable SMBus PEC\n"
243 "\t\t 0x02 disable the block buffer\n"
244 "\t\t 0x08 disable the I2C block read functionality\n"
245 "\t\t 0x10 don't use interrupts ");
247 /* Make sure the SMBus host is ready to start transmitting.
248 Return 0 if it is, -EBUSY if it is not. */
249 static int i801_check_pre(struct i801_priv *priv)
253 status = inb_p(SMBHSTSTS(priv));
254 if (status & SMBHSTSTS_HOST_BUSY) {
255 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
259 status &= STATUS_FLAGS;
261 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
263 outb_p(status, SMBHSTSTS(priv));
264 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
266 dev_err(&priv->pci_dev->dev,
267 "Failed clearing status flags (%02x)\n",
277 * Convert the status register to an error code, and clear it.
278 * Note that status only contains the bits we want to clear, not the
279 * actual register value.
281 static int i801_check_post(struct i801_priv *priv, int status)
286 * If the SMBus is still busy, we give up
287 * Note: This timeout condition only happens when using polling
288 * transactions. For interrupt operation, NAK/timeout is indicated by
291 if (unlikely(status < 0)) {
292 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
293 /* try to stop the current command */
294 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
295 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
297 usleep_range(1000, 2000);
298 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
301 /* Check if it worked */
302 status = inb_p(SMBHSTSTS(priv));
303 if ((status & SMBHSTSTS_HOST_BUSY) ||
304 !(status & SMBHSTSTS_FAILED))
305 dev_err(&priv->pci_dev->dev,
306 "Failed terminating the transaction\n");
307 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
311 if (status & SMBHSTSTS_FAILED) {
313 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
315 if (status & SMBHSTSTS_DEV_ERR) {
317 dev_dbg(&priv->pci_dev->dev, "No response\n");
319 if (status & SMBHSTSTS_BUS_ERR) {
321 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
324 /* Clear status flags except BYTE_DONE, to be cleared by caller */
325 outb_p(status, SMBHSTSTS(priv));
330 /* Wait for BUSY being cleared and either INTR or an error flag being set */
331 static int i801_wait_intr(struct i801_priv *priv)
336 /* We will always wait for a fraction of a second! */
338 usleep_range(250, 500);
339 status = inb_p(SMBHSTSTS(priv));
340 } while (((status & SMBHSTSTS_HOST_BUSY) ||
341 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
342 (timeout++ < MAX_RETRIES));
344 if (timeout > MAX_RETRIES) {
345 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
348 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
351 /* Wait for either BYTE_DONE or an error flag being set */
352 static int i801_wait_byte_done(struct i801_priv *priv)
357 /* We will always wait for a fraction of a second! */
359 usleep_range(250, 500);
360 status = inb_p(SMBHSTSTS(priv));
361 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
362 (timeout++ < MAX_RETRIES));
364 if (timeout > MAX_RETRIES) {
365 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
368 return status & STATUS_ERROR_FLAGS;
371 static int i801_transaction(struct i801_priv *priv, int xact)
376 result = i801_check_pre(priv);
380 if (priv->features & FEATURE_IRQ) {
381 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
383 wait_event(priv->waitq, (status = priv->status));
385 return i801_check_post(priv, status);
388 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
389 * SMBSCMD are passed in xact */
390 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
392 status = i801_wait_intr(priv);
393 return i801_check_post(priv, status);
396 static int i801_block_transaction_by_block(struct i801_priv *priv,
397 union i2c_smbus_data *data,
398 char read_write, int hwpec)
403 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
405 /* Use 32-byte buffer to process this transaction */
406 if (read_write == I2C_SMBUS_WRITE) {
407 len = data->block[0];
408 outb_p(len, SMBHSTDAT0(priv));
409 for (i = 0; i < len; i++)
410 outb_p(data->block[i+1], SMBBLKDAT(priv));
413 status = i801_transaction(priv, I801_BLOCK_DATA |
414 (hwpec ? SMBHSTCNT_PEC_EN : 0));
418 if (read_write == I2C_SMBUS_READ) {
419 len = inb_p(SMBHSTDAT0(priv));
420 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
423 data->block[0] = len;
424 for (i = 0; i < len; i++)
425 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
430 static void i801_isr_byte_done(struct i801_priv *priv)
433 /* For SMBus block reads, length is received with first byte */
434 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
435 (priv->count == 0)) {
436 priv->len = inb_p(SMBHSTDAT0(priv));
437 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
438 dev_err(&priv->pci_dev->dev,
439 "Illegal SMBus block read size %d\n",
442 priv->len = I2C_SMBUS_BLOCK_MAX;
444 dev_dbg(&priv->pci_dev->dev,
445 "SMBus block read size is %d\n",
448 priv->data[-1] = priv->len;
452 if (priv->count < priv->len)
453 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
455 dev_dbg(&priv->pci_dev->dev,
456 "Discarding extra byte on block read\n");
458 /* Set LAST_BYTE for last byte of read transaction */
459 if (priv->count == priv->len - 1)
460 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
462 } else if (priv->count < priv->len - 1) {
463 /* Write next byte, except for IRQ after last byte */
464 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
467 /* Clear BYTE_DONE to continue with next byte */
468 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
472 * There are two kinds of interrupts:
474 * 1) i801 signals transaction completion with one of these interrupts:
476 * DEV_ERR - Invalid command, NAK or communication timeout
477 * BUS_ERR - SMI# transaction collision
478 * FAILED - transaction was canceled due to a KILL request
479 * When any of these occur, update ->status and wake up the waitq.
480 * ->status must be cleared before kicking off the next transaction.
482 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
483 * occurs for each byte of a byte-by-byte to prepare the next byte.
485 static irqreturn_t i801_isr(int irq, void *dev_id)
487 struct i801_priv *priv = dev_id;
491 /* Confirm this is our interrupt */
492 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
493 if (!(pcists & SMBPCISTS_INTS))
496 status = inb_p(SMBHSTSTS(priv));
498 dev_dbg(&priv->pci_dev->dev, "irq: status = %02x\n", status);
500 if (status & SMBHSTSTS_BYTE_DONE)
501 i801_isr_byte_done(priv);
504 * Clear irq sources and report transaction result.
505 * ->status must be cleared before the next transaction is started.
507 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
509 outb_p(status, SMBHSTSTS(priv));
510 priv->status |= status;
511 wake_up(&priv->waitq);
518 * For "byte-by-byte" block transactions:
519 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
520 * I2C read uses cmd=I801_I2C_BLOCK_DATA
522 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
523 union i2c_smbus_data *data,
524 char read_write, int command,
532 result = i801_check_pre(priv);
536 len = data->block[0];
538 if (read_write == I2C_SMBUS_WRITE) {
539 outb_p(len, SMBHSTDAT0(priv));
540 outb_p(data->block[1], SMBBLKDAT(priv));
543 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
544 read_write == I2C_SMBUS_READ)
545 smbcmd = I801_I2C_BLOCK_DATA;
547 smbcmd = I801_BLOCK_DATA;
549 if (priv->features & FEATURE_IRQ) {
550 priv->is_read = (read_write == I2C_SMBUS_READ);
551 if (len == 1 && priv->is_read)
552 smbcmd |= SMBHSTCNT_LAST_BYTE;
553 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
556 priv->data = &data->block[1];
558 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
559 wait_event(priv->waitq, (status = priv->status));
561 return i801_check_post(priv, status);
564 for (i = 1; i <= len; i++) {
565 if (i == len && read_write == I2C_SMBUS_READ)
566 smbcmd |= SMBHSTCNT_LAST_BYTE;
567 outb_p(smbcmd, SMBHSTCNT(priv));
570 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
573 status = i801_wait_byte_done(priv);
577 if (i == 1 && read_write == I2C_SMBUS_READ
578 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
579 len = inb_p(SMBHSTDAT0(priv));
580 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
581 dev_err(&priv->pci_dev->dev,
582 "Illegal SMBus block read size %d\n",
585 while (inb_p(SMBHSTSTS(priv)) &
587 outb_p(SMBHSTSTS_BYTE_DONE,
589 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
592 data->block[0] = len;
595 /* Retrieve/store value in SMBBLKDAT */
596 if (read_write == I2C_SMBUS_READ)
597 data->block[i] = inb_p(SMBBLKDAT(priv));
598 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
599 outb_p(data->block[i+1], SMBBLKDAT(priv));
601 /* signals SMBBLKDAT ready */
602 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
605 status = i801_wait_intr(priv);
607 return i801_check_post(priv, status);
610 static int i801_set_block_buffer_mode(struct i801_priv *priv)
612 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
613 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
618 /* Block transaction function */
619 static int i801_block_transaction(struct i801_priv *priv,
620 union i2c_smbus_data *data, char read_write,
621 int command, int hwpec)
626 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
627 if (read_write == I2C_SMBUS_WRITE) {
628 /* set I2C_EN bit in configuration register */
629 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
630 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
631 hostc | SMBHSTCFG_I2C_EN);
632 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
633 dev_err(&priv->pci_dev->dev,
634 "I2C block read is unsupported!\n");
639 if (read_write == I2C_SMBUS_WRITE
640 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
641 if (data->block[0] < 1)
643 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
644 data->block[0] = I2C_SMBUS_BLOCK_MAX;
646 data->block[0] = 32; /* max for SMBus block reads */
649 /* Experience has shown that the block buffer can only be used for
650 SMBus (not I2C) block transactions, even though the datasheet
651 doesn't mention this limitation. */
652 if ((priv->features & FEATURE_BLOCK_BUFFER)
653 && command != I2C_SMBUS_I2C_BLOCK_DATA
654 && i801_set_block_buffer_mode(priv) == 0)
655 result = i801_block_transaction_by_block(priv, data,
658 result = i801_block_transaction_byte_by_byte(priv, data,
662 if (command == I2C_SMBUS_I2C_BLOCK_DATA
663 && read_write == I2C_SMBUS_WRITE) {
664 /* restore saved configuration register value */
665 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
670 /* Return negative errno on error. */
671 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
672 unsigned short flags, char read_write, u8 command,
673 int size, union i2c_smbus_data *data)
678 struct i801_priv *priv = i2c_get_adapdata(adap);
680 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
681 && size != I2C_SMBUS_QUICK
682 && size != I2C_SMBUS_I2C_BLOCK_DATA;
685 case I2C_SMBUS_QUICK:
686 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
691 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
693 if (read_write == I2C_SMBUS_WRITE)
694 outb_p(command, SMBHSTCMD(priv));
697 case I2C_SMBUS_BYTE_DATA:
698 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
700 outb_p(command, SMBHSTCMD(priv));
701 if (read_write == I2C_SMBUS_WRITE)
702 outb_p(data->byte, SMBHSTDAT0(priv));
703 xact = I801_BYTE_DATA;
705 case I2C_SMBUS_WORD_DATA:
706 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
708 outb_p(command, SMBHSTCMD(priv));
709 if (read_write == I2C_SMBUS_WRITE) {
710 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
711 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
713 xact = I801_WORD_DATA;
715 case I2C_SMBUS_BLOCK_DATA:
716 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
718 outb_p(command, SMBHSTCMD(priv));
721 case I2C_SMBUS_I2C_BLOCK_DATA:
722 /* NB: page 240 of ICH5 datasheet shows that the R/#W
723 * bit should be cleared here, even when reading */
724 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
725 if (read_write == I2C_SMBUS_READ) {
726 /* NB: page 240 of ICH5 datasheet also shows
727 * that DATA1 is the cmd field when reading */
728 outb_p(command, SMBHSTDAT1(priv));
730 outb_p(command, SMBHSTCMD(priv));
734 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
739 if (hwpec) /* enable/disable hardware PEC */
740 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
742 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
746 ret = i801_block_transaction(priv, data, read_write, size,
749 ret = i801_transaction(priv, xact);
751 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
752 time, so we forcibly disable it after every transaction. Turn off
753 E32B for the same reason. */
755 outb_p(inb_p(SMBAUXCTL(priv)) &
756 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
762 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
765 switch (xact & 0x7f) {
766 case I801_BYTE: /* Result put in SMBHSTDAT0 */
768 data->byte = inb_p(SMBHSTDAT0(priv));
771 data->word = inb_p(SMBHSTDAT0(priv)) +
772 (inb_p(SMBHSTDAT1(priv)) << 8);
779 static u32 i801_func(struct i2c_adapter *adapter)
781 struct i801_priv *priv = i2c_get_adapdata(adapter);
783 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
784 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
785 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
786 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
787 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
788 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
791 static const struct i2c_algorithm smbus_algorithm = {
792 .smbus_xfer = i801_access,
793 .functionality = i801_func,
796 static const struct pci_device_id i801_ids[] = {
797 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
798 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
799 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
800 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
801 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
802 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
803 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
804 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
805 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
806 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
807 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
808 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
809 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
810 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
811 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
812 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
813 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
814 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
815 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
816 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
817 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
818 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
819 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
820 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
821 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
822 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
823 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
824 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
825 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
826 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
827 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
828 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
829 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
830 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
834 MODULE_DEVICE_TABLE(pci, i801_ids);
836 #if defined CONFIG_X86 && defined CONFIG_DMI
837 static unsigned char apanel_addr;
839 /* Scan the system ROM for the signature "FJKEYINF" */
840 static __init const void __iomem *bios_signature(const void __iomem *bios)
843 const unsigned char signature[] = "FJKEYINF";
845 for (offset = 0; offset < 0x10000; offset += 0x10) {
846 if (check_signature(bios + offset, signature,
847 sizeof(signature)-1))
848 return bios + offset;
853 static void __init input_apanel_init(void)
856 const void __iomem *p;
858 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
859 p = bios_signature(bios);
861 /* just use the first address */
862 apanel_addr = readb(p + 8 + 3) >> 1;
867 struct dmi_onboard_device_info {
870 unsigned short i2c_addr;
871 const char *i2c_type;
874 static const struct dmi_onboard_device_info dmi_devices[] = {
875 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
876 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
877 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
880 static void dmi_check_onboard_device(u8 type, const char *name,
881 struct i2c_adapter *adap)
884 struct i2c_board_info info;
886 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
887 /* & ~0x80, ignore enabled/disabled bit */
888 if ((type & ~0x80) != dmi_devices[i].type)
890 if (strcasecmp(name, dmi_devices[i].name))
893 memset(&info, 0, sizeof(struct i2c_board_info));
894 info.addr = dmi_devices[i].i2c_addr;
895 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
896 i2c_new_device(adap, &info);
901 /* We use our own function to check for onboard devices instead of
902 dmi_find_device() as some buggy BIOS's have the devices we are interested
903 in marked as disabled */
904 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
911 count = (dm->length - sizeof(struct dmi_header)) / 2;
912 for (i = 0; i < count; i++) {
913 const u8 *d = (char *)(dm + 1) + (i * 2);
914 const char *name = ((char *) dm) + dm->length;
921 while (s > 0 && name[0]) {
922 name += strlen(name) + 1;
925 if (name[0] == 0) /* Bogus string reference */
928 dmi_check_onboard_device(type, name, adap);
932 /* Register optional slaves */
933 static void i801_probe_optional_slaves(struct i801_priv *priv)
935 /* Only register slaves on main SMBus channel */
936 if (priv->features & FEATURE_IDF)
940 struct i2c_board_info info;
942 memset(&info, 0, sizeof(struct i2c_board_info));
943 info.addr = apanel_addr;
944 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
945 i2c_new_device(&priv->adapter, &info);
948 if (dmi_name_in_vendors("FUJITSU"))
949 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
952 static void __init input_apanel_init(void) {}
953 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
954 #endif /* CONFIG_X86 && CONFIG_DMI */
956 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
958 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
959 .gpio_chip = "gpio_ich",
960 .values = { 0x02, 0x03 },
962 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
967 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
968 .gpio_chip = "gpio_ich",
969 .values = { 0x02, 0x03, 0x01 },
971 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
976 static const struct dmi_system_id mux_dmi_table[] = {
979 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
980 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
982 .driver_data = &i801_mux_config_asus_z8_d12,
986 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
987 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
989 .driver_data = &i801_mux_config_asus_z8_d12,
993 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
994 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
996 .driver_data = &i801_mux_config_asus_z8_d12,
1000 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1001 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1003 .driver_data = &i801_mux_config_asus_z8_d12,
1007 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1008 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1010 .driver_data = &i801_mux_config_asus_z8_d12,
1014 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1015 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1017 .driver_data = &i801_mux_config_asus_z8_d12,
1021 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1022 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1024 .driver_data = &i801_mux_config_asus_z8_d18,
1028 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1029 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1031 .driver_data = &i801_mux_config_asus_z8_d18,
1035 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1036 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1038 .driver_data = &i801_mux_config_asus_z8_d12,
1043 /* Setup multiplexing if needed */
1044 static int i801_add_mux(struct i801_priv *priv)
1046 struct device *dev = &priv->adapter.dev;
1047 const struct i801_mux_config *mux_config;
1048 struct i2c_mux_gpio_platform_data gpio_data;
1051 if (!priv->mux_drvdata)
1053 mux_config = priv->mux_drvdata;
1055 /* Prepare the platform data */
1056 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1057 gpio_data.parent = priv->adapter.nr;
1058 gpio_data.values = mux_config->values;
1059 gpio_data.n_values = mux_config->n_values;
1060 gpio_data.classes = mux_config->classes;
1061 gpio_data.gpio_chip = mux_config->gpio_chip;
1062 gpio_data.gpios = mux_config->gpios;
1063 gpio_data.n_gpios = mux_config->n_gpios;
1064 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1066 /* Register the mux device */
1067 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1068 PLATFORM_DEVID_AUTO, &gpio_data,
1069 sizeof(struct i2c_mux_gpio_platform_data));
1070 if (IS_ERR(priv->mux_pdev)) {
1071 err = PTR_ERR(priv->mux_pdev);
1072 priv->mux_pdev = NULL;
1073 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1080 static void i801_del_mux(struct i801_priv *priv)
1083 platform_device_unregister(priv->mux_pdev);
1086 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1088 const struct dmi_system_id *id;
1089 const struct i801_mux_config *mux_config;
1090 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1093 id = dmi_first_match(mux_dmi_table);
1095 /* Remove branch classes from trunk */
1096 mux_config = id->driver_data;
1097 for (i = 0; i < mux_config->n_values; i++)
1098 class &= ~mux_config->classes[i];
1100 /* Remember for later */
1101 priv->mux_drvdata = mux_config;
1107 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1108 static inline void i801_del_mux(struct i801_priv *priv) { }
1110 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1112 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1116 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1120 struct i801_priv *priv;
1122 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1126 i2c_set_adapdata(&priv->adapter, priv);
1127 priv->adapter.owner = THIS_MODULE;
1128 priv->adapter.class = i801_get_adapter_class(priv);
1129 priv->adapter.algo = &smbus_algorithm;
1131 priv->pci_dev = dev;
1132 switch (dev->device) {
1133 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1134 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1135 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1136 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1137 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1138 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1139 priv->features |= FEATURE_IDF;
1142 priv->features |= FEATURE_I2C_BLOCK_READ;
1143 priv->features |= FEATURE_IRQ;
1145 case PCI_DEVICE_ID_INTEL_82801DB_3:
1146 priv->features |= FEATURE_SMBUS_PEC;
1147 priv->features |= FEATURE_BLOCK_BUFFER;
1149 case PCI_DEVICE_ID_INTEL_82801CA_3:
1150 case PCI_DEVICE_ID_INTEL_82801BA_2:
1151 case PCI_DEVICE_ID_INTEL_82801AB_3:
1152 case PCI_DEVICE_ID_INTEL_82801AA_3:
1156 /* Disable features on user request */
1157 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1158 if (priv->features & disable_features & (1 << i))
1159 dev_notice(&dev->dev, "%s disabled by user\n",
1160 i801_feature_names[i]);
1162 priv->features &= ~disable_features;
1164 err = pci_enable_device(dev);
1166 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1171 /* Determine the address of the SMBus area */
1172 priv->smba = pci_resource_start(dev, SMBBAR);
1174 dev_err(&dev->dev, "SMBus base address uninitialized, "
1180 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
1186 err = pci_request_region(dev, SMBBAR, i801_driver.name);
1188 dev_err(&dev->dev, "Failed to request SMBus region "
1189 "0x%lx-0x%Lx\n", priv->smba,
1190 (unsigned long long)pci_resource_end(dev, SMBBAR));
1194 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1195 priv->original_hstcfg = temp;
1196 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1197 if (!(temp & SMBHSTCFG_HST_EN)) {
1198 dev_info(&dev->dev, "Enabling SMBus device\n");
1199 temp |= SMBHSTCFG_HST_EN;
1201 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1203 if (temp & SMBHSTCFG_SMB_SMI_EN) {
1204 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1205 /* Disable SMBus interrupt feature if SMBus using SMI# */
1206 priv->features &= ~FEATURE_IRQ;
1209 /* Clear special mode bits */
1210 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1211 outb_p(inb_p(SMBAUXCTL(priv)) &
1212 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1214 if (priv->features & FEATURE_IRQ) {
1215 init_waitqueue_head(&priv->waitq);
1217 err = request_irq(dev->irq, i801_isr, IRQF_SHARED,
1218 i801_driver.name, priv);
1220 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1224 dev_info(&dev->dev, "SMBus using PCI Interrupt\n");
1227 /* set up the sysfs linkage to our parent device */
1228 priv->adapter.dev.parent = &dev->dev;
1230 /* Retry up to 3 times on lost arbitration */
1231 priv->adapter.retries = 3;
1233 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1234 "SMBus I801 adapter at %04lx", priv->smba);
1235 err = i2c_add_adapter(&priv->adapter);
1237 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
1241 i801_probe_optional_slaves(priv);
1242 /* We ignore errors - multiplexing is optional */
1245 pci_set_drvdata(dev, priv);
1250 if (priv->features & FEATURE_IRQ)
1251 free_irq(dev->irq, priv);
1253 pci_release_region(dev, SMBBAR);
1259 static void i801_remove(struct pci_dev *dev)
1261 struct i801_priv *priv = pci_get_drvdata(dev);
1264 i2c_del_adapter(&priv->adapter);
1265 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1267 if (priv->features & FEATURE_IRQ)
1268 free_irq(dev->irq, priv);
1269 pci_release_region(dev, SMBBAR);
1273 * do not call pci_disable_device(dev) since it can cause hard hangs on
1274 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1279 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
1281 struct i801_priv *priv = pci_get_drvdata(dev);
1283 pci_save_state(dev);
1284 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1285 pci_set_power_state(dev, pci_choose_state(dev, mesg));
1289 static int i801_resume(struct pci_dev *dev)
1291 pci_set_power_state(dev, PCI_D0);
1292 pci_restore_state(dev);
1293 return pci_enable_device(dev);
1296 #define i801_suspend NULL
1297 #define i801_resume NULL
1300 static struct pci_driver i801_driver = {
1301 .name = "i801_smbus",
1302 .id_table = i801_ids,
1303 .probe = i801_probe,
1304 .remove = i801_remove,
1305 .suspend = i801_suspend,
1306 .resume = i801_resume,
1309 static int __init i2c_i801_init(void)
1311 if (dmi_name_in_vendors("FUJITSU"))
1312 input_apanel_init();
1313 return pci_register_driver(&i801_driver);
1316 static void __exit i2c_i801_exit(void)
1318 pci_unregister_driver(&i801_driver);
1321 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1322 MODULE_DESCRIPTION("I801 SMBus driver");
1323 MODULE_LICENSE("GPL");
1325 module_init(i2c_i801_init);
1326 module_exit(i2c_i801_exit);