2 * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/module.h>
14 #include <linux/i2c.h>
15 #include <linux/time.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/errno.h>
19 #include <linux/err.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
22 #include <linux/slab.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
26 #include <linux/spinlock.h>
29 * HSI2C controller from Samsung supports 2 modes of operation
30 * 1. Auto mode: Where in master automatically controls the whole transaction
31 * 2. Manual mode: Software controls the transaction by issuing commands
32 * START, READ, WRITE, STOP, RESTART in I2C_MANUAL_CMD register.
34 * Operation mode can be selected by setting AUTO_MODE bit in I2C_CONF register
36 * Special bits are available for both modes of operation to set commands
37 * and for checking transfer status
41 #define HSI2C_CTL 0x00
42 #define HSI2C_FIFO_CTL 0x04
43 #define HSI2C_TRAILIG_CTL 0x08
44 #define HSI2C_CLK_CTL 0x0C
45 #define HSI2C_CLK_SLOT 0x10
46 #define HSI2C_INT_ENABLE 0x20
47 #define HSI2C_INT_STATUS 0x24
48 #define HSI2C_ERR_STATUS 0x2C
49 #define HSI2C_FIFO_STATUS 0x30
50 #define HSI2C_TX_DATA 0x34
51 #define HSI2C_RX_DATA 0x38
52 #define HSI2C_CONF 0x40
53 #define HSI2C_AUTO_CONF 0x44
54 #define HSI2C_TIMEOUT 0x48
55 #define HSI2C_MANUAL_CMD 0x4C
56 #define HSI2C_TRANS_STATUS 0x50
57 #define HSI2C_TIMING_HS1 0x54
58 #define HSI2C_TIMING_HS2 0x58
59 #define HSI2C_TIMING_HS3 0x5C
60 #define HSI2C_TIMING_FS1 0x60
61 #define HSI2C_TIMING_FS2 0x64
62 #define HSI2C_TIMING_FS3 0x68
63 #define HSI2C_TIMING_SLA 0x6C
64 #define HSI2C_ADDR 0x70
66 /* I2C_CTL Register bits */
67 #define HSI2C_FUNC_MODE_I2C (1u << 0)
68 #define HSI2C_MASTER (1u << 3)
69 #define HSI2C_RXCHON (1u << 6)
70 #define HSI2C_TXCHON (1u << 7)
71 #define HSI2C_SW_RST (1u << 31)
73 /* I2C_FIFO_CTL Register bits */
74 #define HSI2C_RXFIFO_EN (1u << 0)
75 #define HSI2C_TXFIFO_EN (1u << 1)
76 #define HSI2C_RXFIFO_TRIGGER_LEVEL(x) ((x) << 4)
77 #define HSI2C_TXFIFO_TRIGGER_LEVEL(x) ((x) << 16)
79 /* I2C_TRAILING_CTL Register bits */
80 #define HSI2C_TRAILING_COUNT (0xf)
82 /* I2C_INT_EN Register bits */
83 #define HSI2C_INT_TX_ALMOSTEMPTY_EN (1u << 0)
84 #define HSI2C_INT_RX_ALMOSTFULL_EN (1u << 1)
85 #define HSI2C_INT_TRAILING_EN (1u << 6)
86 #define HSI2C_INT_I2C_EN (1u << 9)
88 /* I2C_INT_STAT Register bits */
89 #define HSI2C_INT_TX_ALMOSTEMPTY (1u << 0)
90 #define HSI2C_INT_RX_ALMOSTFULL (1u << 1)
91 #define HSI2C_INT_TX_UNDERRUN (1u << 2)
92 #define HSI2C_INT_TX_OVERRUN (1u << 3)
93 #define HSI2C_INT_RX_UNDERRUN (1u << 4)
94 #define HSI2C_INT_RX_OVERRUN (1u << 5)
95 #define HSI2C_INT_TRAILING (1u << 6)
96 #define HSI2C_INT_I2C (1u << 9)
98 /* I2C_FIFO_STAT Register bits */
99 #define HSI2C_RX_FIFO_EMPTY (1u << 24)
100 #define HSI2C_RX_FIFO_FULL (1u << 23)
101 #define HSI2C_RX_FIFO_LVL(x) ((x >> 16) & 0x7f)
102 #define HSI2C_TX_FIFO_EMPTY (1u << 8)
103 #define HSI2C_TX_FIFO_FULL (1u << 7)
104 #define HSI2C_TX_FIFO_LVL(x) ((x >> 0) & 0x7f)
106 /* I2C_CONF Register bits */
107 #define HSI2C_AUTO_MODE (1u << 31)
108 #define HSI2C_10BIT_ADDR_MODE (1u << 30)
109 #define HSI2C_HS_MODE (1u << 29)
111 /* I2C_AUTO_CONF Register bits */
112 #define HSI2C_READ_WRITE (1u << 16)
113 #define HSI2C_STOP_AFTER_TRANS (1u << 17)
114 #define HSI2C_MASTER_RUN (1u << 31)
116 /* I2C_TIMEOUT Register bits */
117 #define HSI2C_TIMEOUT_EN (1u << 31)
118 #define HSI2C_TIMEOUT_MASK 0xff
120 /* I2C_TRANS_STATUS register bits */
121 #define HSI2C_MASTER_BUSY (1u << 17)
122 #define HSI2C_SLAVE_BUSY (1u << 16)
123 #define HSI2C_TIMEOUT_AUTO (1u << 4)
124 #define HSI2C_NO_DEV (1u << 3)
125 #define HSI2C_NO_DEV_ACK (1u << 2)
126 #define HSI2C_TRANS_ABORT (1u << 1)
127 #define HSI2C_TRANS_DONE (1u << 0)
129 /* I2C_ADDR register bits */
130 #define HSI2C_SLV_ADDR_SLV(x) ((x & 0x3ff) << 0)
131 #define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10)
132 #define HSI2C_MASTER_ID(x) ((x & 0xff) << 24)
133 #define MASTER_ID(x) ((x & 0x7) + 0x08)
136 * Controller operating frequency, timing values for operation
137 * are calculated against this frequency
139 #define HSI2C_HS_TX_CLOCK 1000000
140 #define HSI2C_FS_TX_CLOCK 100000
141 #define HSI2C_HIGH_SPD 1
142 #define HSI2C_FAST_SPD 0
144 #define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(1000))
147 struct i2c_adapter adap;
148 unsigned int suspended:1;
151 struct completion msg_complete;
152 unsigned int msg_ptr;
161 spinlock_t lock; /* IRQ synchronization */
164 * Since the TRANS_DONE bit is cleared on read, and we may read it
165 * either during an IRQ or after a transaction, keep track of its
170 /* Controller operating frequency */
171 unsigned int fs_clock;
172 unsigned int hs_clock;
175 * HSI2C Controller can operate in
176 * 1. High speed upto 3.4Mbps
177 * 2. Fast speed upto 1Mbps
181 /* Version of HS-I2C Hardware */
182 struct exynos_hsi2c_variant *variant;
186 * struct exynos_hsi2c_variant - platform specific HSI2C driver data
187 * @fifo_depth: the fifo depth supported by the HSI2C module
189 * Specifies platform specific configuration of HSI2C module.
190 * Note: A structure for driver specific platform data is used for future
191 * expansion of its usage.
193 struct exynos_hsi2c_variant {
194 unsigned int fifo_depth;
197 static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = {
201 static const struct exynos_hsi2c_variant exynos5260_hsi2c_data = {
205 static const struct of_device_id exynos5_i2c_match[] = {
207 .compatible = "samsung,exynos5-hsi2c",
208 .data = &exynos5250_hsi2c_data
210 .compatible = "samsung,exynos5250-hsi2c",
211 .data = &exynos5250_hsi2c_data
213 .compatible = "samsung,exynos5260-hsi2c",
214 .data = &exynos5260_hsi2c_data
217 MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
219 static inline struct exynos_hsi2c_variant *exynos5_i2c_get_variant
220 (struct platform_device *pdev)
222 const struct of_device_id *match;
224 match = of_match_node(exynos5_i2c_match, pdev->dev.of_node);
225 return (struct exynos_hsi2c_variant *)match->data;
228 static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c)
230 writel(readl(i2c->regs + HSI2C_INT_STATUS),
231 i2c->regs + HSI2C_INT_STATUS);
235 * exynos5_i2c_set_timing: updates the registers with appropriate
236 * timing values calculated
238 * Returns 0 on success, -EINVAL if the cycle length cannot
241 static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, int mode)
247 unsigned int t_start_su, t_start_hd;
248 unsigned int t_stop_su;
249 unsigned int t_data_su, t_data_hd;
250 unsigned int t_scl_l, t_scl_h;
251 unsigned int t_sr_release;
252 unsigned int t_ftl_cycle;
253 unsigned int clkin = clk_get_rate(i2c->clk);
254 unsigned int div, utemp0 = 0, utemp1 = 0, clk_cycle;
255 unsigned int op_clk = (mode == HSI2C_HIGH_SPD) ?
256 i2c->hs_clock : i2c->fs_clock;
260 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
261 * utemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2)
262 * utemp1 = (TSCLK_L + TSCLK_H + 2)
264 t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7;
265 utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle;
267 /* CLK_DIV max is 256 */
268 for (div = 0; div < 256; div++) {
269 utemp1 = utemp0 / (div + 1);
272 * SCL_L and SCL_H each has max value of 255
273 * Hence, For the clk_cycle to the have right value
274 * utemp1 has to be less then 512 and more than 4.
276 if ((utemp1 < 512) && (utemp1 > 4)) {
277 clk_cycle = utemp1 - 2;
279 } else if (div == 255) {
280 dev_warn(i2c->dev, "Failed to calculate divisor");
285 t_scl_l = clk_cycle / 2;
286 t_scl_h = clk_cycle / 2;
287 t_start_su = t_scl_l;
288 t_start_hd = t_scl_l;
290 t_data_su = t_scl_l / 2;
291 t_data_hd = t_scl_l / 2;
292 t_sr_release = clk_cycle;
294 i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
295 i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
296 i2c_timing_s3 = div << 16 | t_sr_release << 0;
297 i2c_timing_sla = t_data_hd << 0;
299 dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n",
300 t_start_su, t_start_hd, t_stop_su);
301 dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n",
302 t_data_su, t_scl_l, t_scl_h);
303 dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n",
305 dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd);
307 if (mode == HSI2C_HIGH_SPD) {
308 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1);
309 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2);
310 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);
312 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1);
313 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2);
314 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);
316 writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA);
321 static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c)
324 * Configure the Fast speed timing values
325 * Even the High Speed mode initially starts with Fast mode
327 if (exynos5_i2c_set_timing(i2c, HSI2C_FAST_SPD)) {
328 dev_err(i2c->dev, "HSI2C FS Clock set up failed\n");
332 /* configure the High speed timing values */
333 if (i2c->speed_mode == HSI2C_HIGH_SPD) {
334 if (exynos5_i2c_set_timing(i2c, HSI2C_HIGH_SPD)) {
335 dev_err(i2c->dev, "HSI2C HS Clock set up failed\n");
344 * exynos5_i2c_init: configures the controller for I2C functionality
345 * Programs I2C controller for Master mode operation
347 static void exynos5_i2c_init(struct exynos5_i2c *i2c)
349 u32 i2c_conf = readl(i2c->regs + HSI2C_CONF);
350 u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT);
352 /* Clear to disable Timeout */
353 i2c_timeout &= ~HSI2C_TIMEOUT_EN;
354 writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT);
356 writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
357 i2c->regs + HSI2C_CTL);
358 writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL);
360 if (i2c->speed_mode == HSI2C_HIGH_SPD) {
361 writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)),
362 i2c->regs + HSI2C_ADDR);
363 i2c_conf |= HSI2C_HS_MODE;
366 writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF);
369 static void exynos5_i2c_reset(struct exynos5_i2c *i2c)
373 /* Set and clear the bit for reset */
374 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
375 i2c_ctl |= HSI2C_SW_RST;
376 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
378 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
379 i2c_ctl &= ~HSI2C_SW_RST;
380 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
382 /* We don't expect calculations to fail during the run */
383 exynos5_hsi2c_clock_setup(i2c);
384 /* Initialize the configure registers */
385 exynos5_i2c_init(i2c);
389 * exynos5_i2c_irq: top level IRQ servicing routine
391 * INT_STATUS registers gives the interrupt details. Further,
392 * FIFO_STATUS or TRANS_STATUS registers are to be check for detailed
395 static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)
397 struct exynos5_i2c *i2c = dev_id;
398 u32 fifo_level, int_status, fifo_status, trans_status;
402 i2c->state = -EINVAL;
404 spin_lock(&i2c->lock);
406 int_status = readl(i2c->regs + HSI2C_INT_STATUS);
407 writel(int_status, i2c->regs + HSI2C_INT_STATUS);
409 /* handle interrupt related to the transfer status */
410 if (int_status & HSI2C_INT_I2C) {
411 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
412 if (trans_status & HSI2C_NO_DEV_ACK) {
413 dev_dbg(i2c->dev, "No ACK from device\n");
416 } else if (trans_status & HSI2C_NO_DEV) {
417 dev_dbg(i2c->dev, "No device\n");
420 } else if (trans_status & HSI2C_TRANS_ABORT) {
421 dev_dbg(i2c->dev, "Deal with arbitration lose\n");
422 i2c->state = -EAGAIN;
424 } else if (trans_status & HSI2C_TIMEOUT_AUTO) {
425 dev_dbg(i2c->dev, "Accessing device timed out\n");
426 i2c->state = -EAGAIN;
428 } else if (trans_status & HSI2C_TRANS_DONE) {
434 if ((i2c->msg->flags & I2C_M_RD) && (int_status &
435 (HSI2C_INT_TRAILING | HSI2C_INT_RX_ALMOSTFULL))) {
436 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
437 fifo_level = HSI2C_RX_FIFO_LVL(fifo_status);
438 len = min(fifo_level, i2c->msg->len - i2c->msg_ptr);
441 byte = (unsigned char)
442 readl(i2c->regs + HSI2C_RX_DATA);
443 i2c->msg->buf[i2c->msg_ptr++] = byte;
447 } else if (int_status & HSI2C_INT_TX_ALMOSTEMPTY) {
448 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
449 fifo_level = HSI2C_TX_FIFO_LVL(fifo_status);
451 len = i2c->variant->fifo_depth - fifo_level;
452 if (len > (i2c->msg->len - i2c->msg_ptr))
453 len = i2c->msg->len - i2c->msg_ptr;
456 byte = i2c->msg->buf[i2c->msg_ptr++];
457 writel(byte, i2c->regs + HSI2C_TX_DATA);
464 if ((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) ||
466 writel(0, i2c->regs + HSI2C_INT_ENABLE);
467 exynos5_i2c_clr_pend_irq(i2c);
468 complete(&i2c->msg_complete);
471 spin_unlock(&i2c->lock);
477 * exynos5_i2c_wait_bus_idle
479 * Wait for the bus to go idle, indicated by the MASTER_BUSY bit being
482 * Returns -EBUSY if the bus cannot be bought to idle
484 static int exynos5_i2c_wait_bus_idle(struct exynos5_i2c *i2c)
486 unsigned long stop_time;
489 /* wait for 100 milli seconds for the bus to be idle */
490 stop_time = jiffies + msecs_to_jiffies(100) + 1;
492 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
493 if (!(trans_status & HSI2C_MASTER_BUSY))
496 usleep_range(50, 200);
497 } while (time_before(jiffies, stop_time));
503 * exynos5_i2c_message_start: Configures the bus and starts the xfer
504 * i2c: struct exynos5_i2c pointer for the current bus
505 * stop: Enables stop after transfer if set. Set for last transfer of
506 * in the list of messages.
508 * Configures the bus for read/write function
509 * Sets chip address to talk to, message length to be sent.
510 * Enables appropriate interrupts and sends start xfer command.
512 static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop)
515 u32 int_en = HSI2C_INT_I2C_EN;
516 u32 i2c_auto_conf = 0;
519 unsigned short trig_lvl;
521 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
522 i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON);
523 fifo_ctl = HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN;
525 if (i2c->msg->flags & I2C_M_RD) {
526 i2c_ctl |= HSI2C_RXCHON;
528 i2c_auto_conf |= HSI2C_READ_WRITE;
530 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
531 (i2c->variant->fifo_depth * 3 / 4) : i2c->msg->len;
532 fifo_ctl |= HSI2C_RXFIFO_TRIGGER_LEVEL(trig_lvl);
534 int_en |= (HSI2C_INT_RX_ALMOSTFULL_EN |
535 HSI2C_INT_TRAILING_EN);
537 i2c_ctl |= HSI2C_TXCHON;
539 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
540 (i2c->variant->fifo_depth * 1 / 4) : i2c->msg->len;
541 fifo_ctl |= HSI2C_TXFIFO_TRIGGER_LEVEL(trig_lvl);
543 int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN;
546 writel(HSI2C_SLV_ADDR_MAS(i2c->msg->addr), i2c->regs + HSI2C_ADDR);
548 writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL);
549 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
552 * Enable interrupts before starting the transfer so that we don't
553 * miss any INT_I2C interrupts.
555 spin_lock_irqsave(&i2c->lock, flags);
556 writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
559 i2c_auto_conf |= HSI2C_STOP_AFTER_TRANS;
560 i2c_auto_conf |= i2c->msg->len;
561 i2c_auto_conf |= HSI2C_MASTER_RUN;
562 writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF);
563 spin_unlock_irqrestore(&i2c->lock, flags);
566 static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c,
567 struct i2c_msg *msgs, int stop)
569 unsigned long timeout;
576 reinit_completion(&i2c->msg_complete);
578 exynos5_i2c_message_start(i2c, stop);
580 timeout = wait_for_completion_timeout(&i2c->msg_complete,
581 EXYNOS5_I2C_TIMEOUT);
588 * If this is the last message to be transfered (stop == 1)
589 * Then check if the bus can be brought back to idle.
591 if (ret == 0 && stop)
592 ret = exynos5_i2c_wait_bus_idle(i2c);
595 exynos5_i2c_reset(i2c);
596 if (ret == -ETIMEDOUT)
597 dev_warn(i2c->dev, "%s timeout\n",
598 (msgs->flags & I2C_M_RD) ? "rx" : "tx");
601 /* Return the state as in interrupt routine */
605 static int exynos5_i2c_xfer(struct i2c_adapter *adap,
606 struct i2c_msg *msgs, int num)
608 struct exynos5_i2c *i2c = adap->algo_data;
609 int i = 0, ret = 0, stop = 0;
611 if (i2c->suspended) {
612 dev_err(i2c->dev, "HS-I2C is not initialized.\n");
616 clk_prepare_enable(i2c->clk);
618 for (i = 0; i < num; i++, msgs++) {
619 stop = (i == num - 1);
621 ret = exynos5_i2c_xfer_msg(i2c, msgs, stop);
630 /* Only one message, cannot access the device */
636 dev_warn(i2c->dev, "xfer message failed\n");
640 clk_disable_unprepare(i2c->clk);
644 static u32 exynos5_i2c_func(struct i2c_adapter *adap)
646 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
649 static const struct i2c_algorithm exynos5_i2c_algorithm = {
650 .master_xfer = exynos5_i2c_xfer,
651 .functionality = exynos5_i2c_func,
654 static int exynos5_i2c_probe(struct platform_device *pdev)
656 struct device_node *np = pdev->dev.of_node;
657 struct exynos5_i2c *i2c;
658 struct resource *mem;
659 unsigned int op_clock;
662 i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL);
666 if (of_property_read_u32(np, "clock-frequency", &op_clock)) {
667 i2c->speed_mode = HSI2C_FAST_SPD;
668 i2c->fs_clock = HSI2C_FS_TX_CLOCK;
670 if (op_clock >= HSI2C_HS_TX_CLOCK) {
671 i2c->speed_mode = HSI2C_HIGH_SPD;
672 i2c->fs_clock = HSI2C_FS_TX_CLOCK;
673 i2c->hs_clock = op_clock;
675 i2c->speed_mode = HSI2C_FAST_SPD;
676 i2c->fs_clock = op_clock;
680 strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name));
681 i2c->adap.owner = THIS_MODULE;
682 i2c->adap.algo = &exynos5_i2c_algorithm;
683 i2c->adap.retries = 3;
685 i2c->dev = &pdev->dev;
686 i2c->clk = devm_clk_get(&pdev->dev, "hsi2c");
687 if (IS_ERR(i2c->clk)) {
688 dev_err(&pdev->dev, "cannot get clock\n");
692 clk_prepare_enable(i2c->clk);
694 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
695 i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
696 if (IS_ERR(i2c->regs)) {
697 ret = PTR_ERR(i2c->regs);
701 i2c->adap.dev.of_node = np;
702 i2c->adap.algo_data = i2c;
703 i2c->adap.dev.parent = &pdev->dev;
705 /* Clear pending interrupts from u-boot or misc causes */
706 exynos5_i2c_clr_pend_irq(i2c);
708 spin_lock_init(&i2c->lock);
709 init_completion(&i2c->msg_complete);
711 i2c->irq = ret = platform_get_irq(pdev, 0);
713 dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n");
718 ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq,
719 IRQF_NO_SUSPEND | IRQF_ONESHOT,
720 dev_name(&pdev->dev), i2c);
723 dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq);
727 ret = exynos5_hsi2c_clock_setup(i2c);
731 i2c->variant = exynos5_i2c_get_variant(pdev);
733 exynos5_i2c_reset(i2c);
735 ret = i2c_add_adapter(&i2c->adap);
737 dev_err(&pdev->dev, "failed to add bus to i2c core\n");
741 platform_set_drvdata(pdev, i2c);
744 clk_disable_unprepare(i2c->clk);
748 static int exynos5_i2c_remove(struct platform_device *pdev)
750 struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
752 i2c_del_adapter(&i2c->adap);
757 #ifdef CONFIG_PM_SLEEP
758 static int exynos5_i2c_suspend_noirq(struct device *dev)
760 struct platform_device *pdev = to_platform_device(dev);
761 struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
768 static int exynos5_i2c_resume_noirq(struct device *dev)
770 struct platform_device *pdev = to_platform_device(dev);
771 struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
774 clk_prepare_enable(i2c->clk);
776 ret = exynos5_hsi2c_clock_setup(i2c);
778 clk_disable_unprepare(i2c->clk);
782 exynos5_i2c_init(i2c);
783 clk_disable_unprepare(i2c->clk);
790 static const struct dev_pm_ops exynos5_i2c_dev_pm_ops = {
791 #ifdef CONFIG_PM_SLEEP
792 .suspend_noirq = exynos5_i2c_suspend_noirq,
793 .resume_noirq = exynos5_i2c_resume_noirq,
794 .freeze_noirq = exynos5_i2c_suspend_noirq,
795 .thaw_noirq = exynos5_i2c_resume_noirq,
796 .poweroff_noirq = exynos5_i2c_suspend_noirq,
797 .restore_noirq = exynos5_i2c_resume_noirq,
801 static struct platform_driver exynos5_i2c_driver = {
802 .probe = exynos5_i2c_probe,
803 .remove = exynos5_i2c_remove,
805 .owner = THIS_MODULE,
806 .name = "exynos5-hsi2c",
807 .pm = &exynos5_i2c_dev_pm_ops,
808 .of_match_table = exynos5_i2c_match,
812 module_platform_driver(exynos5_i2c_driver);
814 MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver");
815 MODULE_AUTHOR("Naveen Krishna Chatradhi, <ch.naveen@samsung.com>");
816 MODULE_AUTHOR("Taekgyun Ko, <taeggyun.ko@samsung.com>");
817 MODULE_LICENSE("GPL v2");