2 * Copyright(C) 2015 Linaro Limited. All rights reserved.
3 * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #ifndef _CORESIGHT_TMC_H
19 #define _CORESIGHT_TMC_H
29 #define TMC_MODE 0x028
30 #define TMC_LBUFLEVEL 0x02c
31 #define TMC_CBUFLEVEL 0x030
32 #define TMC_BUFWM 0x034
33 #define TMC_RRPHI 0x038
34 #define TMC_RWPHI 0x03c
35 #define TMC_AXICTL 0x110
36 #define TMC_DBALO 0x118
37 #define TMC_DBAHI 0x11c
38 #define TMC_FFSR 0x300
39 #define TMC_FFCR 0x304
40 #define TMC_PSCR 0x308
41 #define TMC_ITMISCOP0 0xee0
42 #define TMC_ITTRFLIN 0xee8
43 #define TMC_ITATBDATA0 0xeec
44 #define TMC_ITATBCTR2 0xef0
45 #define TMC_ITATBCTR1 0xef4
46 #define TMC_ITATBCTR0 0xef8
48 /* register description */
50 #define TMC_CTL_CAPT_EN BIT(0)
52 #define TMC_STS_TMCREADY_BIT 2
53 #define TMC_STS_TRIGGERED BIT(1)
54 /* TMC_AXICTL - 0x110 */
55 #define TMC_AXICTL_PROT_CTL_B0 BIT(0)
56 #define TMC_AXICTL_PROT_CTL_B1 BIT(1)
57 #define TMC_AXICTL_SCT_GAT_MODE BIT(7)
58 #define TMC_AXICTL_WR_BURST_16 0xF00
59 /* TMC_FFCR - 0x304 */
60 #define TMC_FFCR_FLUSHMAN_BIT 6
61 #define TMC_FFCR_EN_FMT BIT(0)
62 #define TMC_FFCR_EN_TI BIT(1)
63 #define TMC_FFCR_FON_FLIN BIT(4)
64 #define TMC_FFCR_FON_TRIG_EVT BIT(5)
65 #define TMC_FFCR_TRIGON_TRIGIN BIT(8)
66 #define TMC_FFCR_STOP_ON_FLUSH BIT(12)
69 enum tmc_config_type {
76 TMC_MODE_CIRCULAR_BUFFER,
77 TMC_MODE_SOFTWARE_FIFO,
78 TMC_MODE_HARDWARE_FIFO,
81 enum tmc_mem_intf_width {
82 TMC_MEM_INTF_WIDTH_32BITS = 0x2,
83 TMC_MEM_INTF_WIDTH_64BITS = 0x3,
84 TMC_MEM_INTF_WIDTH_128BITS = 0x4,
85 TMC_MEM_INTF_WIDTH_256BITS = 0x5,
89 * struct tmc_drvdata - specifics associated to an TMC component
90 * @base: memory mapped base address for this component.
91 * @dev: the device entity associated to this component.
92 * @csdev: component vitals needed by the framework.
93 * @miscdev: specifics to handle "/dev/xyz.tmc" entry.
94 * @spinlock: only one at a time pls.
95 * @read_count: manages preparation of buffer for reading.
96 * @buf: area of memory where trace data get sent.
97 * @paddr: DMA start location in RAM.
98 * @vaddr: virtual representation of @paddr.
100 * @enable: this TMC is being used.
101 * @config_type: TMC variant, must be of type @tmc_config_type.
102 * @trigger_cntr: amount of words to store after a trigger.
107 struct coresight_device *csdev;
108 struct miscdevice miscdev;
117 enum tmc_config_type config_type;