1 /* Copyright (c) 2012, The Linux Foundation. All rights reserved.
3 * Description: CoreSight Trace Memory Controller driver
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 and
7 * only version 2 as published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/types.h>
18 #include <linux/device.h>
20 #include <linux/err.h>
22 #include <linux/miscdevice.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/spinlock.h>
27 #include <linux/pm_runtime.h>
29 #include <linux/coresight.h>
30 #include <linux/amba/bus.h>
32 #include "coresight-priv.h"
33 #include "coresight-tmc.h"
35 static void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata)
37 /* Ensure formatter, unformatter and hardware fifo are empty */
38 if (coresight_timeout(drvdata->base,
39 TMC_STS, TMC_STS_TMCREADY_BIT, 1)) {
41 "timeout observed when probing at offset %#x\n",
46 static void tmc_flush_and_stop(struct tmc_drvdata *drvdata)
50 ffcr = readl_relaxed(drvdata->base + TMC_FFCR);
51 ffcr |= TMC_FFCR_STOP_ON_FLUSH;
52 writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
53 ffcr |= TMC_FFCR_FLUSHMAN;
54 writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
55 /* Ensure flush completes */
56 if (coresight_timeout(drvdata->base,
57 TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) {
59 "timeout observed when probing at offset %#x\n",
63 tmc_wait_for_tmcready(drvdata);
66 static void tmc_enable_hw(struct tmc_drvdata *drvdata)
68 writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL);
71 static void tmc_disable_hw(struct tmc_drvdata *drvdata)
73 writel_relaxed(0x0, drvdata->base + TMC_CTL);
76 static void tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
78 /* Zero out the memory to help with debug */
79 memset(drvdata->buf, 0, drvdata->size);
81 CS_UNLOCK(drvdata->base);
83 /* Wait for TMCSReady bit to be set */
84 tmc_wait_for_tmcready(drvdata);
86 writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
87 writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
88 TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
89 TMC_FFCR_TRIGON_TRIGIN,
90 drvdata->base + TMC_FFCR);
92 writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
93 tmc_enable_hw(drvdata);
95 CS_LOCK(drvdata->base);
98 static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
102 /* Zero out the memory to help with debug */
103 memset(drvdata->vaddr, 0, drvdata->size);
105 CS_UNLOCK(drvdata->base);
107 /* Wait for TMCSReady bit to be set */
108 tmc_wait_for_tmcready(drvdata);
110 writel_relaxed(drvdata->size / 4, drvdata->base + TMC_RSZ);
111 writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
113 axictl = readl_relaxed(drvdata->base + TMC_AXICTL);
114 axictl |= TMC_AXICTL_WR_BURST_16;
115 writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
116 axictl &= ~TMC_AXICTL_SCT_GAT_MODE;
117 writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
119 ~(TMC_AXICTL_PROT_CTL_B0 | TMC_AXICTL_PROT_CTL_B1)) |
120 TMC_AXICTL_PROT_CTL_B1;
121 writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
123 writel_relaxed(drvdata->paddr, drvdata->base + TMC_DBALO);
124 writel_relaxed(0x0, drvdata->base + TMC_DBAHI);
125 writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
126 TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
127 TMC_FFCR_TRIGON_TRIGIN,
128 drvdata->base + TMC_FFCR);
129 writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
130 tmc_enable_hw(drvdata);
132 CS_LOCK(drvdata->base);
135 static void tmc_etf_enable_hw(struct tmc_drvdata *drvdata)
137 CS_UNLOCK(drvdata->base);
139 /* Wait for TMCSReady bit to be set */
140 tmc_wait_for_tmcready(drvdata);
142 writel_relaxed(TMC_MODE_HARDWARE_FIFO, drvdata->base + TMC_MODE);
143 writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI,
144 drvdata->base + TMC_FFCR);
145 writel_relaxed(0x0, drvdata->base + TMC_BUFWM);
146 tmc_enable_hw(drvdata);
148 CS_LOCK(drvdata->base);
151 static int tmc_enable(struct tmc_drvdata *drvdata, enum tmc_mode mode)
155 spin_lock_irqsave(&drvdata->spinlock, flags);
156 if (drvdata->reading) {
157 spin_unlock_irqrestore(&drvdata->spinlock, flags);
161 if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
162 tmc_etb_enable_hw(drvdata);
163 } else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
164 tmc_etr_enable_hw(drvdata);
166 if (mode == TMC_MODE_CIRCULAR_BUFFER)
167 tmc_etb_enable_hw(drvdata);
169 tmc_etf_enable_hw(drvdata);
171 drvdata->enable = true;
172 spin_unlock_irqrestore(&drvdata->spinlock, flags);
174 dev_info(drvdata->dev, "TMC enabled\n");
178 static int tmc_enable_sink(struct coresight_device *csdev, u32 mode)
180 struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
182 return tmc_enable(drvdata, TMC_MODE_CIRCULAR_BUFFER);
185 static int tmc_enable_link(struct coresight_device *csdev, int inport,
188 struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
190 return tmc_enable(drvdata, TMC_MODE_HARDWARE_FIFO);
193 static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata)
195 enum tmc_mem_intf_width memwidth;
201 memwidth = BMVAL(readl_relaxed(drvdata->base + CORESIGHT_DEVID), 8, 10);
202 if (memwidth == TMC_MEM_INTF_WIDTH_32BITS)
204 else if (memwidth == TMC_MEM_INTF_WIDTH_64BITS)
206 else if (memwidth == TMC_MEM_INTF_WIDTH_128BITS)
213 for (i = 0; i < memwords; i++) {
214 read_data = readl_relaxed(drvdata->base + TMC_RRD);
215 if (read_data == 0xFFFFFFFF)
217 memcpy(bufp, &read_data, 4);
223 static void tmc_etb_disable_hw(struct tmc_drvdata *drvdata)
225 CS_UNLOCK(drvdata->base);
227 tmc_flush_and_stop(drvdata);
228 tmc_etb_dump_hw(drvdata);
229 tmc_disable_hw(drvdata);
231 CS_LOCK(drvdata->base);
234 static void tmc_etr_dump_hw(struct tmc_drvdata *drvdata)
238 rwp = readl_relaxed(drvdata->base + TMC_RWP);
239 val = readl_relaxed(drvdata->base + TMC_STS);
241 /* How much memory do we still have */
243 drvdata->buf = drvdata->vaddr + rwp - drvdata->paddr;
245 drvdata->buf = drvdata->vaddr;
248 static void tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
250 CS_UNLOCK(drvdata->base);
252 tmc_flush_and_stop(drvdata);
253 tmc_etr_dump_hw(drvdata);
254 tmc_disable_hw(drvdata);
256 CS_LOCK(drvdata->base);
259 static void tmc_etf_disable_hw(struct tmc_drvdata *drvdata)
261 CS_UNLOCK(drvdata->base);
263 tmc_flush_and_stop(drvdata);
264 tmc_disable_hw(drvdata);
266 CS_LOCK(drvdata->base);
269 static void tmc_disable(struct tmc_drvdata *drvdata, enum tmc_mode mode)
273 spin_lock_irqsave(&drvdata->spinlock, flags);
274 if (drvdata->reading)
277 if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
278 tmc_etb_disable_hw(drvdata);
279 } else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
280 tmc_etr_disable_hw(drvdata);
282 if (mode == TMC_MODE_CIRCULAR_BUFFER)
283 tmc_etb_disable_hw(drvdata);
285 tmc_etf_disable_hw(drvdata);
288 drvdata->enable = false;
289 spin_unlock_irqrestore(&drvdata->spinlock, flags);
291 dev_info(drvdata->dev, "TMC disabled\n");
294 static void tmc_disable_sink(struct coresight_device *csdev)
296 struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
298 tmc_disable(drvdata, TMC_MODE_CIRCULAR_BUFFER);
301 static void tmc_disable_link(struct coresight_device *csdev, int inport,
304 struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
306 tmc_disable(drvdata, TMC_MODE_HARDWARE_FIFO);
309 static const struct coresight_ops_sink tmc_sink_ops = {
310 .enable = tmc_enable_sink,
311 .disable = tmc_disable_sink,
314 static const struct coresight_ops_link tmc_link_ops = {
315 .enable = tmc_enable_link,
316 .disable = tmc_disable_link,
319 static const struct coresight_ops tmc_etb_cs_ops = {
320 .sink_ops = &tmc_sink_ops,
323 static const struct coresight_ops tmc_etr_cs_ops = {
324 .sink_ops = &tmc_sink_ops,
327 static const struct coresight_ops tmc_etf_cs_ops = {
328 .sink_ops = &tmc_sink_ops,
329 .link_ops = &tmc_link_ops,
332 static int tmc_read_prepare(struct tmc_drvdata *drvdata)
338 spin_lock_irqsave(&drvdata->spinlock, flags);
339 if (!drvdata->enable)
342 switch (drvdata->config_type) {
343 case TMC_CONFIG_TYPE_ETB:
344 tmc_etb_disable_hw(drvdata);
346 case TMC_CONFIG_TYPE_ETF:
347 /* There is no point in reading a TMC in HW FIFO mode */
348 mode = readl_relaxed(drvdata->base + TMC_MODE);
349 if (mode != TMC_MODE_CIRCULAR_BUFFER) {
354 tmc_etb_disable_hw(drvdata);
356 case TMC_CONFIG_TYPE_ETR:
357 tmc_etr_disable_hw(drvdata);
365 drvdata->reading = true;
366 dev_info(drvdata->dev, "TMC read start\n");
368 spin_unlock_irqrestore(&drvdata->spinlock, flags);
372 static void tmc_read_unprepare(struct tmc_drvdata *drvdata)
377 spin_lock_irqsave(&drvdata->spinlock, flags);
378 if (!drvdata->enable)
381 switch (drvdata->config_type) {
382 case TMC_CONFIG_TYPE_ETB:
383 tmc_etb_enable_hw(drvdata);
385 case TMC_CONFIG_TYPE_ETF:
386 /* Make sure we don't re-enable a TMC in HW FIFO mode */
387 mode = readl_relaxed(drvdata->base + TMC_MODE);
388 if (mode != TMC_MODE_CIRCULAR_BUFFER)
391 tmc_etb_enable_hw(drvdata);
393 case TMC_CONFIG_TYPE_ETR:
394 tmc_etr_disable_hw(drvdata);
401 drvdata->reading = false;
402 dev_info(drvdata->dev, "TMC read end\n");
404 spin_unlock_irqrestore(&drvdata->spinlock, flags);
407 static int tmc_open(struct inode *inode, struct file *file)
409 struct tmc_drvdata *drvdata = container_of(file->private_data,
410 struct tmc_drvdata, miscdev);
413 if (drvdata->read_count++)
416 ret = tmc_read_prepare(drvdata);
420 nonseekable_open(inode, file);
422 dev_dbg(drvdata->dev, "%s: successfully opened\n", __func__);
426 static ssize_t tmc_read(struct file *file, char __user *data, size_t len,
429 struct tmc_drvdata *drvdata = container_of(file->private_data,
430 struct tmc_drvdata, miscdev);
431 char *bufp = drvdata->buf + *ppos;
433 if (*ppos + len > drvdata->size)
434 len = drvdata->size - *ppos;
436 if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
437 if (bufp == (char *)(drvdata->vaddr + drvdata->size))
438 bufp = drvdata->vaddr;
439 else if (bufp > (char *)(drvdata->vaddr + drvdata->size))
440 bufp -= drvdata->size;
441 if ((bufp + len) > (char *)(drvdata->vaddr + drvdata->size))
442 len = (char *)(drvdata->vaddr + drvdata->size) - bufp;
445 if (copy_to_user(data, bufp, len)) {
446 dev_dbg(drvdata->dev, "%s: copy_to_user failed\n", __func__);
452 dev_dbg(drvdata->dev, "%s: %zu bytes copied, %d bytes left\n",
453 __func__, len, (int)(drvdata->size - *ppos));
457 static int tmc_release(struct inode *inode, struct file *file)
459 struct tmc_drvdata *drvdata = container_of(file->private_data,
460 struct tmc_drvdata, miscdev);
462 if (--drvdata->read_count) {
463 if (drvdata->read_count < 0) {
464 dev_err(drvdata->dev, "mismatched close\n");
465 drvdata->read_count = 0;
470 tmc_read_unprepare(drvdata);
472 dev_dbg(drvdata->dev, "%s: released\n", __func__);
476 static const struct file_operations tmc_fops = {
477 .owner = THIS_MODULE,
480 .release = tmc_release,
484 #define coresight_tmc_simple_func(name, offset) \
485 coresight_simple_func(struct tmc_drvdata, name, offset)
487 coresight_tmc_simple_func(rsz, TMC_RSZ);
488 coresight_tmc_simple_func(sts, TMC_STS);
489 coresight_tmc_simple_func(rrp, TMC_RRP);
490 coresight_tmc_simple_func(rwp, TMC_RWP);
491 coresight_tmc_simple_func(trg, TMC_TRG);
492 coresight_tmc_simple_func(ctl, TMC_CTL);
493 coresight_tmc_simple_func(ffsr, TMC_FFSR);
494 coresight_tmc_simple_func(ffcr, TMC_FFCR);
495 coresight_tmc_simple_func(mode, TMC_MODE);
496 coresight_tmc_simple_func(pscr, TMC_PSCR);
497 coresight_tmc_simple_func(devid, CORESIGHT_DEVID);
499 static struct attribute *coresight_tmc_mgmt_attrs[] = {
510 &dev_attr_devid.attr,
514 ssize_t trigger_cntr_show(struct device *dev,
515 struct device_attribute *attr, char *buf)
517 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
518 unsigned long val = drvdata->trigger_cntr;
520 return sprintf(buf, "%#lx\n", val);
523 static ssize_t trigger_cntr_store(struct device *dev,
524 struct device_attribute *attr,
525 const char *buf, size_t size)
529 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
531 ret = kstrtoul(buf, 16, &val);
535 drvdata->trigger_cntr = val;
538 static DEVICE_ATTR_RW(trigger_cntr);
540 static struct attribute *coresight_tmc_attrs[] = {
541 &dev_attr_trigger_cntr.attr,
545 static const struct attribute_group coresight_tmc_group = {
546 .attrs = coresight_tmc_attrs,
549 static const struct attribute_group coresight_tmc_mgmt_group = {
550 .attrs = coresight_tmc_mgmt_attrs,
554 const struct attribute_group *coresight_tmc_groups[] = {
555 &coresight_tmc_group,
556 &coresight_tmc_mgmt_group,
560 static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
565 struct device *dev = &adev->dev;
566 struct coresight_platform_data *pdata = NULL;
567 struct tmc_drvdata *drvdata;
568 struct resource *res = &adev->res;
569 struct coresight_desc *desc;
570 struct device_node *np = adev->dev.of_node;
573 pdata = of_get_coresight_platform_data(dev, np);
575 return PTR_ERR(pdata);
576 adev->dev.platform_data = pdata;
579 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
583 drvdata->dev = &adev->dev;
584 dev_set_drvdata(dev, drvdata);
586 /* Validity for the resource is already checked by the AMBA core */
587 base = devm_ioremap_resource(dev, res);
589 return PTR_ERR(base);
591 drvdata->base = base;
593 spin_lock_init(&drvdata->spinlock);
595 devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
596 drvdata->config_type = BMVAL(devid, 6, 7);
598 if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
600 ret = of_property_read_u32(np,
604 drvdata->size = SZ_1M;
606 drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4;
609 pm_runtime_put(&adev->dev);
611 if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
612 drvdata->vaddr = dma_alloc_coherent(dev, drvdata->size,
613 &drvdata->paddr, GFP_KERNEL);
617 memset(drvdata->vaddr, 0, drvdata->size);
618 drvdata->buf = drvdata->vaddr;
620 drvdata->buf = devm_kzalloc(dev, drvdata->size, GFP_KERNEL);
625 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
628 goto err_devm_kzalloc;
633 desc->subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
634 desc->groups = coresight_tmc_groups;
636 if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
637 desc->type = CORESIGHT_DEV_TYPE_SINK;
638 desc->ops = &tmc_etb_cs_ops;
639 } else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
640 desc->type = CORESIGHT_DEV_TYPE_SINK;
641 desc->ops = &tmc_etr_cs_ops;
643 desc->type = CORESIGHT_DEV_TYPE_LINKSINK;
644 desc->subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
645 desc->ops = &tmc_etf_cs_ops;
648 drvdata->csdev = coresight_register(desc);
649 if (IS_ERR(drvdata->csdev)) {
650 ret = PTR_ERR(drvdata->csdev);
651 goto err_devm_kzalloc;
654 drvdata->miscdev.name = pdata->name;
655 drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
656 drvdata->miscdev.fops = &tmc_fops;
657 ret = misc_register(&drvdata->miscdev);
659 goto err_misc_register;
664 coresight_unregister(drvdata->csdev);
666 if (drvdata->config_type == TMC_CONFIG_TYPE_ETR)
667 dma_free_coherent(dev, drvdata->size,
668 drvdata->vaddr, drvdata->paddr);
672 static struct amba_id tmc_ids[] = {
680 static struct amba_driver tmc_driver = {
682 .name = "coresight-tmc",
683 .owner = THIS_MODULE,
684 .suppress_bind_attrs = true,
689 builtin_amba_driver(tmc_driver);