drivers/hwtracing/coresight/coresight-tmc.c

   1 /* Copyright (c) 2012, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/init.h>
  16 #include <linux/types.h>
  17 #include <linux/device.h>
  18 #include <linux/io.h>
  19 #include <linux/err.h>
  20 #include <linux/fs.h>
  21 #include <linux/miscdevice.h>
  22 #include <linux/uaccess.h>
  23 #include <linux/slab.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/of.h>
  28 #include <linux/coresight.h>
  29 #include <linux/amba/bus.h>
  30
  31 #include "coresight-priv.h"
  32
  33 #define TMC_RSZ                 0x004
  34 #define TMC_STS                 0x00c
  35 #define TMC_RRD                 0x010
  36 #define TMC_RRP                 0x014
  37 #define TMC_RWP                 0x018
  38 #define TMC_TRG                 0x01c
  39 #define TMC_CTL                 0x020
  40 #define TMC_RWD                 0x024
  41 #define TMC_MODE                0x028
  42 #define TMC_LBUFLEVEL           0x02c
  43 #define TMC_CBUFLEVEL           0x030
  44 #define TMC_BUFWM               0x034
  45 #define TMC_RRPHI               0x038
  46 #define TMC_RWPHI               0x03c
  47 #define TMC_AXICTL              0x110
  48 #define TMC_DBALO               0x118
  49 #define TMC_DBAHI               0x11c
  50 #define TMC_FFSR                0x300
  51 #define TMC_FFCR                0x304
  52 #define TMC_PSCR                0x308
  53 #define TMC_ITMISCOP0           0xee0
  54 #define TMC_ITTRFLIN            0xee8
  55 #define TMC_ITATBDATA0          0xeec
  56 #define TMC_ITATBCTR2           0xef0
  57 #define TMC_ITATBCTR1           0xef4
  58 #define TMC_ITATBCTR0           0xef8
  59
  60 /* register description */
  61 /* TMC_CTL - 0x020 */
  62 #define TMC_CTL_CAPT_EN         BIT(0)
  63 /* TMC_STS - 0x00C */
  64 #define TMC_STS_TRIGGERED       BIT(1)
  65 /* TMC_AXICTL - 0x110 */
  66 #define TMC_AXICTL_PROT_CTL_B0  BIT(0)
  67 #define TMC_AXICTL_PROT_CTL_B1  BIT(1)
  68 #define TMC_AXICTL_SCT_GAT_MODE BIT(7)
  69 #define TMC_AXICTL_WR_BURST_LEN 0xF00
  70 /* TMC_FFCR - 0x304 */
  71 #define TMC_FFCR_EN_FMT         BIT(0)
  72 #define TMC_FFCR_EN_TI          BIT(1)
  73 #define TMC_FFCR_FON_FLIN       BIT(4)
  74 #define TMC_FFCR_FON_TRIG_EVT   BIT(5)
  75 #define TMC_FFCR_FLUSHMAN       BIT(6)
  76 #define TMC_FFCR_TRIGON_TRIGIN  BIT(8)
  77 #define TMC_FFCR_STOP_ON_FLUSH  BIT(12)
  78
  79 #define TMC_STS_TRIGGERED_BIT   2
  80 #define TMC_FFCR_FLUSHMAN_BIT   6
  81
  82 enum tmc_config_type {
  83         TMC_CONFIG_TYPE_ETB,
  84         TMC_CONFIG_TYPE_ETR,
  85         TMC_CONFIG_TYPE_ETF,
  86 };
  87
  88 enum tmc_mode {
  89         TMC_MODE_CIRCULAR_BUFFER,
  90         TMC_MODE_SOFTWARE_FIFO,
  91         TMC_MODE_HARDWARE_FIFO,
  92 };
  93
  94 enum tmc_mem_intf_width {
  95         TMC_MEM_INTF_WIDTH_32BITS       = 0x2,
  96         TMC_MEM_INTF_WIDTH_64BITS       = 0x3,
  97         TMC_MEM_INTF_WIDTH_128BITS      = 0x4,
  98         TMC_MEM_INTF_WIDTH_256BITS      = 0x5,
  99 };
 100
 101 /**
 102  * struct tmc_drvdata - specifics associated to an TMC component
 103  * @base:       memory mapped base address for this component.
 104  * @dev:        the device entity associated to this component.
 105  * @csdev:      component vitals needed by the framework.
 106  * @miscdev:    specifics to handle "/dev/xyz.tmc" entry.
 107  * @spinlock:   only one at a time pls.
 108  * @read_count: manages preparation of buffer for reading.
 109  * @buf:        area of memory where trace data get sent.
 110  * @paddr:      DMA start location in RAM.
 111  * @vaddr:      virtual representation of @paddr.
 112  * @size:       @buf size.
 113  * @enable:     this TMC is being used.
 114  * @config_type: TMC variant, must be of type @tmc_config_type.
 115  * @trigger_cntr: amount of words to store after a trigger.
 116  */
 117 struct tmc_drvdata {
 118         void __iomem            *base;
 119         struct device           *dev;
 120         struct coresight_device *csdev;
 121         struct miscdevice       miscdev;
 122         spinlock_t              spinlock;
 123         int                     read_count;
 124         bool                    reading;
 125         char                    *buf;
 126         dma_addr_t              paddr;
 127         void                    *vaddr;
 128         u32                     size;
 129         bool                    enable;
 130         enum tmc_config_type    config_type;
 131         u32                     trigger_cntr;
 132 };
 133
 134 static void tmc_wait_for_ready(struct tmc_drvdata *drvdata)
 135 {
 136         /* Ensure formatter, unformatter and hardware fifo are empty */
 137         if (coresight_timeout(drvdata->base,
 138                               TMC_STS, TMC_STS_TRIGGERED_BIT, 1)) {
 139                 dev_err(drvdata->dev,
 140                         "timeout observed when probing at offset %#x\n",
 141                         TMC_STS);
 142         }
 143 }
 144
 145 static void tmc_flush_and_stop(struct tmc_drvdata *drvdata)
 146 {
 147         u32 ffcr;
 148
 149         ffcr = readl_relaxed(drvdata->base + TMC_FFCR);
 150         ffcr |= TMC_FFCR_STOP_ON_FLUSH;
 151         writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
 152         ffcr |= TMC_FFCR_FLUSHMAN;
 153         writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
 154         /* Ensure flush completes */
 155         if (coresight_timeout(drvdata->base,
 156                               TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) {
 157                 dev_err(drvdata->dev,
 158                         "timeout observed when probing at offset %#x\n",
 159                         TMC_FFCR);
 160         }
 161
 162         tmc_wait_for_ready(drvdata);
 163 }
 164
 165 static void tmc_enable_hw(struct tmc_drvdata *drvdata)
 166 {
 167         writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL);
 168 }
 169
 170 static void tmc_disable_hw(struct tmc_drvdata *drvdata)
 171 {
 172         writel_relaxed(0x0, drvdata->base + TMC_CTL);
 173 }
 174
 175 static void tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
 176 {
 177         /* Zero out the memory to help with debug */
 178         memset(drvdata->buf, 0, drvdata->size);
 179
 180         CS_UNLOCK(drvdata->base);
 181
 182         writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
 183         writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
 184                        TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
 185                        TMC_FFCR_TRIGON_TRIGIN,
 186                        drvdata->base + TMC_FFCR);
 187
 188         writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
 189         tmc_enable_hw(drvdata);
 190
 191         CS_LOCK(drvdata->base);
 192 }
 193
 194 static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
 195 {
 196         u32 axictl;
 197
 198         /* Zero out the memory to help with debug */
 199         memset(drvdata->vaddr, 0, drvdata->size);
 200
 201         CS_UNLOCK(drvdata->base);
 202
 203         writel_relaxed(drvdata->size / 4, drvdata->base + TMC_RSZ);
 204         writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
 205
 206         axictl = readl_relaxed(drvdata->base + TMC_AXICTL);
 207         axictl |= TMC_AXICTL_WR_BURST_LEN;
 208         writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
 209         axictl &= ~TMC_AXICTL_SCT_GAT_MODE;
 210         writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
 211         axictl = (axictl &
 212                   ~(TMC_AXICTL_PROT_CTL_B0 | TMC_AXICTL_PROT_CTL_B1)) |
 213                   TMC_AXICTL_PROT_CTL_B1;
 214         writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
 215
 216         writel_relaxed(drvdata->paddr, drvdata->base + TMC_DBALO);
 217         writel_relaxed(0x0, drvdata->base + TMC_DBAHI);
 218         writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
 219                        TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
 220                        TMC_FFCR_TRIGON_TRIGIN,
 221                        drvdata->base + TMC_FFCR);
 222         writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
 223         tmc_enable_hw(drvdata);
 224
 225         CS_LOCK(drvdata->base);
 226 }
 227
 228 static void tmc_etf_enable_hw(struct tmc_drvdata *drvdata)
 229 {
 230         CS_UNLOCK(drvdata->base);
 231
 232         writel_relaxed(TMC_MODE_HARDWARE_FIFO, drvdata->base + TMC_MODE);
 233         writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI,
 234                        drvdata->base + TMC_FFCR);
 235         writel_relaxed(0x0, drvdata->base + TMC_BUFWM);
 236         tmc_enable_hw(drvdata);
 237
 238         CS_LOCK(drvdata->base);
 239 }
 240
 241 static int tmc_enable(struct tmc_drvdata *drvdata, enum tmc_mode mode)
 242 {
 243         unsigned long flags;
 244
 245         spin_lock_irqsave(&drvdata->spinlock, flags);
 246         if (drvdata->reading) {
 247                 spin_unlock_irqrestore(&drvdata->spinlock, flags);
 248                 return -EBUSY;
 249         }
 250
 251         if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
 252                 tmc_etb_enable_hw(drvdata);
 253         } else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
 254                 tmc_etr_enable_hw(drvdata);
 255         } else {
 256                 if (mode == TMC_MODE_CIRCULAR_BUFFER)
 257                         tmc_etb_enable_hw(drvdata);
 258                 else
 259                         tmc_etf_enable_hw(drvdata);
 260         }
 261         drvdata->enable = true;
 262         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 263
 264         dev_info(drvdata->dev, "TMC enabled\n");
 265         return 0;
 266 }
 267
 268 static int tmc_enable_sink(struct coresight_device *csdev)
 269 {
 270         struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 271
 272         return tmc_enable(drvdata, TMC_MODE_CIRCULAR_BUFFER);
 273 }
 274
 275 static int tmc_enable_link(struct coresight_device *csdev, int inport,
 276                            int outport)
 277 {
 278         struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 279
 280         return tmc_enable(drvdata, TMC_MODE_HARDWARE_FIFO);
 281 }
 282
 283 static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata)
 284 {
 285         enum tmc_mem_intf_width memwidth;
 286         u8 memwords;
 287         char *bufp;
 288         u32 read_data;
 289         int i;
 290
 291         memwidth = BMVAL(readl_relaxed(drvdata->base + CORESIGHT_DEVID), 8, 10);
 292         if (memwidth == TMC_MEM_INTF_WIDTH_32BITS)
 293                 memwords = 1;
 294         else if (memwidth == TMC_MEM_INTF_WIDTH_64BITS)
 295                 memwords = 2;
 296         else if (memwidth == TMC_MEM_INTF_WIDTH_128BITS)
 297                 memwords = 4;
 298         else
 299                 memwords = 8;
 300
 301         bufp = drvdata->buf;
 302         while (1) {
 303                 for (i = 0; i < memwords; i++) {
 304                         read_data = readl_relaxed(drvdata->base + TMC_RRD);
 305                         if (read_data == 0xFFFFFFFF)
 306                                 return;
 307                         memcpy(bufp, &read_data, 4);
 308                         bufp += 4;
 309                 }
 310         }
 311 }
 312
 313 static void tmc_etb_disable_hw(struct tmc_drvdata *drvdata)
 314 {
 315         CS_UNLOCK(drvdata->base);
 316
 317         tmc_flush_and_stop(drvdata);
 318         tmc_etb_dump_hw(drvdata);
 319         tmc_disable_hw(drvdata);
 320
 321         CS_LOCK(drvdata->base);
 322 }
 323
 324 static void tmc_etr_dump_hw(struct tmc_drvdata *drvdata)
 325 {
 326         u32 rwp, val;
 327
 328         rwp = readl_relaxed(drvdata->base + TMC_RWP);
 329         val = readl_relaxed(drvdata->base + TMC_STS);
 330
 331         /* How much memory do we still have */
 332         if (val & BIT(0))
 333                 drvdata->buf = drvdata->vaddr + rwp - drvdata->paddr;
 334         else
 335                 drvdata->buf = drvdata->vaddr;
 336 }
 337
 338 static void tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
 339 {
 340         CS_UNLOCK(drvdata->base);
 341
 342         tmc_flush_and_stop(drvdata);
 343         tmc_etr_dump_hw(drvdata);
 344         tmc_disable_hw(drvdata);
 345
 346         CS_LOCK(drvdata->base);
 347 }
 348
 349 static void tmc_etf_disable_hw(struct tmc_drvdata *drvdata)
 350 {
 351         CS_UNLOCK(drvdata->base);
 352
 353         tmc_flush_and_stop(drvdata);
 354         tmc_disable_hw(drvdata);
 355
 356         CS_LOCK(drvdata->base);
 357 }
 358
 359 static void tmc_disable(struct tmc_drvdata *drvdata, enum tmc_mode mode)
 360 {
 361         unsigned long flags;
 362
 363         spin_lock_irqsave(&drvdata->spinlock, flags);
 364         if (drvdata->reading)
 365                 goto out;
 366
 367         if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
 368                 tmc_etb_disable_hw(drvdata);
 369         } else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
 370                 tmc_etr_disable_hw(drvdata);
 371         } else {
 372                 if (mode == TMC_MODE_CIRCULAR_BUFFER)
 373                         tmc_etb_disable_hw(drvdata);
 374                 else
 375                         tmc_etf_disable_hw(drvdata);
 376         }
 377 out:
 378         drvdata->enable = false;
 379         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 380
 381         dev_info(drvdata->dev, "TMC disabled\n");
 382 }
 383
 384 static void tmc_disable_sink(struct coresight_device *csdev)
 385 {
 386         struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 387
 388         tmc_disable(drvdata, TMC_MODE_CIRCULAR_BUFFER);
 389 }
 390
 391 static void tmc_disable_link(struct coresight_device *csdev, int inport,
 392                              int outport)
 393 {
 394         struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 395
 396         tmc_disable(drvdata, TMC_MODE_HARDWARE_FIFO);
 397 }
 398
 399 static const struct coresight_ops_sink tmc_sink_ops = {
 400         .enable         = tmc_enable_sink,
 401         .disable        = tmc_disable_sink,
 402 };
 403
 404 static const struct coresight_ops_link tmc_link_ops = {
 405         .enable         = tmc_enable_link,
 406         .disable        = tmc_disable_link,
 407 };
 408
 409 static const struct coresight_ops tmc_etb_cs_ops = {
 410         .sink_ops       = &tmc_sink_ops,
 411 };
 412
 413 static const struct coresight_ops tmc_etr_cs_ops = {
 414         .sink_ops       = &tmc_sink_ops,
 415 };
 416
 417 static const struct coresight_ops tmc_etf_cs_ops = {
 418         .sink_ops       = &tmc_sink_ops,
 419         .link_ops       = &tmc_link_ops,
 420 };
 421
 422 static int tmc_read_prepare(struct tmc_drvdata *drvdata)
 423 {
 424         int ret;
 425         unsigned long flags;
 426         enum tmc_mode mode;
 427
 428         spin_lock_irqsave(&drvdata->spinlock, flags);
 429         if (!drvdata->enable)
 430                 goto out;
 431
 432         if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
 433                 tmc_etb_disable_hw(drvdata);
 434         } else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
 435                 tmc_etr_disable_hw(drvdata);
 436         } else {
 437                 mode = readl_relaxed(drvdata->base + TMC_MODE);
 438                 if (mode == TMC_MODE_CIRCULAR_BUFFER) {
 439                         tmc_etb_disable_hw(drvdata);
 440                 } else {
 441                         ret = -ENODEV;
 442                         goto err;
 443                 }
 444         }
 445 out:
 446         drvdata->reading = true;
 447         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 448
 449         dev_info(drvdata->dev, "TMC read start\n");
 450         return 0;
 451 err:
 452         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 453         return ret;
 454 }
 455
 456 static void tmc_read_unprepare(struct tmc_drvdata *drvdata)
 457 {
 458         unsigned long flags;
 459         enum tmc_mode mode;
 460
 461         spin_lock_irqsave(&drvdata->spinlock, flags);
 462         if (!drvdata->enable)
 463                 goto out;
 464
 465         if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
 466                 tmc_etb_enable_hw(drvdata);
 467         } else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
 468                 tmc_etr_enable_hw(drvdata);
 469         } else {
 470                 mode = readl_relaxed(drvdata->base + TMC_MODE);
 471                 if (mode == TMC_MODE_CIRCULAR_BUFFER)
 472                         tmc_etb_enable_hw(drvdata);
 473         }
 474 out:
 475         drvdata->reading = false;
 476         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 477
 478         dev_info(drvdata->dev, "TMC read end\n");
 479 }
 480
 481 static int tmc_open(struct inode *inode, struct file *file)
 482 {
 483         struct tmc_drvdata *drvdata = container_of(file->private_data,
 484                                                    struct tmc_drvdata, miscdev);
 485         int ret = 0;
 486
 487         if (drvdata->read_count++)
 488                 goto out;
 489
 490         ret = tmc_read_prepare(drvdata);
 491         if (ret)
 492                 return ret;
 493 out:
 494         nonseekable_open(inode, file);
 495
 496         dev_dbg(drvdata->dev, "%s: successfully opened\n", __func__);
 497         return 0;
 498 }
 499
 500 static ssize_t tmc_read(struct file *file, char __user *data, size_t len,
 501                         loff_t *ppos)
 502 {
 503         struct tmc_drvdata *drvdata = container_of(file->private_data,
 504                                                    struct tmc_drvdata, miscdev);
 505         char *bufp = drvdata->buf + *ppos;
 506
 507         if (*ppos + len > drvdata->size)
 508                 len = drvdata->size - *ppos;
 509
 510         if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
 511                 if (bufp == (char *)(drvdata->vaddr + drvdata->size))
 512                         bufp = drvdata->vaddr;
 513                 else if (bufp > (char *)(drvdata->vaddr + drvdata->size))
 514                         bufp -= drvdata->size;
 515                 if ((bufp + len) > (char *)(drvdata->vaddr + drvdata->size))
 516                         len = (char *)(drvdata->vaddr + drvdata->size) - bufp;
 517         }
 518
 519         if (copy_to_user(data, bufp, len)) {
 520                 dev_dbg(drvdata->dev, "%s: copy_to_user failed\n", __func__);
 521                 return -EFAULT;
 522         }
 523
 524         *ppos += len;
 525
 526         dev_dbg(drvdata->dev, "%s: %zu bytes copied, %d bytes left\n",
 527                 __func__, len, (int)(drvdata->size - *ppos));
 528         return len;
 529 }
 530
 531 static int tmc_release(struct inode *inode, struct file *file)
 532 {
 533         struct tmc_drvdata *drvdata = container_of(file->private_data,
 534                                                    struct tmc_drvdata, miscdev);
 535
 536         if (--drvdata->read_count) {
 537                 if (drvdata->read_count < 0) {
 538                         dev_err(drvdata->dev, "mismatched close\n");
 539                         drvdata->read_count = 0;
 540                 }
 541                 goto out;
 542         }
 543
 544         tmc_read_unprepare(drvdata);
 545 out:
 546         dev_dbg(drvdata->dev, "%s: released\n", __func__);
 547         return 0;
 548 }
 549
 550 static const struct file_operations tmc_fops = {
 551         .owner          = THIS_MODULE,
 552         .open           = tmc_open,
 553         .read           = tmc_read,
 554         .release        = tmc_release,
 555         .llseek         = no_llseek,
 556 };
 557
 558 static ssize_t status_show(struct device *dev,
 559                            struct device_attribute *attr, char *buf)
 560 {
 561         unsigned long flags;
 562         u32 tmc_rsz, tmc_sts, tmc_rrp, tmc_rwp, tmc_trg;
 563         u32 tmc_ctl, tmc_ffsr, tmc_ffcr, tmc_mode, tmc_pscr;
 564         u32 devid;
 565         struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
 566
 567         pm_runtime_get_sync(drvdata->dev);
 568         spin_lock_irqsave(&drvdata->spinlock, flags);
 569         CS_UNLOCK(drvdata->base);
 570
 571         tmc_rsz = readl_relaxed(drvdata->base + TMC_RSZ);
 572         tmc_sts = readl_relaxed(drvdata->base + TMC_STS);
 573         tmc_rrp = readl_relaxed(drvdata->base + TMC_RRP);
 574         tmc_rwp = readl_relaxed(drvdata->base + TMC_RWP);
 575         tmc_trg = readl_relaxed(drvdata->base + TMC_TRG);
 576         tmc_ctl = readl_relaxed(drvdata->base + TMC_CTL);
 577         tmc_ffsr = readl_relaxed(drvdata->base + TMC_FFSR);
 578         tmc_ffcr = readl_relaxed(drvdata->base + TMC_FFCR);
 579         tmc_mode = readl_relaxed(drvdata->base + TMC_MODE);
 580         tmc_pscr = readl_relaxed(drvdata->base + TMC_PSCR);
 581         devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
 582
 583         CS_LOCK(drvdata->base);
 584         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 585         pm_runtime_put(drvdata->dev);
 586
 587         return sprintf(buf,
 588                        "Depth:\t\t0x%x\n"
 589                        "Status:\t\t0x%x\n"
 590                        "RAM read ptr:\t0x%x\n"
 591                        "RAM wrt ptr:\t0x%x\n"
 592                        "Trigger cnt:\t0x%x\n"
 593                        "Control:\t0x%x\n"
 594                        "Flush status:\t0x%x\n"
 595                        "Flush ctrl:\t0x%x\n"
 596                        "Mode:\t\t0x%x\n"
 597                        "PSRC:\t\t0x%x\n"
 598                        "DEVID:\t\t0x%x\n",
 599                         tmc_rsz, tmc_sts, tmc_rrp, tmc_rwp, tmc_trg,
 600                         tmc_ctl, tmc_ffsr, tmc_ffcr, tmc_mode, tmc_pscr, devid);
 601
 602         return -EINVAL;
 603 }
 604 static DEVICE_ATTR_RO(status);
 605
 606 static ssize_t trigger_cntr_show(struct device *dev,
 607                             struct device_attribute *attr, char *buf)
 608 {
 609         struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
 610         unsigned long val = drvdata->trigger_cntr;
 611
 612         return sprintf(buf, "%#lx\n", val);
 613 }
 614
 615 static ssize_t trigger_cntr_store(struct device *dev,
 616                              struct device_attribute *attr,
 617                              const char *buf, size_t size)
 618 {
 619         int ret;
 620         unsigned long val;
 621         struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
 622
 623         ret = kstrtoul(buf, 16, &val);
 624         if (ret)
 625                 return ret;
 626
 627         drvdata->trigger_cntr = val;
 628         return size;
 629 }
 630 static DEVICE_ATTR_RW(trigger_cntr);
 631
 632 static struct attribute *coresight_etb_attrs[] = {
 633         &dev_attr_trigger_cntr.attr,
 634         &dev_attr_status.attr,
 635         NULL,
 636 };
 637 ATTRIBUTE_GROUPS(coresight_etb);
 638
 639 static struct attribute *coresight_etr_attrs[] = {
 640         &dev_attr_trigger_cntr.attr,
 641         &dev_attr_status.attr,
 642         NULL,
 643 };
 644 ATTRIBUTE_GROUPS(coresight_etr);
 645
 646 static struct attribute *coresight_etf_attrs[] = {
 647         &dev_attr_trigger_cntr.attr,
 648         &dev_attr_status.attr,
 649         NULL,
 650 };
 651 ATTRIBUTE_GROUPS(coresight_etf);
 652
 653 static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
 654 {
 655         int ret = 0;
 656         u32 devid;
 657         void __iomem *base;
 658         struct device *dev = &adev->dev;
 659         struct coresight_platform_data *pdata = NULL;
 660         struct tmc_drvdata *drvdata;
 661         struct resource *res = &adev->res;
 662         struct coresight_desc *desc;
 663         struct device_node *np = adev->dev.of_node;
 664
 665         if (np) {
 666                 pdata = of_get_coresight_platform_data(dev, np);
 667                 if (IS_ERR(pdata))
 668                         return PTR_ERR(pdata);
 669                 adev->dev.platform_data = pdata;
 670         }
 671
 672         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
 673         if (!drvdata)
 674                 return -ENOMEM;
 675
 676         drvdata->dev = &adev->dev;
 677         dev_set_drvdata(dev, drvdata);
 678
 679         /* Validity for the resource is already checked by the AMBA core */
 680         base = devm_ioremap_resource(dev, res);
 681         if (IS_ERR(base))
 682                 return PTR_ERR(base);
 683
 684         drvdata->base = base;
 685
 686         spin_lock_init(&drvdata->spinlock);
 687
 688         devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
 689         drvdata->config_type = BMVAL(devid, 6, 7);
 690
 691         if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
 692                 if (np)
 693                         ret = of_property_read_u32(np,
 694                                                    "arm,buffer-size",
 695                                                    &drvdata->size);
 696                 if (ret)
 697                         drvdata->size = SZ_1M;
 698         } else {
 699                 drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4;
 700         }
 701
 702         pm_runtime_put(&adev->dev);
 703
 704         if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
 705                 drvdata->vaddr = dma_alloc_coherent(dev, drvdata->size,
 706                                                 &drvdata->paddr, GFP_KERNEL);
 707                 if (!drvdata->vaddr)
 708                         return -ENOMEM;
 709
 710                 memset(drvdata->vaddr, 0, drvdata->size);
 711                 drvdata->buf = drvdata->vaddr;
 712         } else {
 713                 drvdata->buf = devm_kzalloc(dev, drvdata->size, GFP_KERNEL);
 714                 if (!drvdata->buf)
 715                         return -ENOMEM;
 716         }
 717
 718         desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
 719         if (!desc) {
 720                 ret = -ENOMEM;
 721                 goto err_devm_kzalloc;
 722         }
 723
 724         desc->pdata = pdata;
 725         desc->dev = dev;
 726         desc->subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
 727
 728         if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
 729                 desc->type = CORESIGHT_DEV_TYPE_SINK;
 730                 desc->ops = &tmc_etb_cs_ops;
 731                 desc->groups = coresight_etb_groups;
 732         } else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
 733                 desc->type = CORESIGHT_DEV_TYPE_SINK;
 734                 desc->ops = &tmc_etr_cs_ops;
 735                 desc->groups = coresight_etr_groups;
 736         } else {
 737                 desc->type = CORESIGHT_DEV_TYPE_LINKSINK;
 738                 desc->subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
 739                 desc->ops = &tmc_etf_cs_ops;
 740                 desc->groups = coresight_etf_groups;
 741         }
 742
 743         drvdata->csdev = coresight_register(desc);
 744         if (IS_ERR(drvdata->csdev)) {
 745                 ret = PTR_ERR(drvdata->csdev);
 746                 goto err_devm_kzalloc;
 747         }
 748
 749         drvdata->miscdev.name = pdata->name;
 750         drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
 751         drvdata->miscdev.fops = &tmc_fops;
 752         ret = misc_register(&drvdata->miscdev);
 753         if (ret)
 754                 goto err_misc_register;
 755
 756         dev_info(dev, "TMC initialized\n");
 757         return 0;
 758
 759 err_misc_register:
 760         coresight_unregister(drvdata->csdev);
 761 err_devm_kzalloc:
 762         if (drvdata->config_type == TMC_CONFIG_TYPE_ETR)
 763                 dma_free_coherent(dev, drvdata->size,
 764                                 drvdata->vaddr, drvdata->paddr);
 765         return ret;
 766 }
 767
 768 static struct amba_id tmc_ids[] = {
 769         {
 770                 .id     = 0x0003b961,
 771                 .mask   = 0x0003ffff,
 772         },
 773         { 0, 0},
 774 };
 775
 776 static struct amba_driver tmc_driver = {
 777         .drv = {
 778                 .name   = "coresight-tmc",
 779                 .owner  = THIS_MODULE,
 780                 .suppress_bind_attrs = true,
 781         },
 782         .probe          = tmc_probe,
 783         .id_table       = tmc_ids,
 784 };
 785
 786 module_amba_driver(tmc_driver);
 787
 788 MODULE_LICENSE("GPL v2");
 789 MODULE_DESCRIPTION("CoreSight Trace Memory Controller driver");