1 /* Copyright (c) 2012, The Linux Foundation. All rights reserved.
3 * Description: CoreSight Trace Memory Controller driver
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 and
7 * only version 2 as published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/types.h>
18 #include <linux/device.h>
20 #include <linux/err.h>
22 #include <linux/miscdevice.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/spinlock.h>
27 #include <linux/pm_runtime.h>
29 #include <linux/coresight.h>
30 #include <linux/amba/bus.h>
32 #include "coresight-priv.h"
42 #define TMC_MODE 0x028
43 #define TMC_LBUFLEVEL 0x02c
44 #define TMC_CBUFLEVEL 0x030
45 #define TMC_BUFWM 0x034
46 #define TMC_RRPHI 0x038
47 #define TMC_RWPHI 0x03c
48 #define TMC_AXICTL 0x110
49 #define TMC_DBALO 0x118
50 #define TMC_DBAHI 0x11c
51 #define TMC_FFSR 0x300
52 #define TMC_FFCR 0x304
53 #define TMC_PSCR 0x308
54 #define TMC_ITMISCOP0 0xee0
55 #define TMC_ITTRFLIN 0xee8
56 #define TMC_ITATBDATA0 0xeec
57 #define TMC_ITATBCTR2 0xef0
58 #define TMC_ITATBCTR1 0xef4
59 #define TMC_ITATBCTR0 0xef8
61 /* register description */
63 #define TMC_CTL_CAPT_EN BIT(0)
65 #define TMC_STS_TRIGGERED BIT(1)
66 /* TMC_AXICTL - 0x110 */
67 #define TMC_AXICTL_PROT_CTL_B0 BIT(0)
68 #define TMC_AXICTL_PROT_CTL_B1 BIT(1)
69 #define TMC_AXICTL_SCT_GAT_MODE BIT(7)
70 #define TMC_AXICTL_WR_BURST_LEN 0xF00
71 /* TMC_FFCR - 0x304 */
72 #define TMC_FFCR_EN_FMT BIT(0)
73 #define TMC_FFCR_EN_TI BIT(1)
74 #define TMC_FFCR_FON_FLIN BIT(4)
75 #define TMC_FFCR_FON_TRIG_EVT BIT(5)
76 #define TMC_FFCR_FLUSHMAN BIT(6)
77 #define TMC_FFCR_TRIGON_TRIGIN BIT(8)
78 #define TMC_FFCR_STOP_ON_FLUSH BIT(12)
80 #define TMC_STS_TRIGGERED_BIT 2
81 #define TMC_FFCR_FLUSHMAN_BIT 6
83 enum tmc_config_type {
90 TMC_MODE_CIRCULAR_BUFFER,
91 TMC_MODE_SOFTWARE_FIFO,
92 TMC_MODE_HARDWARE_FIFO,
95 enum tmc_mem_intf_width {
96 TMC_MEM_INTF_WIDTH_32BITS = 0x2,
97 TMC_MEM_INTF_WIDTH_64BITS = 0x3,
98 TMC_MEM_INTF_WIDTH_128BITS = 0x4,
99 TMC_MEM_INTF_WIDTH_256BITS = 0x5,
103 * struct tmc_drvdata - specifics associated to an TMC component
104 * @base: memory mapped base address for this component.
105 * @dev: the device entity associated to this component.
106 * @csdev: component vitals needed by the framework.
107 * @miscdev: specifics to handle "/dev/xyz.tmc" entry.
108 * @spinlock: only one at a time pls.
109 * @read_count: manages preparation of buffer for reading.
110 * @buf: area of memory where trace data get sent.
111 * @paddr: DMA start location in RAM.
112 * @vaddr: virtual representation of @paddr.
114 * @enable: this TMC is being used.
115 * @config_type: TMC variant, must be of type @tmc_config_type.
116 * @trigger_cntr: amount of words to store after a trigger.
121 struct coresight_device *csdev;
122 struct miscdevice miscdev;
131 enum tmc_config_type config_type;
135 static void tmc_wait_for_ready(struct tmc_drvdata *drvdata)
137 /* Ensure formatter, unformatter and hardware fifo are empty */
138 if (coresight_timeout(drvdata->base,
139 TMC_STS, TMC_STS_TRIGGERED_BIT, 1)) {
140 dev_err(drvdata->dev,
141 "timeout observed when probing at offset %#x\n",
146 static void tmc_flush_and_stop(struct tmc_drvdata *drvdata)
150 ffcr = readl_relaxed(drvdata->base + TMC_FFCR);
151 ffcr |= TMC_FFCR_STOP_ON_FLUSH;
152 writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
153 ffcr |= TMC_FFCR_FLUSHMAN;
154 writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
155 /* Ensure flush completes */
156 if (coresight_timeout(drvdata->base,
157 TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) {
158 dev_err(drvdata->dev,
159 "timeout observed when probing at offset %#x\n",
163 tmc_wait_for_ready(drvdata);
166 static void tmc_enable_hw(struct tmc_drvdata *drvdata)
168 writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL);
171 static void tmc_disable_hw(struct tmc_drvdata *drvdata)
173 writel_relaxed(0x0, drvdata->base + TMC_CTL);
176 static void tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
178 /* Zero out the memory to help with debug */
179 memset(drvdata->buf, 0, drvdata->size);
181 CS_UNLOCK(drvdata->base);
183 writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
184 writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
185 TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
186 TMC_FFCR_TRIGON_TRIGIN,
187 drvdata->base + TMC_FFCR);
189 writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
190 tmc_enable_hw(drvdata);
192 CS_LOCK(drvdata->base);
195 static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
199 /* Zero out the memory to help with debug */
200 memset(drvdata->vaddr, 0, drvdata->size);
202 CS_UNLOCK(drvdata->base);
204 writel_relaxed(drvdata->size / 4, drvdata->base + TMC_RSZ);
205 writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
207 axictl = readl_relaxed(drvdata->base + TMC_AXICTL);
208 axictl |= TMC_AXICTL_WR_BURST_LEN;
209 writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
210 axictl &= ~TMC_AXICTL_SCT_GAT_MODE;
211 writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
213 ~(TMC_AXICTL_PROT_CTL_B0 | TMC_AXICTL_PROT_CTL_B1)) |
214 TMC_AXICTL_PROT_CTL_B1;
215 writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
217 writel_relaxed(drvdata->paddr, drvdata->base + TMC_DBALO);
218 writel_relaxed(0x0, drvdata->base + TMC_DBAHI);
219 writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
220 TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
221 TMC_FFCR_TRIGON_TRIGIN,
222 drvdata->base + TMC_FFCR);
223 writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
224 tmc_enable_hw(drvdata);
226 CS_LOCK(drvdata->base);
229 static void tmc_etf_enable_hw(struct tmc_drvdata *drvdata)
231 CS_UNLOCK(drvdata->base);
233 writel_relaxed(TMC_MODE_HARDWARE_FIFO, drvdata->base + TMC_MODE);
234 writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI,
235 drvdata->base + TMC_FFCR);
236 writel_relaxed(0x0, drvdata->base + TMC_BUFWM);
237 tmc_enable_hw(drvdata);
239 CS_LOCK(drvdata->base);
242 static int tmc_enable(struct tmc_drvdata *drvdata, enum tmc_mode mode)
246 spin_lock_irqsave(&drvdata->spinlock, flags);
247 if (drvdata->reading) {
248 spin_unlock_irqrestore(&drvdata->spinlock, flags);
252 if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
253 tmc_etb_enable_hw(drvdata);
254 } else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
255 tmc_etr_enable_hw(drvdata);
257 if (mode == TMC_MODE_CIRCULAR_BUFFER)
258 tmc_etb_enable_hw(drvdata);
260 tmc_etf_enable_hw(drvdata);
262 drvdata->enable = true;
263 spin_unlock_irqrestore(&drvdata->spinlock, flags);
265 dev_info(drvdata->dev, "TMC enabled\n");
269 static int tmc_enable_sink(struct coresight_device *csdev, u32 mode)
271 struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
273 return tmc_enable(drvdata, TMC_MODE_CIRCULAR_BUFFER);
276 static int tmc_enable_link(struct coresight_device *csdev, int inport,
279 struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
281 return tmc_enable(drvdata, TMC_MODE_HARDWARE_FIFO);
284 static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata)
286 enum tmc_mem_intf_width memwidth;
292 memwidth = BMVAL(readl_relaxed(drvdata->base + CORESIGHT_DEVID), 8, 10);
293 if (memwidth == TMC_MEM_INTF_WIDTH_32BITS)
295 else if (memwidth == TMC_MEM_INTF_WIDTH_64BITS)
297 else if (memwidth == TMC_MEM_INTF_WIDTH_128BITS)
304 for (i = 0; i < memwords; i++) {
305 read_data = readl_relaxed(drvdata->base + TMC_RRD);
306 if (read_data == 0xFFFFFFFF)
308 memcpy(bufp, &read_data, 4);
314 static void tmc_etb_disable_hw(struct tmc_drvdata *drvdata)
316 CS_UNLOCK(drvdata->base);
318 tmc_flush_and_stop(drvdata);
319 tmc_etb_dump_hw(drvdata);
320 tmc_disable_hw(drvdata);
322 CS_LOCK(drvdata->base);
325 static void tmc_etr_dump_hw(struct tmc_drvdata *drvdata)
329 rwp = readl_relaxed(drvdata->base + TMC_RWP);
330 val = readl_relaxed(drvdata->base + TMC_STS);
332 /* How much memory do we still have */
334 drvdata->buf = drvdata->vaddr + rwp - drvdata->paddr;
336 drvdata->buf = drvdata->vaddr;
339 static void tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
341 CS_UNLOCK(drvdata->base);
343 tmc_flush_and_stop(drvdata);
344 tmc_etr_dump_hw(drvdata);
345 tmc_disable_hw(drvdata);
347 CS_LOCK(drvdata->base);
350 static void tmc_etf_disable_hw(struct tmc_drvdata *drvdata)
352 CS_UNLOCK(drvdata->base);
354 tmc_flush_and_stop(drvdata);
355 tmc_disable_hw(drvdata);
357 CS_LOCK(drvdata->base);
360 static void tmc_disable(struct tmc_drvdata *drvdata, enum tmc_mode mode)
364 spin_lock_irqsave(&drvdata->spinlock, flags);
365 if (drvdata->reading)
368 if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
369 tmc_etb_disable_hw(drvdata);
370 } else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
371 tmc_etr_disable_hw(drvdata);
373 if (mode == TMC_MODE_CIRCULAR_BUFFER)
374 tmc_etb_disable_hw(drvdata);
376 tmc_etf_disable_hw(drvdata);
379 drvdata->enable = false;
380 spin_unlock_irqrestore(&drvdata->spinlock, flags);
382 dev_info(drvdata->dev, "TMC disabled\n");
385 static void tmc_disable_sink(struct coresight_device *csdev)
387 struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
389 tmc_disable(drvdata, TMC_MODE_CIRCULAR_BUFFER);
392 static void tmc_disable_link(struct coresight_device *csdev, int inport,
395 struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
397 tmc_disable(drvdata, TMC_MODE_HARDWARE_FIFO);
400 static const struct coresight_ops_sink tmc_sink_ops = {
401 .enable = tmc_enable_sink,
402 .disable = tmc_disable_sink,
405 static const struct coresight_ops_link tmc_link_ops = {
406 .enable = tmc_enable_link,
407 .disable = tmc_disable_link,
410 static const struct coresight_ops tmc_etb_cs_ops = {
411 .sink_ops = &tmc_sink_ops,
414 static const struct coresight_ops tmc_etr_cs_ops = {
415 .sink_ops = &tmc_sink_ops,
418 static const struct coresight_ops tmc_etf_cs_ops = {
419 .sink_ops = &tmc_sink_ops,
420 .link_ops = &tmc_link_ops,
423 static int tmc_read_prepare(struct tmc_drvdata *drvdata)
429 spin_lock_irqsave(&drvdata->spinlock, flags);
430 if (!drvdata->enable)
433 if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
434 tmc_etb_disable_hw(drvdata);
435 } else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
436 tmc_etr_disable_hw(drvdata);
438 mode = readl_relaxed(drvdata->base + TMC_MODE);
439 if (mode == TMC_MODE_CIRCULAR_BUFFER) {
440 tmc_etb_disable_hw(drvdata);
447 drvdata->reading = true;
448 spin_unlock_irqrestore(&drvdata->spinlock, flags);
450 dev_info(drvdata->dev, "TMC read start\n");
453 spin_unlock_irqrestore(&drvdata->spinlock, flags);
457 static void tmc_read_unprepare(struct tmc_drvdata *drvdata)
462 spin_lock_irqsave(&drvdata->spinlock, flags);
463 if (!drvdata->enable)
466 if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
467 tmc_etb_enable_hw(drvdata);
468 } else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
469 tmc_etr_enable_hw(drvdata);
471 mode = readl_relaxed(drvdata->base + TMC_MODE);
472 if (mode == TMC_MODE_CIRCULAR_BUFFER)
473 tmc_etb_enable_hw(drvdata);
476 drvdata->reading = false;
477 spin_unlock_irqrestore(&drvdata->spinlock, flags);
479 dev_info(drvdata->dev, "TMC read end\n");
482 static int tmc_open(struct inode *inode, struct file *file)
484 struct tmc_drvdata *drvdata = container_of(file->private_data,
485 struct tmc_drvdata, miscdev);
488 if (drvdata->read_count++)
491 ret = tmc_read_prepare(drvdata);
495 nonseekable_open(inode, file);
497 dev_dbg(drvdata->dev, "%s: successfully opened\n", __func__);
501 static ssize_t tmc_read(struct file *file, char __user *data, size_t len,
504 struct tmc_drvdata *drvdata = container_of(file->private_data,
505 struct tmc_drvdata, miscdev);
506 char *bufp = drvdata->buf + *ppos;
508 if (*ppos + len > drvdata->size)
509 len = drvdata->size - *ppos;
511 if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
512 if (bufp == (char *)(drvdata->vaddr + drvdata->size))
513 bufp = drvdata->vaddr;
514 else if (bufp > (char *)(drvdata->vaddr + drvdata->size))
515 bufp -= drvdata->size;
516 if ((bufp + len) > (char *)(drvdata->vaddr + drvdata->size))
517 len = (char *)(drvdata->vaddr + drvdata->size) - bufp;
520 if (copy_to_user(data, bufp, len)) {
521 dev_dbg(drvdata->dev, "%s: copy_to_user failed\n", __func__);
527 dev_dbg(drvdata->dev, "%s: %zu bytes copied, %d bytes left\n",
528 __func__, len, (int)(drvdata->size - *ppos));
532 static int tmc_release(struct inode *inode, struct file *file)
534 struct tmc_drvdata *drvdata = container_of(file->private_data,
535 struct tmc_drvdata, miscdev);
537 if (--drvdata->read_count) {
538 if (drvdata->read_count < 0) {
539 dev_err(drvdata->dev, "mismatched close\n");
540 drvdata->read_count = 0;
545 tmc_read_unprepare(drvdata);
547 dev_dbg(drvdata->dev, "%s: released\n", __func__);
551 static const struct file_operations tmc_fops = {
552 .owner = THIS_MODULE,
555 .release = tmc_release,
559 static ssize_t status_show(struct device *dev,
560 struct device_attribute *attr, char *buf)
563 u32 tmc_rsz, tmc_sts, tmc_rrp, tmc_rwp, tmc_trg;
564 u32 tmc_ctl, tmc_ffsr, tmc_ffcr, tmc_mode, tmc_pscr;
566 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
568 pm_runtime_get_sync(drvdata->dev);
569 spin_lock_irqsave(&drvdata->spinlock, flags);
570 CS_UNLOCK(drvdata->base);
572 tmc_rsz = readl_relaxed(drvdata->base + TMC_RSZ);
573 tmc_sts = readl_relaxed(drvdata->base + TMC_STS);
574 tmc_rrp = readl_relaxed(drvdata->base + TMC_RRP);
575 tmc_rwp = readl_relaxed(drvdata->base + TMC_RWP);
576 tmc_trg = readl_relaxed(drvdata->base + TMC_TRG);
577 tmc_ctl = readl_relaxed(drvdata->base + TMC_CTL);
578 tmc_ffsr = readl_relaxed(drvdata->base + TMC_FFSR);
579 tmc_ffcr = readl_relaxed(drvdata->base + TMC_FFCR);
580 tmc_mode = readl_relaxed(drvdata->base + TMC_MODE);
581 tmc_pscr = readl_relaxed(drvdata->base + TMC_PSCR);
582 devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
584 CS_LOCK(drvdata->base);
585 spin_unlock_irqrestore(&drvdata->spinlock, flags);
586 pm_runtime_put(drvdata->dev);
591 "RAM read ptr:\t0x%x\n"
592 "RAM wrt ptr:\t0x%x\n"
593 "Trigger cnt:\t0x%x\n"
595 "Flush status:\t0x%x\n"
596 "Flush ctrl:\t0x%x\n"
600 tmc_rsz, tmc_sts, tmc_rrp, tmc_rwp, tmc_trg,
601 tmc_ctl, tmc_ffsr, tmc_ffcr, tmc_mode, tmc_pscr, devid);
605 static DEVICE_ATTR_RO(status);
607 static ssize_t trigger_cntr_show(struct device *dev,
608 struct device_attribute *attr, char *buf)
610 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
611 unsigned long val = drvdata->trigger_cntr;
613 return sprintf(buf, "%#lx\n", val);
616 static ssize_t trigger_cntr_store(struct device *dev,
617 struct device_attribute *attr,
618 const char *buf, size_t size)
622 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
624 ret = kstrtoul(buf, 16, &val);
628 drvdata->trigger_cntr = val;
631 static DEVICE_ATTR_RW(trigger_cntr);
633 static struct attribute *coresight_etb_attrs[] = {
634 &dev_attr_trigger_cntr.attr,
635 &dev_attr_status.attr,
638 ATTRIBUTE_GROUPS(coresight_etb);
640 static struct attribute *coresight_etr_attrs[] = {
641 &dev_attr_trigger_cntr.attr,
642 &dev_attr_status.attr,
645 ATTRIBUTE_GROUPS(coresight_etr);
647 static struct attribute *coresight_etf_attrs[] = {
648 &dev_attr_trigger_cntr.attr,
649 &dev_attr_status.attr,
652 ATTRIBUTE_GROUPS(coresight_etf);
654 static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
659 struct device *dev = &adev->dev;
660 struct coresight_platform_data *pdata = NULL;
661 struct tmc_drvdata *drvdata;
662 struct resource *res = &adev->res;
663 struct coresight_desc *desc;
664 struct device_node *np = adev->dev.of_node;
667 pdata = of_get_coresight_platform_data(dev, np);
669 return PTR_ERR(pdata);
670 adev->dev.platform_data = pdata;
673 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
677 drvdata->dev = &adev->dev;
678 dev_set_drvdata(dev, drvdata);
680 /* Validity for the resource is already checked by the AMBA core */
681 base = devm_ioremap_resource(dev, res);
683 return PTR_ERR(base);
685 drvdata->base = base;
687 spin_lock_init(&drvdata->spinlock);
689 devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
690 drvdata->config_type = BMVAL(devid, 6, 7);
692 if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
694 ret = of_property_read_u32(np,
698 drvdata->size = SZ_1M;
700 drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4;
703 pm_runtime_put(&adev->dev);
705 if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
706 drvdata->vaddr = dma_alloc_coherent(dev, drvdata->size,
707 &drvdata->paddr, GFP_KERNEL);
711 memset(drvdata->vaddr, 0, drvdata->size);
712 drvdata->buf = drvdata->vaddr;
714 drvdata->buf = devm_kzalloc(dev, drvdata->size, GFP_KERNEL);
719 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
722 goto err_devm_kzalloc;
727 desc->subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
729 if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
730 desc->type = CORESIGHT_DEV_TYPE_SINK;
731 desc->ops = &tmc_etb_cs_ops;
732 desc->groups = coresight_etb_groups;
733 } else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
734 desc->type = CORESIGHT_DEV_TYPE_SINK;
735 desc->ops = &tmc_etr_cs_ops;
736 desc->groups = coresight_etr_groups;
738 desc->type = CORESIGHT_DEV_TYPE_LINKSINK;
739 desc->subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
740 desc->ops = &tmc_etf_cs_ops;
741 desc->groups = coresight_etf_groups;
744 drvdata->csdev = coresight_register(desc);
745 if (IS_ERR(drvdata->csdev)) {
746 ret = PTR_ERR(drvdata->csdev);
747 goto err_devm_kzalloc;
750 drvdata->miscdev.name = pdata->name;
751 drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
752 drvdata->miscdev.fops = &tmc_fops;
753 ret = misc_register(&drvdata->miscdev);
755 goto err_misc_register;
757 dev_info(dev, "TMC initialized\n");
761 coresight_unregister(drvdata->csdev);
763 if (drvdata->config_type == TMC_CONFIG_TYPE_ETR)
764 dma_free_coherent(dev, drvdata->size,
765 drvdata->vaddr, drvdata->paddr);
769 static struct amba_id tmc_ids[] = {
777 static struct amba_driver tmc_driver = {
779 .name = "coresight-tmc",
780 .owner = THIS_MODULE,
781 .suppress_bind_attrs = true,
786 builtin_amba_driver(tmc_driver);