2 * Copyright(C) 2016 Linaro Limited. All rights reserved.
3 * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/circ_buf.h>
19 #include <linux/coresight.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
23 #include "coresight-priv.h"
24 #include "coresight-tmc.h"
27 * struct cs_etr_buffer - keep track of a recording session' specifics
28 * @tmc: generic portion of the TMC buffers
29 * @paddr: the physical address of a DMA'able contiguous memory area
30 * @vaddr: the virtual address associated to @paddr
31 * @size: how much memory we have, starting at @paddr
32 * @dev: the device @vaddr has been tied to
34 struct cs_etr_buffers {
35 struct cs_buffers tmc;
42 void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
46 /* Zero out the memory to help with debug */
47 memset(drvdata->vaddr, 0, drvdata->size);
49 CS_UNLOCK(drvdata->base);
51 /* Wait for TMCSReady bit to be set */
52 tmc_wait_for_tmcready(drvdata);
54 writel_relaxed(drvdata->size / 4, drvdata->base + TMC_RSZ);
55 writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
57 axictl = readl_relaxed(drvdata->base + TMC_AXICTL);
58 axictl |= TMC_AXICTL_WR_BURST_16;
59 writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
60 axictl &= ~TMC_AXICTL_SCT_GAT_MODE;
61 writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
63 ~(TMC_AXICTL_PROT_CTL_B0 | TMC_AXICTL_PROT_CTL_B1)) |
64 TMC_AXICTL_PROT_CTL_B1;
65 writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
67 writel_relaxed(drvdata->paddr, drvdata->base + TMC_DBALO);
68 writel_relaxed(0x0, drvdata->base + TMC_DBAHI);
69 writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
70 TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
71 TMC_FFCR_TRIGON_TRIGIN,
72 drvdata->base + TMC_FFCR);
73 writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
74 tmc_enable_hw(drvdata);
76 CS_LOCK(drvdata->base);
79 static void tmc_etr_dump_hw(struct tmc_drvdata *drvdata)
83 rwp = readl_relaxed(drvdata->base + TMC_RWP);
84 val = readl_relaxed(drvdata->base + TMC_STS);
86 /* How much memory do we still have */
88 drvdata->buf = drvdata->vaddr + rwp - drvdata->paddr;
90 drvdata->buf = drvdata->vaddr;
93 static void tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
95 CS_UNLOCK(drvdata->base);
97 tmc_flush_and_stop(drvdata);
99 * When operating in sysFS mode the content of the buffer needs to be
100 * read before the TMC is disabled.
102 if (local_read(&drvdata->mode) == CS_MODE_SYSFS)
103 tmc_etr_dump_hw(drvdata);
104 tmc_disable_hw(drvdata);
106 CS_LOCK(drvdata->base);
109 static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev, u32 mode)
115 void __iomem *vaddr = NULL;
117 struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
119 /* This shouldn't be happening */
120 if (WARN_ON(mode != CS_MODE_SYSFS))
124 * If we don't have a buffer release the lock and allocate memory.
125 * Otherwise keep the lock and move along.
127 spin_lock_irqsave(&drvdata->spinlock, flags);
128 if (!drvdata->vaddr) {
129 spin_unlock_irqrestore(&drvdata->spinlock, flags);
132 * Contiguous memory can't be allocated while a spinlock is
133 * held. As such allocate memory here and free it if a buffer
134 * has already been allocated (from a previous session).
136 vaddr = dma_alloc_coherent(drvdata->dev, drvdata->size,
141 /* Let's try again */
142 spin_lock_irqsave(&drvdata->spinlock, flags);
145 if (drvdata->reading) {
150 val = local_xchg(&drvdata->mode, mode);
152 * In sysFS mode we can have multiple writers per sink. Since this
153 * sink is already enabled no memory is needed and the HW need not be
156 if (val == CS_MODE_SYSFS)
160 * If drvdata::buf == NULL, use the memory allocated above.
161 * Otherwise a buffer still exists from a previous session, so
164 if (drvdata->buf == NULL) {
166 drvdata->vaddr = vaddr;
167 drvdata->paddr = paddr;
168 drvdata->buf = drvdata->vaddr;
171 memset(drvdata->vaddr, 0, drvdata->size);
173 tmc_etr_enable_hw(drvdata);
175 spin_unlock_irqrestore(&drvdata->spinlock, flags);
177 /* Free memory outside the spinlock if need be */
179 dma_free_coherent(drvdata->dev, drvdata->size, vaddr, paddr);
182 dev_info(drvdata->dev, "TMC-ETR enabled\n");
187 static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, u32 mode)
192 struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
194 /* This shouldn't be happening */
195 if (WARN_ON(mode != CS_MODE_PERF))
198 spin_lock_irqsave(&drvdata->spinlock, flags);
199 if (drvdata->reading) {
204 val = local_xchg(&drvdata->mode, mode);
206 * In Perf mode there can be only one writer per sink. There
207 * is also no need to continue if the ETR is already operated
210 if (val != CS_MODE_DISABLED) {
215 tmc_etr_enable_hw(drvdata);
217 spin_unlock_irqrestore(&drvdata->spinlock, flags);
222 static int tmc_enable_etr_sink(struct coresight_device *csdev, u32 mode)
226 return tmc_enable_etr_sink_sysfs(csdev, mode);
228 return tmc_enable_etr_sink_perf(csdev, mode);
231 /* We shouldn't be here */
235 static void tmc_disable_etr_sink(struct coresight_device *csdev)
239 struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
241 spin_lock_irqsave(&drvdata->spinlock, flags);
242 if (drvdata->reading) {
243 spin_unlock_irqrestore(&drvdata->spinlock, flags);
247 val = local_xchg(&drvdata->mode, CS_MODE_DISABLED);
248 /* Disable the TMC only if it needs to */
249 if (val != CS_MODE_DISABLED)
250 tmc_etr_disable_hw(drvdata);
252 spin_unlock_irqrestore(&drvdata->spinlock, flags);
254 dev_info(drvdata->dev, "TMC-ETR disabled\n");
257 static void *tmc_alloc_etr_buffer(struct coresight_device *csdev, int cpu,
258 void **pages, int nr_pages, bool overwrite)
261 struct cs_etr_buffers *buf;
262 struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
265 cpu = smp_processor_id();
266 node = cpu_to_node(cpu);
268 /* Allocate memory structure for interaction with Perf */
269 buf = kzalloc_node(sizeof(struct cs_etr_buffers), GFP_KERNEL, node);
273 buf->dev = drvdata->dev;
274 buf->size = drvdata->size;
275 buf->vaddr = dma_alloc_coherent(buf->dev, buf->size,
276 &buf->paddr, GFP_KERNEL);
282 buf->tmc.snapshot = overwrite;
283 buf->tmc.nr_pages = nr_pages;
284 buf->tmc.data_pages = pages;
289 static void tmc_free_etr_buffer(void *config)
291 struct cs_etr_buffers *buf = config;
293 dma_free_coherent(buf->dev, buf->size, buf->vaddr, buf->paddr);
297 static int tmc_set_etr_buffer(struct coresight_device *csdev,
298 struct perf_output_handle *handle,
303 struct cs_etr_buffers *buf = sink_config;
304 struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
306 /* wrap head around to the amount of space we have */
307 head = handle->head & ((buf->tmc.nr_pages << PAGE_SHIFT) - 1);
309 /* find the page to write to */
310 buf->tmc.cur = head / PAGE_SIZE;
312 /* and offset within that page */
313 buf->tmc.offset = head % PAGE_SIZE;
315 local_set(&buf->tmc.data_size, 0);
317 /* Tell the HW where to put the trace data */
318 drvdata->vaddr = buf->vaddr;
319 drvdata->paddr = buf->paddr;
320 memset(drvdata->vaddr, 0, drvdata->size);
325 static unsigned long tmc_reset_etr_buffer(struct coresight_device *csdev,
326 struct perf_output_handle *handle,
327 void *sink_config, bool *lost)
330 struct cs_etr_buffers *buf = sink_config;
331 struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
335 * In snapshot mode ->data_size holds the new address of the
336 * ring buffer's head. The size itself is the whole address
337 * range since we want the latest information.
339 if (buf->tmc.snapshot) {
340 size = buf->tmc.nr_pages << PAGE_SHIFT;
341 handle->head = local_xchg(&buf->tmc.data_size, size);
345 * Tell the tracer PMU how much we got in this run and if
346 * something went wrong along the way. Nobody else can use
347 * this cs_etr_buffers instance until we are done. As such
348 * resetting parameters here and squaring off with the ring
349 * buffer API in the tracer PMU is fine.
351 *lost = !!local_xchg(&buf->tmc.lost, 0);
352 size = local_xchg(&buf->tmc.data_size, 0);
355 /* Get ready for another run */
356 drvdata->vaddr = NULL;
362 static void tmc_update_etr_buffer(struct coresight_device *csdev,
363 struct perf_output_handle *handle,
368 u32 read_ptr, write_ptr;
370 unsigned long offset;
371 struct cs_buffers *buf = sink_config;
372 struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
377 /* This shouldn't happen */
378 if (WARN_ON_ONCE(local_read(&drvdata->mode) != CS_MODE_PERF))
381 CS_UNLOCK(drvdata->base);
383 tmc_flush_and_stop(drvdata);
385 read_ptr = readl_relaxed(drvdata->base + TMC_RRP);
386 write_ptr = readl_relaxed(drvdata->base + TMC_RWP);
389 * Get a hold of the status register and see if a wrap around
390 * has occurred. If so adjust things accordingly.
392 status = readl_relaxed(drvdata->base + TMC_STS);
393 if (status & TMC_STS_FULL) {
394 local_inc(&buf->lost);
395 to_read = drvdata->size;
397 to_read = CIRC_CNT(write_ptr, read_ptr, drvdata->size);
401 * The TMC RAM buffer may be bigger than the space available in the
402 * perf ring buffer (handle->size). If so advance the RRP so that we
403 * get the latest trace data.
405 if (to_read > handle->size) {
406 u32 buffer_start, mask = 0;
408 /* Read buffer start address in system memory */
409 buffer_start = readl_relaxed(drvdata->base + TMC_DBALO);
412 * The value written to RRP must be byte-address aligned to
413 * the width of the trace memory databus _and_ to a frame
414 * boundary (16 byte), whichever is the biggest. For example,
415 * for 32-bit, 64-bit and 128-bit wide trace memory, the four
416 * LSBs must be 0s. For 256-bit wide trace memory, the five
419 switch (drvdata->memwidth) {
420 case TMC_MEM_INTF_WIDTH_32BITS:
421 case TMC_MEM_INTF_WIDTH_64BITS:
422 case TMC_MEM_INTF_WIDTH_128BITS:
423 mask = GENMASK(31, 5);
425 case TMC_MEM_INTF_WIDTH_256BITS:
426 mask = GENMASK(31, 6);
431 * Make sure the new size is aligned in accordance with the
432 * requirement explained above.
434 to_read = handle->size & mask;
435 /* Move the RAM read pointer up */
436 read_ptr = (write_ptr + drvdata->size) - to_read;
437 /* Make sure we are still within our limits */
438 if (read_ptr > (buffer_start + (drvdata->size - 1)))
439 read_ptr -= drvdata->size;
441 writel_relaxed(read_ptr, drvdata->base + TMC_RRP);
442 local_inc(&buf->lost);
446 offset = buf->offset;
448 /* for every byte to read */
449 for (i = 0; i < to_read; i += 4) {
450 buf_ptr = buf->data_pages[cur] + offset;
451 *buf_ptr = readl_relaxed(drvdata->base + TMC_RRD);
454 if (offset >= PAGE_SIZE) {
457 /* wrap around at the end of the buffer */
458 cur &= buf->nr_pages - 1;
463 * In snapshot mode all we have to do is communicate to
464 * perf_aux_output_end() the address of the current head. In full
465 * trace mode the same function expects a size to move rb->aux_head
469 local_set(&buf->data_size, (cur * PAGE_SIZE) + offset);
471 local_add(to_read, &buf->data_size);
473 CS_LOCK(drvdata->base);
476 static const struct coresight_ops_sink tmc_etr_sink_ops = {
477 .enable = tmc_enable_etr_sink,
478 .disable = tmc_disable_etr_sink,
479 .alloc_buffer = tmc_alloc_etr_buffer,
480 .free_buffer = tmc_free_etr_buffer,
481 .set_buffer = tmc_set_etr_buffer,
482 .reset_buffer = tmc_reset_etr_buffer,
483 .update_buffer = tmc_update_etr_buffer,
486 const struct coresight_ops tmc_etr_cs_ops = {
487 .sink_ops = &tmc_etr_sink_ops,
490 int tmc_read_prepare_etr(struct tmc_drvdata *drvdata)
496 /* config types are set a boot time and never change */
497 if (WARN_ON_ONCE(drvdata->config_type != TMC_CONFIG_TYPE_ETR))
500 spin_lock_irqsave(&drvdata->spinlock, flags);
501 if (drvdata->reading) {
506 val = local_read(&drvdata->mode);
507 /* Don't interfere if operated from Perf */
508 if (val == CS_MODE_PERF) {
513 /* If drvdata::buf is NULL the trace data has been read already */
514 if (drvdata->buf == NULL) {
519 /* Disable the TMC if need be */
520 if (val == CS_MODE_SYSFS)
521 tmc_etr_disable_hw(drvdata);
523 drvdata->reading = true;
525 spin_unlock_irqrestore(&drvdata->spinlock, flags);
530 int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata)
534 void __iomem *vaddr = NULL;
536 /* config types are set a boot time and never change */
537 if (WARN_ON_ONCE(drvdata->config_type != TMC_CONFIG_TYPE_ETR))
540 spin_lock_irqsave(&drvdata->spinlock, flags);
542 /* RE-enable the TMC if need be */
543 if (local_read(&drvdata->mode) == CS_MODE_SYSFS) {
545 * The trace run will continue with the same allocated trace
546 * buffer. The trace buffer is cleared in tmc_etr_enable_hw(),
547 * so we don't have to explicitly clear it. Also, since the
548 * tracer is still enabled drvdata::buf can't be NULL.
550 tmc_etr_enable_hw(drvdata);
553 * The ETR is not tracing and the buffer was just read.
554 * As such prepare to free the trace buffer.
556 vaddr = drvdata->vaddr;
557 paddr = drvdata->paddr;
558 drvdata->buf = drvdata->vaddr = NULL;
561 drvdata->reading = false;
562 spin_unlock_irqrestore(&drvdata->spinlock, flags);
564 /* Free allocated memory out side of the spinlock */
566 dma_free_coherent(drvdata->dev, drvdata->size, vaddr, paddr);