drivers/hwtracing/coresight/coresight-etm3x.c

   1 /* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/init.h>
  16 #include <linux/types.h>
  17 #include <linux/device.h>
  18 #include <linux/io.h>
  19 #include <linux/err.h>
  20 #include <linux/fs.h>
  21 #include <linux/slab.h>
  22 #include <linux/delay.h>
  23 #include <linux/smp.h>
  24 #include <linux/sysfs.h>
  25 #include <linux/stat.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/cpu.h>
  28 #include <linux/of.h>
  29 #include <linux/coresight.h>
  30 #include <linux/amba/bus.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/uaccess.h>
  33 #include <linux/clk.h>
  34 #include <asm/sections.h>
  35
  36 #include "coresight-etm.h"
  37
  38 static int boot_enable;
  39 module_param_named(boot_enable, boot_enable, int, S_IRUGO);
  40
  41 /* The number of ETM/PTM currently registered */
  42 static int etm_count;
  43 static struct etm_drvdata *etmdrvdata[NR_CPUS];
  44
  45 static inline void etm_writel(struct etm_drvdata *drvdata,
  46                               u32 val, u32 off)
  47 {
  48         if (drvdata->use_cp14) {
  49                 if (etm_writel_cp14(off, val)) {
  50                         dev_err(drvdata->dev,
  51                                 "invalid CP14 access to ETM reg: %#x", off);
  52                 }
  53         } else {
  54                 writel_relaxed(val, drvdata->base + off);
  55         }
  56 }
  57
  58 static inline unsigned int etm_readl(struct etm_drvdata *drvdata, u32 off)
  59 {
  60         u32 val;
  61
  62         if (drvdata->use_cp14) {
  63                 if (etm_readl_cp14(off, &val)) {
  64                         dev_err(drvdata->dev,
  65                                 "invalid CP14 access to ETM reg: %#x", off);
  66                 }
  67         } else {
  68                 val = readl_relaxed(drvdata->base + off);
  69         }
  70
  71         return val;
  72 }
  73
  74 /*
  75  * Memory mapped writes to clear os lock are not supported on some processors
  76  * and OS lock must be unlocked before any memory mapped access on such
  77  * processors, otherwise memory mapped reads/writes will be invalid.
  78  */
  79 static void etm_os_unlock(void *info)
  80 {
  81         struct etm_drvdata *drvdata = (struct etm_drvdata *)info;
  82         /* Writing any value to ETMOSLAR unlocks the trace registers */
  83         etm_writel(drvdata, 0x0, ETMOSLAR);
  84         isb();
  85 }
  86
  87 static void etm_set_pwrdwn(struct etm_drvdata *drvdata)
  88 {
  89         u32 etmcr;
  90
  91         /* Ensure pending cp14 accesses complete before setting pwrdwn */
  92         mb();
  93         isb();
  94         etmcr = etm_readl(drvdata, ETMCR);
  95         etmcr |= ETMCR_PWD_DWN;
  96         etm_writel(drvdata, etmcr, ETMCR);
  97 }
  98
  99 static void etm_clr_pwrdwn(struct etm_drvdata *drvdata)
 100 {
 101         u32 etmcr;
 102
 103         etmcr = etm_readl(drvdata, ETMCR);
 104         etmcr &= ~ETMCR_PWD_DWN;
 105         etm_writel(drvdata, etmcr, ETMCR);
 106         /* Ensure pwrup completes before subsequent cp14 accesses */
 107         mb();
 108         isb();
 109 }
 110
 111 static void etm_set_pwrup(struct etm_drvdata *drvdata)
 112 {
 113         u32 etmpdcr;
 114
 115         etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
 116         etmpdcr |= ETMPDCR_PWD_UP;
 117         writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
 118         /* Ensure pwrup completes before subsequent cp14 accesses */
 119         mb();
 120         isb();
 121 }
 122
 123 static void etm_clr_pwrup(struct etm_drvdata *drvdata)
 124 {
 125         u32 etmpdcr;
 126
 127         /* Ensure pending cp14 accesses complete before clearing pwrup */
 128         mb();
 129         isb();
 130         etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
 131         etmpdcr &= ~ETMPDCR_PWD_UP;
 132         writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
 133 }
 134
 135 /**
 136  * coresight_timeout_etm - loop until a bit has changed to a specific state.
 137  * @drvdata: etm's private data structure.
 138  * @offset: address of a register, starting from @addr.
 139  * @position: the position of the bit of interest.
 140  * @value: the value the bit should have.
 141  *
 142  * Basically the same as @coresight_timeout except for the register access
 143  * method where we have to account for CP14 configurations.
 144
 145  * Return: 0 as soon as the bit has taken the desired state or -EAGAIN if
 146  * TIMEOUT_US has elapsed, which ever happens first.
 147  */
 148
 149 static int coresight_timeout_etm(struct etm_drvdata *drvdata, u32 offset,
 150                                   int position, int value)
 151 {
 152         int i;
 153         u32 val;
 154
 155         for (i = TIMEOUT_US; i > 0; i--) {
 156                 val = etm_readl(drvdata, offset);
 157                 /* Waiting on the bit to go from 0 to 1 */
 158                 if (value) {
 159                         if (val & BIT(position))
 160                                 return 0;
 161                 /* Waiting on the bit to go from 1 to 0 */
 162                 } else {
 163                         if (!(val & BIT(position)))
 164                                 return 0;
 165                 }
 166
 167                 /*
 168                  * Delay is arbitrary - the specification doesn't say how long
 169                  * we are expected to wait.  Extra check required to make sure
 170                  * we don't wait needlessly on the last iteration.
 171                  */
 172                 if (i - 1)
 173                         udelay(1);
 174         }
 175
 176         return -EAGAIN;
 177 }
 178
 179
 180 static void etm_set_prog(struct etm_drvdata *drvdata)
 181 {
 182         u32 etmcr;
 183
 184         etmcr = etm_readl(drvdata, ETMCR);
 185         etmcr |= ETMCR_ETM_PRG;
 186         etm_writel(drvdata, etmcr, ETMCR);
 187         /*
 188          * Recommended by spec for cp14 accesses to ensure etmcr write is
 189          * complete before polling etmsr
 190          */
 191         isb();
 192         if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 1)) {
 193                 dev_err(drvdata->dev,
 194                         "%s: timeout observed when probing at offset %#x\n",
 195                         __func__, ETMSR);
 196         }
 197 }
 198
 199 static void etm_clr_prog(struct etm_drvdata *drvdata)
 200 {
 201         u32 etmcr;
 202
 203         etmcr = etm_readl(drvdata, ETMCR);
 204         etmcr &= ~ETMCR_ETM_PRG;
 205         etm_writel(drvdata, etmcr, ETMCR);
 206         /*
 207          * Recommended by spec for cp14 accesses to ensure etmcr write is
 208          * complete before polling etmsr
 209          */
 210         isb();
 211         if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 0)) {
 212                 dev_err(drvdata->dev,
 213                         "%s: timeout observed when probing at offset %#x\n",
 214                         __func__, ETMSR);
 215         }
 216 }
 217
 218 static void etm_set_default(struct etm_drvdata *drvdata)
 219 {
 220         int i;
 221
 222         drvdata->trigger_event = ETM_DEFAULT_EVENT_VAL;
 223         drvdata->enable_event = ETM_HARD_WIRE_RES_A;
 224
 225         drvdata->seq_12_event = ETM_DEFAULT_EVENT_VAL;
 226         drvdata->seq_21_event = ETM_DEFAULT_EVENT_VAL;
 227         drvdata->seq_23_event = ETM_DEFAULT_EVENT_VAL;
 228         drvdata->seq_31_event = ETM_DEFAULT_EVENT_VAL;
 229         drvdata->seq_32_event = ETM_DEFAULT_EVENT_VAL;
 230         drvdata->seq_13_event = ETM_DEFAULT_EVENT_VAL;
 231         drvdata->timestamp_event = ETM_DEFAULT_EVENT_VAL;
 232
 233         for (i = 0; i < drvdata->nr_cntr; i++) {
 234                 drvdata->cntr_rld_val[i] = 0x0;
 235                 drvdata->cntr_event[i] = ETM_DEFAULT_EVENT_VAL;
 236                 drvdata->cntr_rld_event[i] = ETM_DEFAULT_EVENT_VAL;
 237                 drvdata->cntr_val[i] = 0x0;
 238         }
 239
 240         drvdata->seq_curr_state = 0x0;
 241         drvdata->ctxid_idx = 0x0;
 242         for (i = 0; i < drvdata->nr_ctxid_cmp; i++) {
 243                 drvdata->ctxid_pid[i] = 0x0;
 244                 drvdata->ctxid_vpid[i] = 0x0;
 245         }
 246
 247         drvdata->ctxid_mask = 0x0;
 248 }
 249
 250 static void etm_enable_hw(void *info)
 251 {
 252         int i;
 253         u32 etmcr;
 254         struct etm_drvdata *drvdata = info;
 255
 256         CS_UNLOCK(drvdata->base);
 257
 258         /* Turn engine on */
 259         etm_clr_pwrdwn(drvdata);
 260         /* Apply power to trace registers */
 261         etm_set_pwrup(drvdata);
 262         /* Make sure all registers are accessible */
 263         etm_os_unlock(drvdata);
 264
 265         etm_set_prog(drvdata);
 266
 267         etmcr = etm_readl(drvdata, ETMCR);
 268         etmcr &= (ETMCR_PWD_DWN | ETMCR_ETM_PRG);
 269         etmcr |= drvdata->port_size;
 270         etm_writel(drvdata, drvdata->ctrl | etmcr, ETMCR);
 271         etm_writel(drvdata, drvdata->trigger_event, ETMTRIGGER);
 272         etm_writel(drvdata, drvdata->startstop_ctrl, ETMTSSCR);
 273         etm_writel(drvdata, drvdata->enable_event, ETMTEEVR);
 274         etm_writel(drvdata, drvdata->enable_ctrl1, ETMTECR1);
 275         etm_writel(drvdata, drvdata->fifofull_level, ETMFFLR);
 276         for (i = 0; i < drvdata->nr_addr_cmp; i++) {
 277                 etm_writel(drvdata, drvdata->addr_val[i], ETMACVRn(i));
 278                 etm_writel(drvdata, drvdata->addr_acctype[i], ETMACTRn(i));
 279         }
 280         for (i = 0; i < drvdata->nr_cntr; i++) {
 281                 etm_writel(drvdata, drvdata->cntr_rld_val[i], ETMCNTRLDVRn(i));
 282                 etm_writel(drvdata, drvdata->cntr_event[i], ETMCNTENRn(i));
 283                 etm_writel(drvdata, drvdata->cntr_rld_event[i],
 284                            ETMCNTRLDEVRn(i));
 285                 etm_writel(drvdata, drvdata->cntr_val[i], ETMCNTVRn(i));
 286         }
 287         etm_writel(drvdata, drvdata->seq_12_event, ETMSQ12EVR);
 288         etm_writel(drvdata, drvdata->seq_21_event, ETMSQ21EVR);
 289         etm_writel(drvdata, drvdata->seq_23_event, ETMSQ23EVR);
 290         etm_writel(drvdata, drvdata->seq_31_event, ETMSQ31EVR);
 291         etm_writel(drvdata, drvdata->seq_32_event, ETMSQ32EVR);
 292         etm_writel(drvdata, drvdata->seq_13_event, ETMSQ13EVR);
 293         etm_writel(drvdata, drvdata->seq_curr_state, ETMSQR);
 294         for (i = 0; i < drvdata->nr_ext_out; i++)
 295                 etm_writel(drvdata, ETM_DEFAULT_EVENT_VAL, ETMEXTOUTEVRn(i));
 296         for (i = 0; i < drvdata->nr_ctxid_cmp; i++)
 297                 etm_writel(drvdata, drvdata->ctxid_pid[i], ETMCIDCVRn(i));
 298         etm_writel(drvdata, drvdata->ctxid_mask, ETMCIDCMR);
 299         etm_writel(drvdata, drvdata->sync_freq, ETMSYNCFR);
 300         /* No external input selected */
 301         etm_writel(drvdata, 0x0, ETMEXTINSELR);
 302         etm_writel(drvdata, drvdata->timestamp_event, ETMTSEVR);
 303         /* No auxiliary control selected */
 304         etm_writel(drvdata, 0x0, ETMAUXCR);
 305         etm_writel(drvdata, drvdata->traceid, ETMTRACEIDR);
 306         /* No VMID comparator value selected */
 307         etm_writel(drvdata, 0x0, ETMVMIDCVR);
 308
 309         /* Ensures trace output is enabled from this ETM */
 310         etm_writel(drvdata, drvdata->ctrl | ETMCR_ETM_EN | etmcr, ETMCR);
 311
 312         etm_clr_prog(drvdata);
 313         CS_LOCK(drvdata->base);
 314
 315         dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
 316 }
 317
 318 static int etm_cpu_id(struct coresight_device *csdev)
 319 {
 320         struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 321
 322         return drvdata->cpu;
 323 }
 324
 325 static int etm_trace_id(struct coresight_device *csdev)
 326 {
 327         struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 328         unsigned long flags;
 329         int trace_id = -1;
 330
 331         if (!drvdata->enable)
 332                 return drvdata->traceid;
 333         pm_runtime_get_sync(csdev->dev.parent);
 334
 335         spin_lock_irqsave(&drvdata->spinlock, flags);
 336
 337         CS_UNLOCK(drvdata->base);
 338         trace_id = (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK);
 339         CS_LOCK(drvdata->base);
 340
 341         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 342         pm_runtime_put(csdev->dev.parent);
 343
 344         return trace_id;
 345 }
 346
 347 static int etm_enable(struct coresight_device *csdev)
 348 {
 349         struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 350         int ret;
 351
 352         spin_lock(&drvdata->spinlock);
 353
 354         /*
 355          * Configure the ETM only if the CPU is online.  If it isn't online
 356          * hw configuration will take place when 'CPU_STARTING' is received
 357          * in @etm_cpu_callback.
 358          */
 359         if (cpu_online(drvdata->cpu)) {
 360                 ret = smp_call_function_single(drvdata->cpu,
 361                                                etm_enable_hw, drvdata, 1);
 362                 if (ret)
 363                         goto err;
 364         }
 365
 366         drvdata->enable = true;
 367         drvdata->sticky_enable = true;
 368
 369         spin_unlock(&drvdata->spinlock);
 370
 371         dev_info(drvdata->dev, "ETM tracing enabled\n");
 372         return 0;
 373 err:
 374         spin_unlock(&drvdata->spinlock);
 375         return ret;
 376 }
 377
 378 static void etm_disable_hw(void *info)
 379 {
 380         int i;
 381         struct etm_drvdata *drvdata = info;
 382
 383         CS_UNLOCK(drvdata->base);
 384         etm_set_prog(drvdata);
 385
 386         /* Program trace enable to low by using always false event */
 387         etm_writel(drvdata, ETM_HARD_WIRE_RES_A | ETM_EVENT_NOT_A, ETMTEEVR);
 388
 389         /* Read back sequencer and counters for post trace analysis */
 390         drvdata->seq_curr_state = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
 391
 392         for (i = 0; i < drvdata->nr_cntr; i++)
 393                 drvdata->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i));
 394
 395         etm_set_pwrdwn(drvdata);
 396         CS_LOCK(drvdata->base);
 397
 398         dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
 399 }
 400
 401 static void etm_disable(struct coresight_device *csdev)
 402 {
 403         struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 404
 405         /*
 406          * Taking hotplug lock here protects from clocks getting disabled
 407          * with tracing being left on (crash scenario) if user disable occurs
 408          * after cpu online mask indicates the cpu is offline but before the
 409          * DYING hotplug callback is serviced by the ETM driver.
 410          */
 411         get_online_cpus();
 412         spin_lock(&drvdata->spinlock);
 413
 414         /*
 415          * Executing etm_disable_hw on the cpu whose ETM is being disabled
 416          * ensures that register writes occur when cpu is powered.
 417          */
 418         smp_call_function_single(drvdata->cpu, etm_disable_hw, drvdata, 1);
 419         drvdata->enable = false;
 420
 421         spin_unlock(&drvdata->spinlock);
 422         put_online_cpus();
 423
 424         dev_info(drvdata->dev, "ETM tracing disabled\n");
 425 }
 426
 427 static const struct coresight_ops_source etm_source_ops = {
 428         .cpu_id         = etm_cpu_id,
 429         .trace_id       = etm_trace_id,
 430         .enable         = etm_enable,
 431         .disable        = etm_disable,
 432 };
 433
 434 static const struct coresight_ops etm_cs_ops = {
 435         .source_ops     = &etm_source_ops,
 436 };
 437
 438 static ssize_t nr_addr_cmp_show(struct device *dev,
 439                                 struct device_attribute *attr, char *buf)
 440 {
 441         unsigned long val;
 442         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 443
 444         val = drvdata->nr_addr_cmp;
 445         return sprintf(buf, "%#lx\n", val);
 446 }
 447 static DEVICE_ATTR_RO(nr_addr_cmp);
 448
 449 static ssize_t nr_cntr_show(struct device *dev,
 450                             struct device_attribute *attr, char *buf)
 451 {       unsigned long val;
 452         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 453
 454         val = drvdata->nr_cntr;
 455         return sprintf(buf, "%#lx\n", val);
 456 }
 457 static DEVICE_ATTR_RO(nr_cntr);
 458
 459 static ssize_t nr_ctxid_cmp_show(struct device *dev,
 460                                  struct device_attribute *attr, char *buf)
 461 {
 462         unsigned long val;
 463         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 464
 465         val = drvdata->nr_ctxid_cmp;
 466         return sprintf(buf, "%#lx\n", val);
 467 }
 468 static DEVICE_ATTR_RO(nr_ctxid_cmp);
 469
 470 static ssize_t etmsr_show(struct device *dev,
 471                           struct device_attribute *attr, char *buf)
 472 {
 473         unsigned long flags, val;
 474         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 475
 476         pm_runtime_get_sync(drvdata->dev);
 477         spin_lock_irqsave(&drvdata->spinlock, flags);
 478         CS_UNLOCK(drvdata->base);
 479
 480         val = etm_readl(drvdata, ETMSR);
 481
 482         CS_LOCK(drvdata->base);
 483         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 484         pm_runtime_put(drvdata->dev);
 485
 486         return sprintf(buf, "%#lx\n", val);
 487 }
 488 static DEVICE_ATTR_RO(etmsr);
 489
 490 static ssize_t reset_store(struct device *dev,
 491                            struct device_attribute *attr,
 492                            const char *buf, size_t size)
 493 {
 494         int i, ret;
 495         unsigned long val;
 496         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 497
 498         ret = kstrtoul(buf, 16, &val);
 499         if (ret)
 500                 return ret;
 501
 502         if (val) {
 503                 spin_lock(&drvdata->spinlock);
 504                 drvdata->mode = ETM_MODE_EXCLUDE;
 505                 drvdata->ctrl = 0x0;
 506                 drvdata->trigger_event = ETM_DEFAULT_EVENT_VAL;
 507                 drvdata->startstop_ctrl = 0x0;
 508                 drvdata->addr_idx = 0x0;
 509                 for (i = 0; i < drvdata->nr_addr_cmp; i++) {
 510                         drvdata->addr_val[i] = 0x0;
 511                         drvdata->addr_acctype[i] = 0x0;
 512                         drvdata->addr_type[i] = ETM_ADDR_TYPE_NONE;
 513                 }
 514                 drvdata->cntr_idx = 0x0;
 515
 516                 etm_set_default(drvdata);
 517                 spin_unlock(&drvdata->spinlock);
 518         }
 519
 520         return size;
 521 }
 522 static DEVICE_ATTR_WO(reset);
 523
 524 static ssize_t mode_show(struct device *dev,
 525                          struct device_attribute *attr, char *buf)
 526 {
 527         unsigned long val;
 528         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 529
 530         val = drvdata->mode;
 531         return sprintf(buf, "%#lx\n", val);
 532 }
 533
 534 static ssize_t mode_store(struct device *dev,
 535                           struct device_attribute *attr,
 536                           const char *buf, size_t size)
 537 {
 538         int ret;
 539         unsigned long val;
 540         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 541
 542         ret = kstrtoul(buf, 16, &val);
 543         if (ret)
 544                 return ret;
 545
 546         spin_lock(&drvdata->spinlock);
 547         drvdata->mode = val & ETM_MODE_ALL;
 548
 549         if (drvdata->mode & ETM_MODE_EXCLUDE)
 550                 drvdata->enable_ctrl1 |= ETMTECR1_INC_EXC;
 551         else
 552                 drvdata->enable_ctrl1 &= ~ETMTECR1_INC_EXC;
 553
 554         if (drvdata->mode & ETM_MODE_CYCACC)
 555                 drvdata->ctrl |= ETMCR_CYC_ACC;
 556         else
 557                 drvdata->ctrl &= ~ETMCR_CYC_ACC;
 558
 559         if (drvdata->mode & ETM_MODE_STALL) {
 560                 if (!(drvdata->etmccr & ETMCCR_FIFOFULL)) {
 561                         dev_warn(drvdata->dev, "stall mode not supported\n");
 562                         ret = -EINVAL;
 563                         goto err_unlock;
 564                 }
 565                 drvdata->ctrl |= ETMCR_STALL_MODE;
 566          } else
 567                 drvdata->ctrl &= ~ETMCR_STALL_MODE;
 568
 569         if (drvdata->mode & ETM_MODE_TIMESTAMP) {
 570                 if (!(drvdata->etmccer & ETMCCER_TIMESTAMP)) {
 571                         dev_warn(drvdata->dev, "timestamp not supported\n");
 572                         ret = -EINVAL;
 573                         goto err_unlock;
 574                 }
 575                 drvdata->ctrl |= ETMCR_TIMESTAMP_EN;
 576         } else
 577                 drvdata->ctrl &= ~ETMCR_TIMESTAMP_EN;
 578
 579         if (drvdata->mode & ETM_MODE_CTXID)
 580                 drvdata->ctrl |= ETMCR_CTXID_SIZE;
 581         else
 582                 drvdata->ctrl &= ~ETMCR_CTXID_SIZE;
 583         spin_unlock(&drvdata->spinlock);
 584
 585         return size;
 586
 587 err_unlock:
 588         spin_unlock(&drvdata->spinlock);
 589         return ret;
 590 }
 591 static DEVICE_ATTR_RW(mode);
 592
 593 static ssize_t trigger_event_show(struct device *dev,
 594                                   struct device_attribute *attr, char *buf)
 595 {
 596         unsigned long val;
 597         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 598
 599         val = drvdata->trigger_event;
 600         return sprintf(buf, "%#lx\n", val);
 601 }
 602
 603 static ssize_t trigger_event_store(struct device *dev,
 604                                    struct device_attribute *attr,
 605                                    const char *buf, size_t size)
 606 {
 607         int ret;
 608         unsigned long val;
 609         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 610
 611         ret = kstrtoul(buf, 16, &val);
 612         if (ret)
 613                 return ret;
 614
 615         drvdata->trigger_event = val & ETM_EVENT_MASK;
 616
 617         return size;
 618 }
 619 static DEVICE_ATTR_RW(trigger_event);
 620
 621 static ssize_t enable_event_show(struct device *dev,
 622                                  struct device_attribute *attr, char *buf)
 623 {
 624         unsigned long val;
 625         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 626
 627         val = drvdata->enable_event;
 628         return sprintf(buf, "%#lx\n", val);
 629 }
 630
 631 static ssize_t enable_event_store(struct device *dev,
 632                                   struct device_attribute *attr,
 633                                   const char *buf, size_t size)
 634 {
 635         int ret;
 636         unsigned long val;
 637         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 638
 639         ret = kstrtoul(buf, 16, &val);
 640         if (ret)
 641                 return ret;
 642
 643         drvdata->enable_event = val & ETM_EVENT_MASK;
 644
 645         return size;
 646 }
 647 static DEVICE_ATTR_RW(enable_event);
 648
 649 static ssize_t fifofull_level_show(struct device *dev,
 650                                    struct device_attribute *attr, char *buf)
 651 {
 652         unsigned long val;
 653         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 654
 655         val = drvdata->fifofull_level;
 656         return sprintf(buf, "%#lx\n", val);
 657 }
 658
 659 static ssize_t fifofull_level_store(struct device *dev,
 660                                     struct device_attribute *attr,
 661                                     const char *buf, size_t size)
 662 {
 663         int ret;
 664         unsigned long val;
 665         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 666
 667         ret = kstrtoul(buf, 16, &val);
 668         if (ret)
 669                 return ret;
 670
 671         drvdata->fifofull_level = val;
 672
 673         return size;
 674 }
 675 static DEVICE_ATTR_RW(fifofull_level);
 676
 677 static ssize_t addr_idx_show(struct device *dev,
 678                              struct device_attribute *attr, char *buf)
 679 {
 680         unsigned long val;
 681         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 682
 683         val = drvdata->addr_idx;
 684         return sprintf(buf, "%#lx\n", val);
 685 }
 686
 687 static ssize_t addr_idx_store(struct device *dev,
 688                               struct device_attribute *attr,
 689                               const char *buf, size_t size)
 690 {
 691         int ret;
 692         unsigned long val;
 693         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 694
 695         ret = kstrtoul(buf, 16, &val);
 696         if (ret)
 697                 return ret;
 698
 699         if (val >= drvdata->nr_addr_cmp)
 700                 return -EINVAL;
 701
 702         /*
 703          * Use spinlock to ensure index doesn't change while it gets
 704          * dereferenced multiple times within a spinlock block elsewhere.
 705          */
 706         spin_lock(&drvdata->spinlock);
 707         drvdata->addr_idx = val;
 708         spin_unlock(&drvdata->spinlock);
 709
 710         return size;
 711 }
 712 static DEVICE_ATTR_RW(addr_idx);
 713
 714 static ssize_t addr_single_show(struct device *dev,
 715                                 struct device_attribute *attr, char *buf)
 716 {
 717         u8 idx;
 718         unsigned long val;
 719         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 720
 721         spin_lock(&drvdata->spinlock);
 722         idx = drvdata->addr_idx;
 723         if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
 724               drvdata->addr_type[idx] == ETM_ADDR_TYPE_SINGLE)) {
 725                 spin_unlock(&drvdata->spinlock);
 726                 return -EINVAL;
 727         }
 728
 729         val = drvdata->addr_val[idx];
 730         spin_unlock(&drvdata->spinlock);
 731
 732         return sprintf(buf, "%#lx\n", val);
 733 }
 734
 735 static ssize_t addr_single_store(struct device *dev,
 736                                  struct device_attribute *attr,
 737                                  const char *buf, size_t size)
 738 {
 739         u8 idx;
 740         int ret;
 741         unsigned long val;
 742         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 743
 744         ret = kstrtoul(buf, 16, &val);
 745         if (ret)
 746                 return ret;
 747
 748         spin_lock(&drvdata->spinlock);
 749         idx = drvdata->addr_idx;
 750         if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
 751               drvdata->addr_type[idx] == ETM_ADDR_TYPE_SINGLE)) {
 752                 spin_unlock(&drvdata->spinlock);
 753                 return -EINVAL;
 754         }
 755
 756         drvdata->addr_val[idx] = val;
 757         drvdata->addr_type[idx] = ETM_ADDR_TYPE_SINGLE;
 758         spin_unlock(&drvdata->spinlock);
 759
 760         return size;
 761 }
 762 static DEVICE_ATTR_RW(addr_single);
 763
 764 static ssize_t addr_range_show(struct device *dev,
 765                                struct device_attribute *attr, char *buf)
 766 {
 767         u8 idx;
 768         unsigned long val1, val2;
 769         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 770
 771         spin_lock(&drvdata->spinlock);
 772         idx = drvdata->addr_idx;
 773         if (idx % 2 != 0) {
 774                 spin_unlock(&drvdata->spinlock);
 775                 return -EPERM;
 776         }
 777         if (!((drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE &&
 778                drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_NONE) ||
 779               (drvdata->addr_type[idx] == ETM_ADDR_TYPE_RANGE &&
 780                drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_RANGE))) {
 781                 spin_unlock(&drvdata->spinlock);
 782                 return -EPERM;
 783         }
 784
 785         val1 = drvdata->addr_val[idx];
 786         val2 = drvdata->addr_val[idx + 1];
 787         spin_unlock(&drvdata->spinlock);
 788
 789         return sprintf(buf, "%#lx %#lx\n", val1, val2);
 790 }
 791
 792 static ssize_t addr_range_store(struct device *dev,
 793                               struct device_attribute *attr,
 794                               const char *buf, size_t size)
 795 {
 796         u8 idx;
 797         unsigned long val1, val2;
 798         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 799
 800         if (sscanf(buf, "%lx %lx", &val1, &val2) != 2)
 801                 return -EINVAL;
 802         /* Lower address comparator cannot have a higher address value */
 803         if (val1 > val2)
 804                 return -EINVAL;
 805
 806         spin_lock(&drvdata->spinlock);
 807         idx = drvdata->addr_idx;
 808         if (idx % 2 != 0) {
 809                 spin_unlock(&drvdata->spinlock);
 810                 return -EPERM;
 811         }
 812         if (!((drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE &&
 813                drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_NONE) ||
 814               (drvdata->addr_type[idx] == ETM_ADDR_TYPE_RANGE &&
 815                drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_RANGE))) {
 816                 spin_unlock(&drvdata->spinlock);
 817                 return -EPERM;
 818         }
 819
 820         drvdata->addr_val[idx] = val1;
 821         drvdata->addr_type[idx] = ETM_ADDR_TYPE_RANGE;
 822         drvdata->addr_val[idx + 1] = val2;
 823         drvdata->addr_type[idx + 1] = ETM_ADDR_TYPE_RANGE;
 824         drvdata->enable_ctrl1 |= (1 << (idx/2));
 825         spin_unlock(&drvdata->spinlock);
 826
 827         return size;
 828 }
 829 static DEVICE_ATTR_RW(addr_range);
 830
 831 static ssize_t addr_start_show(struct device *dev,
 832                                struct device_attribute *attr, char *buf)
 833 {
 834         u8 idx;
 835         unsigned long val;
 836         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 837
 838         spin_lock(&drvdata->spinlock);
 839         idx = drvdata->addr_idx;
 840         if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
 841               drvdata->addr_type[idx] == ETM_ADDR_TYPE_START)) {
 842                 spin_unlock(&drvdata->spinlock);
 843                 return -EPERM;
 844         }
 845
 846         val = drvdata->addr_val[idx];
 847         spin_unlock(&drvdata->spinlock);
 848
 849         return sprintf(buf, "%#lx\n", val);
 850 }
 851
 852 static ssize_t addr_start_store(struct device *dev,
 853                                 struct device_attribute *attr,
 854                                 const char *buf, size_t size)
 855 {
 856         u8 idx;
 857         int ret;
 858         unsigned long val;
 859         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 860
 861         ret = kstrtoul(buf, 16, &val);
 862         if (ret)
 863                 return ret;
 864
 865         spin_lock(&drvdata->spinlock);
 866         idx = drvdata->addr_idx;
 867         if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
 868               drvdata->addr_type[idx] == ETM_ADDR_TYPE_START)) {
 869                 spin_unlock(&drvdata->spinlock);
 870                 return -EPERM;
 871         }
 872
 873         drvdata->addr_val[idx] = val;
 874         drvdata->addr_type[idx] = ETM_ADDR_TYPE_START;
 875         drvdata->startstop_ctrl |= (1 << idx);
 876         drvdata->enable_ctrl1 |= BIT(25);
 877         spin_unlock(&drvdata->spinlock);
 878
 879         return size;
 880 }
 881 static DEVICE_ATTR_RW(addr_start);
 882
 883 static ssize_t addr_stop_show(struct device *dev,
 884                               struct device_attribute *attr, char *buf)
 885 {
 886         u8 idx;
 887         unsigned long val;
 888         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 889
 890         spin_lock(&drvdata->spinlock);
 891         idx = drvdata->addr_idx;
 892         if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
 893               drvdata->addr_type[idx] == ETM_ADDR_TYPE_STOP)) {
 894                 spin_unlock(&drvdata->spinlock);
 895                 return -EPERM;
 896         }
 897
 898         val = drvdata->addr_val[idx];
 899         spin_unlock(&drvdata->spinlock);
 900
 901         return sprintf(buf, "%#lx\n", val);
 902 }
 903
 904 static ssize_t addr_stop_store(struct device *dev,
 905                                struct device_attribute *attr,
 906                                const char *buf, size_t size)
 907 {
 908         u8 idx;
 909         int ret;
 910         unsigned long val;
 911         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 912
 913         ret = kstrtoul(buf, 16, &val);
 914         if (ret)
 915                 return ret;
 916
 917         spin_lock(&drvdata->spinlock);
 918         idx = drvdata->addr_idx;
 919         if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
 920               drvdata->addr_type[idx] == ETM_ADDR_TYPE_STOP)) {
 921                 spin_unlock(&drvdata->spinlock);
 922                 return -EPERM;
 923         }
 924
 925         drvdata->addr_val[idx] = val;
 926         drvdata->addr_type[idx] = ETM_ADDR_TYPE_STOP;
 927         drvdata->startstop_ctrl |= (1 << (idx + 16));
 928         drvdata->enable_ctrl1 |= ETMTECR1_START_STOP;
 929         spin_unlock(&drvdata->spinlock);
 930
 931         return size;
 932 }
 933 static DEVICE_ATTR_RW(addr_stop);
 934
 935 static ssize_t addr_acctype_show(struct device *dev,
 936                                  struct device_attribute *attr, char *buf)
 937 {
 938         unsigned long val;
 939         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 940
 941         spin_lock(&drvdata->spinlock);
 942         val = drvdata->addr_acctype[drvdata->addr_idx];
 943         spin_unlock(&drvdata->spinlock);
 944
 945         return sprintf(buf, "%#lx\n", val);
 946 }
 947
 948 static ssize_t addr_acctype_store(struct device *dev,
 949                                   struct device_attribute *attr,
 950                                   const char *buf, size_t size)
 951 {
 952         int ret;
 953         unsigned long val;
 954         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 955
 956         ret = kstrtoul(buf, 16, &val);
 957         if (ret)
 958                 return ret;
 959
 960         spin_lock(&drvdata->spinlock);
 961         drvdata->addr_acctype[drvdata->addr_idx] = val;
 962         spin_unlock(&drvdata->spinlock);
 963
 964         return size;
 965 }
 966 static DEVICE_ATTR_RW(addr_acctype);
 967
 968 static ssize_t cntr_idx_show(struct device *dev,
 969                              struct device_attribute *attr, char *buf)
 970 {
 971         unsigned long val;
 972         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 973
 974         val = drvdata->cntr_idx;
 975         return sprintf(buf, "%#lx\n", val);
 976 }
 977
 978 static ssize_t cntr_idx_store(struct device *dev,
 979                               struct device_attribute *attr,
 980                               const char *buf, size_t size)
 981 {
 982         int ret;
 983         unsigned long val;
 984         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 985
 986         ret = kstrtoul(buf, 16, &val);
 987         if (ret)
 988                 return ret;
 989
 990         if (val >= drvdata->nr_cntr)
 991                 return -EINVAL;
 992         /*
 993          * Use spinlock to ensure index doesn't change while it gets
 994          * dereferenced multiple times within a spinlock block elsewhere.
 995          */
 996         spin_lock(&drvdata->spinlock);
 997         drvdata->cntr_idx = val;
 998         spin_unlock(&drvdata->spinlock);
 999
1000         return size;
1001 }
1002 static DEVICE_ATTR_RW(cntr_idx);
1003
1004 static ssize_t cntr_rld_val_show(struct device *dev,
1005                                  struct device_attribute *attr, char *buf)
1006 {
1007         unsigned long val;
1008         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1009
1010         spin_lock(&drvdata->spinlock);
1011         val = drvdata->cntr_rld_val[drvdata->cntr_idx];
1012         spin_unlock(&drvdata->spinlock);
1013
1014         return sprintf(buf, "%#lx\n", val);
1015 }
1016
1017 static ssize_t cntr_rld_val_store(struct device *dev,
1018                                   struct device_attribute *attr,
1019                                   const char *buf, size_t size)
1020 {
1021         int ret;
1022         unsigned long val;
1023         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1024
1025         ret = kstrtoul(buf, 16, &val);
1026         if (ret)
1027                 return ret;
1028
1029         spin_lock(&drvdata->spinlock);
1030         drvdata->cntr_rld_val[drvdata->cntr_idx] = val;
1031         spin_unlock(&drvdata->spinlock);
1032
1033         return size;
1034 }
1035 static DEVICE_ATTR_RW(cntr_rld_val);
1036
1037 static ssize_t cntr_event_show(struct device *dev,
1038                                struct device_attribute *attr, char *buf)
1039 {
1040         unsigned long val;
1041         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1042
1043         spin_lock(&drvdata->spinlock);
1044         val = drvdata->cntr_event[drvdata->cntr_idx];
1045         spin_unlock(&drvdata->spinlock);
1046
1047         return sprintf(buf, "%#lx\n", val);
1048 }
1049
1050 static ssize_t cntr_event_store(struct device *dev,
1051                                 struct device_attribute *attr,
1052                                 const char *buf, size_t size)
1053 {
1054         int ret;
1055         unsigned long val;
1056         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1057
1058         ret = kstrtoul(buf, 16, &val);
1059         if (ret)
1060                 return ret;
1061
1062         spin_lock(&drvdata->spinlock);
1063         drvdata->cntr_event[drvdata->cntr_idx] = val & ETM_EVENT_MASK;
1064         spin_unlock(&drvdata->spinlock);
1065
1066         return size;
1067 }
1068 static DEVICE_ATTR_RW(cntr_event);
1069
1070 static ssize_t cntr_rld_event_show(struct device *dev,
1071                                    struct device_attribute *attr, char *buf)
1072 {
1073         unsigned long val;
1074         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1075
1076         spin_lock(&drvdata->spinlock);
1077         val = drvdata->cntr_rld_event[drvdata->cntr_idx];
1078         spin_unlock(&drvdata->spinlock);
1079
1080         return sprintf(buf, "%#lx\n", val);
1081 }
1082
1083 static ssize_t cntr_rld_event_store(struct device *dev,
1084                                     struct device_attribute *attr,
1085                                     const char *buf, size_t size)
1086 {
1087         int ret;
1088         unsigned long val;
1089         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1090
1091         ret = kstrtoul(buf, 16, &val);
1092         if (ret)
1093                 return ret;
1094
1095         spin_lock(&drvdata->spinlock);
1096         drvdata->cntr_rld_event[drvdata->cntr_idx] = val & ETM_EVENT_MASK;
1097         spin_unlock(&drvdata->spinlock);
1098
1099         return size;
1100 }
1101 static DEVICE_ATTR_RW(cntr_rld_event);
1102
1103 static ssize_t cntr_val_show(struct device *dev,
1104                              struct device_attribute *attr, char *buf)
1105 {
1106         int i, ret = 0;
1107         u32 val;
1108         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1109
1110         if (!drvdata->enable) {
1111                 spin_lock(&drvdata->spinlock);
1112                 for (i = 0; i < drvdata->nr_cntr; i++)
1113                         ret += sprintf(buf, "counter %d: %x\n",
1114                                        i, drvdata->cntr_val[i]);
1115                 spin_unlock(&drvdata->spinlock);
1116                 return ret;
1117         }
1118
1119         for (i = 0; i < drvdata->nr_cntr; i++) {
1120                 val = etm_readl(drvdata, ETMCNTVRn(i));
1121                 ret += sprintf(buf, "counter %d: %x\n", i, val);
1122         }
1123
1124         return ret;
1125 }
1126
1127 static ssize_t cntr_val_store(struct device *dev,
1128                               struct device_attribute *attr,
1129                               const char *buf, size_t size)
1130 {
1131         int ret;
1132         unsigned long val;
1133         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1134
1135         ret = kstrtoul(buf, 16, &val);
1136         if (ret)
1137                 return ret;
1138
1139         spin_lock(&drvdata->spinlock);
1140         drvdata->cntr_val[drvdata->cntr_idx] = val;
1141         spin_unlock(&drvdata->spinlock);
1142
1143         return size;
1144 }
1145 static DEVICE_ATTR_RW(cntr_val);
1146
1147 static ssize_t seq_12_event_show(struct device *dev,
1148                                  struct device_attribute *attr, char *buf)
1149 {
1150         unsigned long val;
1151         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1152
1153         val = drvdata->seq_12_event;
1154         return sprintf(buf, "%#lx\n", val);
1155 }
1156
1157 static ssize_t seq_12_event_store(struct device *dev,
1158                                   struct device_attribute *attr,
1159                                   const char *buf, size_t size)
1160 {
1161         int ret;
1162         unsigned long val;
1163         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1164
1165         ret = kstrtoul(buf, 16, &val);
1166         if (ret)
1167                 return ret;
1168
1169         drvdata->seq_12_event = val & ETM_EVENT_MASK;
1170         return size;
1171 }
1172 static DEVICE_ATTR_RW(seq_12_event);
1173
1174 static ssize_t seq_21_event_show(struct device *dev,
1175                                  struct device_attribute *attr, char *buf)
1176 {
1177         unsigned long val;
1178         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1179
1180         val = drvdata->seq_21_event;
1181         return sprintf(buf, "%#lx\n", val);
1182 }
1183
1184 static ssize_t seq_21_event_store(struct device *dev,
1185                                   struct device_attribute *attr,
1186                                   const char *buf, size_t size)
1187 {
1188         int ret;
1189         unsigned long val;
1190         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1191
1192         ret = kstrtoul(buf, 16, &val);
1193         if (ret)
1194                 return ret;
1195
1196         drvdata->seq_21_event = val & ETM_EVENT_MASK;
1197         return size;
1198 }
1199 static DEVICE_ATTR_RW(seq_21_event);
1200
1201 static ssize_t seq_23_event_show(struct device *dev,
1202                                  struct device_attribute *attr, char *buf)
1203 {
1204         unsigned long val;
1205         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1206
1207         val = drvdata->seq_23_event;
1208         return sprintf(buf, "%#lx\n", val);
1209 }
1210
1211 static ssize_t seq_23_event_store(struct device *dev,
1212                                   struct device_attribute *attr,
1213                                   const char *buf, size_t size)
1214 {
1215         int ret;
1216         unsigned long val;
1217         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1218
1219         ret = kstrtoul(buf, 16, &val);
1220         if (ret)
1221                 return ret;
1222
1223         drvdata->seq_23_event = val & ETM_EVENT_MASK;
1224         return size;
1225 }
1226 static DEVICE_ATTR_RW(seq_23_event);
1227
1228 static ssize_t seq_31_event_show(struct device *dev,
1229                                  struct device_attribute *attr, char *buf)
1230 {
1231         unsigned long val;
1232         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1233
1234         val = drvdata->seq_31_event;
1235         return sprintf(buf, "%#lx\n", val);
1236 }
1237
1238 static ssize_t seq_31_event_store(struct device *dev,
1239                                   struct device_attribute *attr,
1240                                   const char *buf, size_t size)
1241 {
1242         int ret;
1243         unsigned long val;
1244         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1245
1246         ret = kstrtoul(buf, 16, &val);
1247         if (ret)
1248                 return ret;
1249
1250         drvdata->seq_31_event = val & ETM_EVENT_MASK;
1251         return size;
1252 }
1253 static DEVICE_ATTR_RW(seq_31_event);
1254
1255 static ssize_t seq_32_event_show(struct device *dev,
1256                                  struct device_attribute *attr, char *buf)
1257 {
1258         unsigned long val;
1259         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1260
1261         val = drvdata->seq_32_event;
1262         return sprintf(buf, "%#lx\n", val);
1263 }
1264
1265 static ssize_t seq_32_event_store(struct device *dev,
1266                                   struct device_attribute *attr,
1267                                   const char *buf, size_t size)
1268 {
1269         int ret;
1270         unsigned long val;
1271         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1272
1273         ret = kstrtoul(buf, 16, &val);
1274         if (ret)
1275                 return ret;
1276
1277         drvdata->seq_32_event = val & ETM_EVENT_MASK;
1278         return size;
1279 }
1280 static DEVICE_ATTR_RW(seq_32_event);
1281
1282 static ssize_t seq_13_event_show(struct device *dev,
1283                                  struct device_attribute *attr, char *buf)
1284 {
1285         unsigned long val;
1286         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1287
1288         val = drvdata->seq_13_event;
1289         return sprintf(buf, "%#lx\n", val);
1290 }
1291
1292 static ssize_t seq_13_event_store(struct device *dev,
1293                                   struct device_attribute *attr,
1294                                   const char *buf, size_t size)
1295 {
1296         int ret;
1297         unsigned long val;
1298         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1299
1300         ret = kstrtoul(buf, 16, &val);
1301         if (ret)
1302                 return ret;
1303
1304         drvdata->seq_13_event = val & ETM_EVENT_MASK;
1305         return size;
1306 }
1307 static DEVICE_ATTR_RW(seq_13_event);
1308
1309 static ssize_t seq_curr_state_show(struct device *dev,
1310                                    struct device_attribute *attr, char *buf)
1311 {
1312         unsigned long val, flags;
1313         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1314
1315         if (!drvdata->enable) {
1316                 val = drvdata->seq_curr_state;
1317                 goto out;
1318         }
1319
1320         pm_runtime_get_sync(drvdata->dev);
1321         spin_lock_irqsave(&drvdata->spinlock, flags);
1322
1323         CS_UNLOCK(drvdata->base);
1324         val = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
1325         CS_LOCK(drvdata->base);
1326
1327         spin_unlock_irqrestore(&drvdata->spinlock, flags);
1328         pm_runtime_put(drvdata->dev);
1329 out:
1330         return sprintf(buf, "%#lx\n", val);
1331 }
1332
1333 static ssize_t seq_curr_state_store(struct device *dev,
1334                                     struct device_attribute *attr,
1335                                     const char *buf, size_t size)
1336 {
1337         int ret;
1338         unsigned long val;
1339         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1340
1341         ret = kstrtoul(buf, 16, &val);
1342         if (ret)
1343                 return ret;
1344
1345         if (val > ETM_SEQ_STATE_MAX_VAL)
1346                 return -EINVAL;
1347
1348         drvdata->seq_curr_state = val;
1349
1350         return size;
1351 }
1352 static DEVICE_ATTR_RW(seq_curr_state);
1353
1354 static ssize_t ctxid_idx_show(struct device *dev,
1355                               struct device_attribute *attr, char *buf)
1356 {
1357         unsigned long val;
1358         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1359
1360         val = drvdata->ctxid_idx;
1361         return sprintf(buf, "%#lx\n", val);
1362 }
1363
1364 static ssize_t ctxid_idx_store(struct device *dev,
1365                                 struct device_attribute *attr,
1366                                 const char *buf, size_t size)
1367 {
1368         int ret;
1369         unsigned long val;
1370         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1371
1372         ret = kstrtoul(buf, 16, &val);
1373         if (ret)
1374                 return ret;
1375
1376         if (val >= drvdata->nr_ctxid_cmp)
1377                 return -EINVAL;
1378
1379         /*
1380          * Use spinlock to ensure index doesn't change while it gets
1381          * dereferenced multiple times within a spinlock block elsewhere.
1382          */
1383         spin_lock(&drvdata->spinlock);
1384         drvdata->ctxid_idx = val;
1385         spin_unlock(&drvdata->spinlock);
1386
1387         return size;
1388 }
1389 static DEVICE_ATTR_RW(ctxid_idx);
1390
1391 static ssize_t ctxid_pid_show(struct device *dev,
1392                               struct device_attribute *attr, char *buf)
1393 {
1394         unsigned long val;
1395         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1396
1397         spin_lock(&drvdata->spinlock);
1398         val = drvdata->ctxid_vpid[drvdata->ctxid_idx];
1399         spin_unlock(&drvdata->spinlock);
1400
1401         return sprintf(buf, "%#lx\n", val);
1402 }
1403
1404 static ssize_t ctxid_pid_store(struct device *dev,
1405                                struct device_attribute *attr,
1406                                const char *buf, size_t size)
1407 {
1408         int ret;
1409         unsigned long vpid, pid;
1410         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1411
1412         ret = kstrtoul(buf, 16, &vpid);
1413         if (ret)
1414                 return ret;
1415
1416         pid = coresight_vpid_to_pid(vpid);
1417
1418         spin_lock(&drvdata->spinlock);
1419         drvdata->ctxid_pid[drvdata->ctxid_idx] = pid;
1420         drvdata->ctxid_vpid[drvdata->ctxid_idx] = vpid;
1421         spin_unlock(&drvdata->spinlock);
1422
1423         return size;
1424 }
1425 static DEVICE_ATTR_RW(ctxid_pid);
1426
1427 static ssize_t ctxid_mask_show(struct device *dev,
1428                                struct device_attribute *attr, char *buf)
1429 {
1430         unsigned long val;
1431         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1432
1433         val = drvdata->ctxid_mask;
1434         return sprintf(buf, "%#lx\n", val);
1435 }
1436
1437 static ssize_t ctxid_mask_store(struct device *dev,
1438                                 struct device_attribute *attr,
1439                                 const char *buf, size_t size)
1440 {
1441         int ret;
1442         unsigned long val;
1443         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1444
1445         ret = kstrtoul(buf, 16, &val);
1446         if (ret)
1447                 return ret;
1448
1449         drvdata->ctxid_mask = val;
1450         return size;
1451 }
1452 static DEVICE_ATTR_RW(ctxid_mask);
1453
1454 static ssize_t sync_freq_show(struct device *dev,
1455                               struct device_attribute *attr, char *buf)
1456 {
1457         unsigned long val;
1458         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1459
1460         val = drvdata->sync_freq;
1461         return sprintf(buf, "%#lx\n", val);
1462 }
1463
1464 static ssize_t sync_freq_store(struct device *dev,
1465                                struct device_attribute *attr,
1466                                const char *buf, size_t size)
1467 {
1468         int ret;
1469         unsigned long val;
1470         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1471
1472         ret = kstrtoul(buf, 16, &val);
1473         if (ret)
1474                 return ret;
1475
1476         drvdata->sync_freq = val & ETM_SYNC_MASK;
1477         return size;
1478 }
1479 static DEVICE_ATTR_RW(sync_freq);
1480
1481 static ssize_t timestamp_event_show(struct device *dev,
1482                                     struct device_attribute *attr, char *buf)
1483 {
1484         unsigned long val;
1485         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1486
1487         val = drvdata->timestamp_event;
1488         return sprintf(buf, "%#lx\n", val);
1489 }
1490
1491 static ssize_t timestamp_event_store(struct device *dev,
1492                                      struct device_attribute *attr,
1493                                      const char *buf, size_t size)
1494 {
1495         int ret;
1496         unsigned long val;
1497         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1498
1499         ret = kstrtoul(buf, 16, &val);
1500         if (ret)
1501                 return ret;
1502
1503         drvdata->timestamp_event = val & ETM_EVENT_MASK;
1504         return size;
1505 }
1506 static DEVICE_ATTR_RW(timestamp_event);
1507
1508 static ssize_t cpu_show(struct device *dev,
1509                         struct device_attribute *attr, char *buf)
1510 {
1511         int val;
1512         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1513
1514         val = drvdata->cpu;
1515         return scnprintf(buf, PAGE_SIZE, "%d\n", val);
1516
1517 }
1518 static DEVICE_ATTR_RO(cpu);
1519
1520 static ssize_t traceid_show(struct device *dev,
1521                             struct device_attribute *attr, char *buf)
1522 {
1523         unsigned long val, flags;
1524         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1525
1526         if (!drvdata->enable) {
1527                 val = drvdata->traceid;
1528                 goto out;
1529         }
1530
1531         pm_runtime_get_sync(drvdata->dev);
1532         spin_lock_irqsave(&drvdata->spinlock, flags);
1533         CS_UNLOCK(drvdata->base);
1534
1535         val = (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK);
1536
1537         CS_LOCK(drvdata->base);
1538         spin_unlock_irqrestore(&drvdata->spinlock, flags);
1539         pm_runtime_put(drvdata->dev);
1540 out:
1541         return sprintf(buf, "%#lx\n", val);
1542 }
1543
1544 static ssize_t traceid_store(struct device *dev,
1545                              struct device_attribute *attr,
1546                              const char *buf, size_t size)
1547 {
1548         int ret;
1549         unsigned long val;
1550         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1551
1552         ret = kstrtoul(buf, 16, &val);
1553         if (ret)
1554                 return ret;
1555
1556         drvdata->traceid = val & ETM_TRACEID_MASK;
1557         return size;
1558 }
1559 static DEVICE_ATTR_RW(traceid);
1560
1561 static struct attribute *coresight_etm_attrs[] = {
1562         &dev_attr_nr_addr_cmp.attr,
1563         &dev_attr_nr_cntr.attr,
1564         &dev_attr_nr_ctxid_cmp.attr,
1565         &dev_attr_etmsr.attr,
1566         &dev_attr_reset.attr,
1567         &dev_attr_mode.attr,
1568         &dev_attr_trigger_event.attr,
1569         &dev_attr_enable_event.attr,
1570         &dev_attr_fifofull_level.attr,
1571         &dev_attr_addr_idx.attr,
1572         &dev_attr_addr_single.attr,
1573         &dev_attr_addr_range.attr,
1574         &dev_attr_addr_start.attr,
1575         &dev_attr_addr_stop.attr,
1576         &dev_attr_addr_acctype.attr,
1577         &dev_attr_cntr_idx.attr,
1578         &dev_attr_cntr_rld_val.attr,
1579         &dev_attr_cntr_event.attr,
1580         &dev_attr_cntr_rld_event.attr,
1581         &dev_attr_cntr_val.attr,
1582         &dev_attr_seq_12_event.attr,
1583         &dev_attr_seq_21_event.attr,
1584         &dev_attr_seq_23_event.attr,
1585         &dev_attr_seq_31_event.attr,
1586         &dev_attr_seq_32_event.attr,
1587         &dev_attr_seq_13_event.attr,
1588         &dev_attr_seq_curr_state.attr,
1589         &dev_attr_ctxid_idx.attr,
1590         &dev_attr_ctxid_pid.attr,
1591         &dev_attr_ctxid_mask.attr,
1592         &dev_attr_sync_freq.attr,
1593         &dev_attr_timestamp_event.attr,
1594         &dev_attr_traceid.attr,
1595         &dev_attr_cpu.attr,
1596         NULL,
1597 };
1598
1599 #define coresight_simple_func(name, offset)                             \
1600 static ssize_t name##_show(struct device *_dev,                         \
1601                            struct device_attribute *attr, char *buf)    \
1602 {                                                                       \
1603         struct etm_drvdata *drvdata = dev_get_drvdata(_dev->parent);    \
1604         return scnprintf(buf, PAGE_SIZE, "0x%x\n",                      \
1605                          readl_relaxed(drvdata->base + offset));        \
1606 }                                                                       \
1607 DEVICE_ATTR_RO(name)
1608
1609 coresight_simple_func(etmccr, ETMCCR);
1610 coresight_simple_func(etmccer, ETMCCER);
1611 coresight_simple_func(etmscr, ETMSCR);
1612 coresight_simple_func(etmidr, ETMIDR);
1613 coresight_simple_func(etmcr, ETMCR);
1614 coresight_simple_func(etmtraceidr, ETMTRACEIDR);
1615 coresight_simple_func(etmteevr, ETMTEEVR);
1616 coresight_simple_func(etmtssvr, ETMTSSCR);
1617 coresight_simple_func(etmtecr1, ETMTECR1);
1618 coresight_simple_func(etmtecr2, ETMTECR2);
1619
1620 static struct attribute *coresight_etm_mgmt_attrs[] = {
1621         &dev_attr_etmccr.attr,
1622         &dev_attr_etmccer.attr,
1623         &dev_attr_etmscr.attr,
1624         &dev_attr_etmidr.attr,
1625         &dev_attr_etmcr.attr,
1626         &dev_attr_etmtraceidr.attr,
1627         &dev_attr_etmteevr.attr,
1628         &dev_attr_etmtssvr.attr,
1629         &dev_attr_etmtecr1.attr,
1630         &dev_attr_etmtecr2.attr,
1631         NULL,
1632 };
1633
1634 static const struct attribute_group coresight_etm_group = {
1635         .attrs = coresight_etm_attrs,
1636 };
1637
1638
1639 static const struct attribute_group coresight_etm_mgmt_group = {
1640         .attrs = coresight_etm_mgmt_attrs,
1641         .name = "mgmt",
1642 };
1643
1644 static const struct attribute_group *coresight_etm_groups[] = {
1645         &coresight_etm_group,
1646         &coresight_etm_mgmt_group,
1647         NULL,
1648 };
1649
1650 static int etm_cpu_callback(struct notifier_block *nfb, unsigned long action,
1651                             void *hcpu)
1652 {
1653         unsigned int cpu = (unsigned long)hcpu;
1654
1655         if (!etmdrvdata[cpu])
1656                 goto out;
1657
1658         switch (action & (~CPU_TASKS_FROZEN)) {
1659         case CPU_STARTING:
1660                 spin_lock(&etmdrvdata[cpu]->spinlock);
1661                 if (!etmdrvdata[cpu]->os_unlock) {
1662                         etm_os_unlock(etmdrvdata[cpu]);
1663                         etmdrvdata[cpu]->os_unlock = true;
1664                 }
1665
1666                 if (etmdrvdata[cpu]->enable)
1667                         etm_enable_hw(etmdrvdata[cpu]);
1668                 spin_unlock(&etmdrvdata[cpu]->spinlock);
1669                 break;
1670
1671         case CPU_ONLINE:
1672                 if (etmdrvdata[cpu]->boot_enable &&
1673                     !etmdrvdata[cpu]->sticky_enable)
1674                         coresight_enable(etmdrvdata[cpu]->csdev);
1675                 break;
1676
1677         case CPU_DYING:
1678                 spin_lock(&etmdrvdata[cpu]->spinlock);
1679                 if (etmdrvdata[cpu]->enable)
1680                         etm_disable_hw(etmdrvdata[cpu]);
1681                 spin_unlock(&etmdrvdata[cpu]->spinlock);
1682                 break;
1683         }
1684 out:
1685         return NOTIFY_OK;
1686 }
1687
1688 static struct notifier_block etm_cpu_notifier = {
1689         .notifier_call = etm_cpu_callback,
1690 };
1691
1692 static bool etm_arch_supported(u8 arch)
1693 {
1694         switch (arch) {
1695         case ETM_ARCH_V3_3:
1696                 break;
1697         case ETM_ARCH_V3_5:
1698                 break;
1699         case PFT_ARCH_V1_0:
1700                 break;
1701         case PFT_ARCH_V1_1:
1702                 break;
1703         default:
1704                 return false;
1705         }
1706         return true;
1707 }
1708
1709 static void etm_init_arch_data(void *info)
1710 {
1711         u32 etmidr;
1712         u32 etmccr;
1713         struct etm_drvdata *drvdata = info;
1714
1715         CS_UNLOCK(drvdata->base);
1716
1717         /* First dummy read */
1718         (void)etm_readl(drvdata, ETMPDSR);
1719         /* Provide power to ETM: ETMPDCR[3] == 1 */
1720         etm_set_pwrup(drvdata);
1721         /*
1722          * Clear power down bit since when this bit is set writes to
1723          * certain registers might be ignored.
1724          */
1725         etm_clr_pwrdwn(drvdata);
1726         /*
1727          * Set prog bit. It will be set from reset but this is included to
1728          * ensure it is set
1729          */
1730         etm_set_prog(drvdata);
1731
1732         /* Find all capabilities */
1733         etmidr = etm_readl(drvdata, ETMIDR);
1734         drvdata->arch = BMVAL(etmidr, 4, 11);
1735         drvdata->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK;
1736
1737         drvdata->etmccer = etm_readl(drvdata, ETMCCER);
1738         etmccr = etm_readl(drvdata, ETMCCR);
1739         drvdata->etmccr = etmccr;
1740         drvdata->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
1741         drvdata->nr_cntr = BMVAL(etmccr, 13, 15);
1742         drvdata->nr_ext_inp = BMVAL(etmccr, 17, 19);
1743         drvdata->nr_ext_out = BMVAL(etmccr, 20, 22);
1744         drvdata->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
1745
1746         etm_set_pwrdwn(drvdata);
1747         etm_clr_pwrup(drvdata);
1748         CS_LOCK(drvdata->base);
1749 }
1750
1751 static void etm_init_default_data(struct etm_drvdata *drvdata)
1752 {
1753         /*
1754          * A trace ID of value 0 is invalid, so let's start at some
1755          * random value that fits in 7 bits and will be just as good.
1756          */
1757         static int etm3x_traceid = 0x10;
1758
1759         u32 flags = (1 << 0 | /* instruction execute*/
1760                      3 << 3 | /* ARM instruction */
1761                      0 << 5 | /* No data value comparison */
1762                      0 << 7 | /* No exact mach */
1763                      0 << 8 | /* Ignore context ID */
1764                      0 << 10); /* Security ignored */
1765
1766         /*
1767          * Initial configuration only - guarantees sources handled by
1768          * this driver have a unique ID at startup time but not between
1769          * all other types of sources.  For that we lean on the core
1770          * framework.
1771          */
1772         drvdata->traceid = etm3x_traceid++;
1773         drvdata->ctrl = (ETMCR_CYC_ACC | ETMCR_TIMESTAMP_EN);
1774         drvdata->enable_ctrl1 = ETMTECR1_ADDR_COMP_1;
1775         if (drvdata->nr_addr_cmp >= 2) {
1776                 drvdata->addr_val[0] = (u32) _stext;
1777                 drvdata->addr_val[1] = (u32) _etext;
1778                 drvdata->addr_acctype[0] = flags;
1779                 drvdata->addr_acctype[1] = flags;
1780                 drvdata->addr_type[0] = ETM_ADDR_TYPE_RANGE;
1781                 drvdata->addr_type[1] = ETM_ADDR_TYPE_RANGE;
1782         }
1783
1784         etm_set_default(drvdata);
1785 }
1786
1787 static int etm_probe(struct amba_device *adev, const struct amba_id *id)
1788 {
1789         int ret;
1790         void __iomem *base;
1791         struct device *dev = &adev->dev;
1792         struct coresight_platform_data *pdata = NULL;
1793         struct etm_drvdata *drvdata;
1794         struct resource *res = &adev->res;
1795         struct coresight_desc *desc;
1796         struct device_node *np = adev->dev.of_node;
1797
1798         desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
1799         if (!desc)
1800                 return -ENOMEM;
1801
1802         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
1803         if (!drvdata)
1804                 return -ENOMEM;
1805
1806         if (np) {
1807                 pdata = of_get_coresight_platform_data(dev, np);
1808                 if (IS_ERR(pdata))
1809                         return PTR_ERR(pdata);
1810
1811                 adev->dev.platform_data = pdata;
1812                 drvdata->use_cp14 = of_property_read_bool(np, "arm,cp14");
1813         }
1814
1815         drvdata->dev = &adev->dev;
1816         dev_set_drvdata(dev, drvdata);
1817
1818         /* Validity for the resource is already checked by the AMBA core */
1819         base = devm_ioremap_resource(dev, res);
1820         if (IS_ERR(base))
1821                 return PTR_ERR(base);
1822
1823         drvdata->base = base;
1824
1825         spin_lock_init(&drvdata->spinlock);
1826
1827         drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
1828         if (!IS_ERR(drvdata->atclk)) {
1829                 ret = clk_prepare_enable(drvdata->atclk);
1830                 if (ret)
1831                         return ret;
1832         }
1833
1834         drvdata->cpu = pdata ? pdata->cpu : 0;
1835
1836         get_online_cpus();
1837         etmdrvdata[drvdata->cpu] = drvdata;
1838
1839         if (!smp_call_function_single(drvdata->cpu, etm_os_unlock, drvdata, 1))
1840                 drvdata->os_unlock = true;
1841
1842         if (smp_call_function_single(drvdata->cpu,
1843                                      etm_init_arch_data,  drvdata, 1))
1844                 dev_err(dev, "ETM arch init failed\n");
1845
1846         if (!etm_count++)
1847                 register_hotcpu_notifier(&etm_cpu_notifier);
1848
1849         put_online_cpus();
1850
1851         if (etm_arch_supported(drvdata->arch) == false) {
1852                 ret = -EINVAL;
1853                 goto err_arch_supported;
1854         }
1855         etm_init_default_data(drvdata);
1856
1857         desc->type = CORESIGHT_DEV_TYPE_SOURCE;
1858         desc->subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
1859         desc->ops = &etm_cs_ops;
1860         desc->pdata = pdata;
1861         desc->dev = dev;
1862         desc->groups = coresight_etm_groups;
1863         drvdata->csdev = coresight_register(desc);
1864         if (IS_ERR(drvdata->csdev)) {
1865                 ret = PTR_ERR(drvdata->csdev);
1866                 goto err_arch_supported;
1867         }
1868
1869         pm_runtime_put(&adev->dev);
1870         dev_info(dev, "%s initialized\n", (char *)id->data);
1871
1872         if (boot_enable) {
1873                 coresight_enable(drvdata->csdev);
1874                 drvdata->boot_enable = true;
1875         }
1876
1877         return 0;
1878
1879 err_arch_supported:
1880         if (--etm_count == 0)
1881                 unregister_hotcpu_notifier(&etm_cpu_notifier);
1882         return ret;
1883 }
1884
1885 #ifdef CONFIG_PM
1886 static int etm_runtime_suspend(struct device *dev)
1887 {
1888         struct etm_drvdata *drvdata = dev_get_drvdata(dev);
1889
1890         if (drvdata && !IS_ERR(drvdata->atclk))
1891                 clk_disable_unprepare(drvdata->atclk);
1892
1893         return 0;
1894 }
1895
1896 static int etm_runtime_resume(struct device *dev)
1897 {
1898         struct etm_drvdata *drvdata = dev_get_drvdata(dev);
1899
1900         if (drvdata && !IS_ERR(drvdata->atclk))
1901                 clk_prepare_enable(drvdata->atclk);
1902
1903         return 0;
1904 }
1905 #endif
1906
1907 static const struct dev_pm_ops etm_dev_pm_ops = {
1908         SET_RUNTIME_PM_OPS(etm_runtime_suspend, etm_runtime_resume, NULL)
1909 };
1910
1911 static struct amba_id etm_ids[] = {
1912         {       /* ETM 3.3 */
1913                 .id     = 0x0003b921,
1914                 .mask   = 0x0003ffff,
1915                 .data   = "ETM 3.3",
1916         },
1917         {       /* ETM 3.5 */
1918                 .id     = 0x0003b956,
1919                 .mask   = 0x0003ffff,
1920                 .data   = "ETM 3.5",
1921         },
1922         {       /* PTM 1.0 */
1923                 .id     = 0x0003b950,
1924                 .mask   = 0x0003ffff,
1925                 .data   = "PTM 1.0",
1926         },
1927         {       /* PTM 1.1 */
1928                 .id     = 0x0003b95f,
1929                 .mask   = 0x0003ffff,
1930                 .data   = "PTM 1.1",
1931         },
1932         {       /* PTM 1.1 Qualcomm */
1933                 .id     = 0x0003006f,
1934                 .mask   = 0x0003ffff,
1935                 .data   = "PTM 1.1",
1936         },
1937         { 0, 0},
1938 };
1939
1940 static struct amba_driver etm_driver = {
1941         .drv = {
1942                 .name   = "coresight-etm3x",
1943                 .owner  = THIS_MODULE,
1944                 .pm     = &etm_dev_pm_ops,
1945                 .suppress_bind_attrs = true,
1946         },
1947         .probe          = etm_probe,
1948         .id_table       = etm_ids,
1949 };
1950
1951 module_amba_driver(etm_driver);
1952
1953 MODULE_LICENSE("GPL v2");
1954 MODULE_DESCRIPTION("CoreSight Program Flow Trace driver");