1 /* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/types.h>
17 #include <linux/device.h>
19 #include <linux/err.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/smp.h>
24 #include <linux/sysfs.h>
25 #include <linux/stat.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/cpu.h>
29 #include <linux/coresight.h>
30 #include <linux/amba/bus.h>
31 #include <linux/seq_file.h>
32 #include <linux/uaccess.h>
33 #include <linux/clk.h>
34 #include <linux/perf_event.h>
35 #include <asm/sections.h>
37 #include "coresight-etm.h"
39 static int boot_enable;
40 module_param_named(boot_enable, boot_enable, int, S_IRUGO);
42 /* The number of ETM/PTM currently registered */
44 static struct etm_drvdata *etmdrvdata[NR_CPUS];
47 * Memory mapped writes to clear os lock are not supported on some processors
48 * and OS lock must be unlocked before any memory mapped access on such
49 * processors, otherwise memory mapped reads/writes will be invalid.
51 static void etm_os_unlock(struct etm_drvdata *drvdata)
53 /* Writing any value to ETMOSLAR unlocks the trace registers */
54 etm_writel(drvdata, 0x0, ETMOSLAR);
55 drvdata->os_unlock = true;
59 static void etm_set_pwrdwn(struct etm_drvdata *drvdata)
63 /* Ensure pending cp14 accesses complete before setting pwrdwn */
66 etmcr = etm_readl(drvdata, ETMCR);
67 etmcr |= ETMCR_PWD_DWN;
68 etm_writel(drvdata, etmcr, ETMCR);
71 static void etm_clr_pwrdwn(struct etm_drvdata *drvdata)
75 etmcr = etm_readl(drvdata, ETMCR);
76 etmcr &= ~ETMCR_PWD_DWN;
77 etm_writel(drvdata, etmcr, ETMCR);
78 /* Ensure pwrup completes before subsequent cp14 accesses */
83 static void etm_set_pwrup(struct etm_drvdata *drvdata)
87 etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
88 etmpdcr |= ETMPDCR_PWD_UP;
89 writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
90 /* Ensure pwrup completes before subsequent cp14 accesses */
95 static void etm_clr_pwrup(struct etm_drvdata *drvdata)
99 /* Ensure pending cp14 accesses complete before clearing pwrup */
102 etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
103 etmpdcr &= ~ETMPDCR_PWD_UP;
104 writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
108 * coresight_timeout_etm - loop until a bit has changed to a specific state.
109 * @drvdata: etm's private data structure.
110 * @offset: address of a register, starting from @addr.
111 * @position: the position of the bit of interest.
112 * @value: the value the bit should have.
114 * Basically the same as @coresight_timeout except for the register access
115 * method where we have to account for CP14 configurations.
117 * Return: 0 as soon as the bit has taken the desired state or -EAGAIN if
118 * TIMEOUT_US has elapsed, which ever happens first.
121 static int coresight_timeout_etm(struct etm_drvdata *drvdata, u32 offset,
122 int position, int value)
127 for (i = TIMEOUT_US; i > 0; i--) {
128 val = etm_readl(drvdata, offset);
129 /* Waiting on the bit to go from 0 to 1 */
131 if (val & BIT(position))
133 /* Waiting on the bit to go from 1 to 0 */
135 if (!(val & BIT(position)))
140 * Delay is arbitrary - the specification doesn't say how long
141 * we are expected to wait. Extra check required to make sure
142 * we don't wait needlessly on the last iteration.
152 static void etm_set_prog(struct etm_drvdata *drvdata)
156 etmcr = etm_readl(drvdata, ETMCR);
157 etmcr |= ETMCR_ETM_PRG;
158 etm_writel(drvdata, etmcr, ETMCR);
160 * Recommended by spec for cp14 accesses to ensure etmcr write is
161 * complete before polling etmsr
164 if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 1)) {
165 dev_err(drvdata->dev,
166 "%s: timeout observed when probing at offset %#x\n",
171 static void etm_clr_prog(struct etm_drvdata *drvdata)
175 etmcr = etm_readl(drvdata, ETMCR);
176 etmcr &= ~ETMCR_ETM_PRG;
177 etm_writel(drvdata, etmcr, ETMCR);
179 * Recommended by spec for cp14 accesses to ensure etmcr write is
180 * complete before polling etmsr
183 if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 0)) {
184 dev_err(drvdata->dev,
185 "%s: timeout observed when probing at offset %#x\n",
190 void etm_set_default(struct etm_config *config)
194 if (WARN_ON_ONCE(!config))
198 * Taken verbatim from the TRM:
200 * To trace all memory:
201 * set bit [24] in register 0x009, the ETMTECR1, to 1
202 * set all other bits in register 0x009, the ETMTECR1, to 0
203 * set all bits in register 0x007, the ETMTECR2, to 0
204 * set register 0x008, the ETMTEEVR, to 0x6F (TRUE).
206 config->enable_ctrl1 = BIT(24);
207 config->enable_ctrl2 = 0x0;
208 config->enable_event = ETM_HARD_WIRE_RES_A;
210 config->trigger_event = ETM_DEFAULT_EVENT_VAL;
211 config->enable_event = ETM_HARD_WIRE_RES_A;
213 config->seq_12_event = ETM_DEFAULT_EVENT_VAL;
214 config->seq_21_event = ETM_DEFAULT_EVENT_VAL;
215 config->seq_23_event = ETM_DEFAULT_EVENT_VAL;
216 config->seq_31_event = ETM_DEFAULT_EVENT_VAL;
217 config->seq_32_event = ETM_DEFAULT_EVENT_VAL;
218 config->seq_13_event = ETM_DEFAULT_EVENT_VAL;
219 config->timestamp_event = ETM_DEFAULT_EVENT_VAL;
221 for (i = 0; i < ETM_MAX_CNTR; i++) {
222 config->cntr_rld_val[i] = 0x0;
223 config->cntr_event[i] = ETM_DEFAULT_EVENT_VAL;
224 config->cntr_rld_event[i] = ETM_DEFAULT_EVENT_VAL;
225 config->cntr_val[i] = 0x0;
228 config->seq_curr_state = 0x0;
229 config->ctxid_idx = 0x0;
230 for (i = 0; i < ETM_MAX_CTXID_CMP; i++) {
231 config->ctxid_pid[i] = 0x0;
232 config->ctxid_vpid[i] = 0x0;
235 config->ctxid_mask = 0x0;
238 void etm_config_trace_mode(struct etm_config *config)
244 mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
246 /* excluding kernel AND user space doesn't make sense */
247 if (mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER))
250 /* nothing to do if neither flags are set */
251 if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
254 flags = (1 << 0 | /* instruction execute */
255 3 << 3 | /* ARM instruction */
256 0 << 5 | /* No data value comparison */
257 0 << 7 | /* No exact mach */
258 0 << 8); /* Ignore context ID */
260 /* No need to worry about single address comparators. */
261 config->enable_ctrl2 = 0x0;
263 /* Bit 0 is address range comparator 1 */
264 config->enable_ctrl1 = ETMTECR1_ADDR_COMP_1;
268 * ETMACTRn[13,11] == Non-secure state comparison control
269 * ETMACTRn[12,10] == Secure state comparison control
271 * b00 == Match in all modes in this state
272 * b01 == Do not match in any more in this state
273 * b10 == Match in all modes excepts user mode in this state
274 * b11 == Match only in user mode in this state
277 /* Tracing in secure mode is not supported at this time */
278 flags |= (0 << 12 | 1 << 10);
280 if (mode & ETM_MODE_EXCL_USER) {
281 /* exclude user, match all modes except user mode */
282 flags |= (1 << 13 | 0 << 11);
284 /* exclude kernel, match only in user mode */
285 flags |= (1 << 13 | 1 << 11);
289 * The ETMEEVR register is already set to "hard wire A". As such
290 * all there is to do is setup an address comparator that spans
291 * the entire address range and configure the state and mode bits.
293 config->addr_val[0] = (u32) 0x0;
294 config->addr_val[1] = (u32) ~0x0;
295 config->addr_acctype[0] = flags;
296 config->addr_acctype[1] = flags;
297 config->addr_type[0] = ETM_ADDR_TYPE_RANGE;
298 config->addr_type[1] = ETM_ADDR_TYPE_RANGE;
301 #define ETM3X_SUPPORTED_OPTIONS (ETMCR_CYC_ACC | ETMCR_TIMESTAMP_EN)
303 static int etm_parse_event_config(struct etm_drvdata *drvdata,
304 struct perf_event_attr *attr)
306 struct etm_config *config = &drvdata->config;
311 /* Clear configuration from previous run */
312 memset(config, 0, sizeof(struct etm_config));
314 if (attr->exclude_kernel)
315 config->mode = ETM_MODE_EXCL_KERN;
317 if (attr->exclude_user)
318 config->mode = ETM_MODE_EXCL_USER;
320 /* Always start from the default config */
321 etm_set_default(config);
324 * By default the tracers are configured to trace the whole address
325 * range. Narrow the field only if requested by user space.
328 etm_config_trace_mode(config);
331 * At this time only cycle accurate and timestamp options are
334 if (attr->config & ~ETM3X_SUPPORTED_OPTIONS)
337 config->ctrl = attr->config;
342 static void etm_enable_hw(void *info)
346 struct etm_drvdata *drvdata = info;
347 struct etm_config *config = &drvdata->config;
349 CS_UNLOCK(drvdata->base);
352 etm_clr_pwrdwn(drvdata);
353 /* Apply power to trace registers */
354 etm_set_pwrup(drvdata);
355 /* Make sure all registers are accessible */
356 etm_os_unlock(drvdata);
358 etm_set_prog(drvdata);
360 etmcr = etm_readl(drvdata, ETMCR);
361 /* Clear setting from a previous run if need be */
362 etmcr &= ~ETM3X_SUPPORTED_OPTIONS;
363 etmcr |= drvdata->port_size;
364 etmcr |= ETMCR_ETM_EN;
365 etm_writel(drvdata, config->ctrl | etmcr, ETMCR);
366 etm_writel(drvdata, config->trigger_event, ETMTRIGGER);
367 etm_writel(drvdata, config->startstop_ctrl, ETMTSSCR);
368 etm_writel(drvdata, config->enable_event, ETMTEEVR);
369 etm_writel(drvdata, config->enable_ctrl1, ETMTECR1);
370 etm_writel(drvdata, config->fifofull_level, ETMFFLR);
371 for (i = 0; i < drvdata->nr_addr_cmp; i++) {
372 etm_writel(drvdata, config->addr_val[i], ETMACVRn(i));
373 etm_writel(drvdata, config->addr_acctype[i], ETMACTRn(i));
375 for (i = 0; i < drvdata->nr_cntr; i++) {
376 etm_writel(drvdata, config->cntr_rld_val[i], ETMCNTRLDVRn(i));
377 etm_writel(drvdata, config->cntr_event[i], ETMCNTENRn(i));
378 etm_writel(drvdata, config->cntr_rld_event[i],
380 etm_writel(drvdata, config->cntr_val[i], ETMCNTVRn(i));
382 etm_writel(drvdata, config->seq_12_event, ETMSQ12EVR);
383 etm_writel(drvdata, config->seq_21_event, ETMSQ21EVR);
384 etm_writel(drvdata, config->seq_23_event, ETMSQ23EVR);
385 etm_writel(drvdata, config->seq_31_event, ETMSQ31EVR);
386 etm_writel(drvdata, config->seq_32_event, ETMSQ32EVR);
387 etm_writel(drvdata, config->seq_13_event, ETMSQ13EVR);
388 etm_writel(drvdata, config->seq_curr_state, ETMSQR);
389 for (i = 0; i < drvdata->nr_ext_out; i++)
390 etm_writel(drvdata, ETM_DEFAULT_EVENT_VAL, ETMEXTOUTEVRn(i));
391 for (i = 0; i < drvdata->nr_ctxid_cmp; i++)
392 etm_writel(drvdata, config->ctxid_pid[i], ETMCIDCVRn(i));
393 etm_writel(drvdata, config->ctxid_mask, ETMCIDCMR);
394 etm_writel(drvdata, config->sync_freq, ETMSYNCFR);
395 /* No external input selected */
396 etm_writel(drvdata, 0x0, ETMEXTINSELR);
397 etm_writel(drvdata, config->timestamp_event, ETMTSEVR);
398 /* No auxiliary control selected */
399 etm_writel(drvdata, 0x0, ETMAUXCR);
400 etm_writel(drvdata, drvdata->traceid, ETMTRACEIDR);
401 /* No VMID comparator value selected */
402 etm_writel(drvdata, 0x0, ETMVMIDCVR);
404 etm_clr_prog(drvdata);
405 CS_LOCK(drvdata->base);
407 dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
410 static int etm_cpu_id(struct coresight_device *csdev)
412 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
417 int etm_get_trace_id(struct etm_drvdata *drvdata)
425 if (!local_read(&drvdata->mode))
426 return drvdata->traceid;
428 pm_runtime_get_sync(drvdata->dev);
430 spin_lock_irqsave(&drvdata->spinlock, flags);
432 CS_UNLOCK(drvdata->base);
433 trace_id = (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK);
434 CS_LOCK(drvdata->base);
436 spin_unlock_irqrestore(&drvdata->spinlock, flags);
437 pm_runtime_put(drvdata->dev);
444 static int etm_trace_id(struct coresight_device *csdev)
446 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
448 return etm_get_trace_id(drvdata);
451 static int etm_enable_perf(struct coresight_device *csdev,
452 struct perf_event_attr *attr)
454 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
456 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
459 /* Configure the tracer based on the session's specifics */
460 etm_parse_event_config(drvdata, attr);
462 etm_enable_hw(drvdata);
467 static int etm_enable_sysfs(struct coresight_device *csdev)
469 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
472 spin_lock(&drvdata->spinlock);
475 * Configure the ETM only if the CPU is online. If it isn't online
476 * hw configuration will take place when 'CPU_STARTING' is received
477 * in @etm_cpu_callback.
479 if (cpu_online(drvdata->cpu)) {
480 ret = smp_call_function_single(drvdata->cpu,
481 etm_enable_hw, drvdata, 1);
486 drvdata->sticky_enable = true;
487 spin_unlock(&drvdata->spinlock);
489 dev_info(drvdata->dev, "ETM tracing enabled\n");
493 spin_unlock(&drvdata->spinlock);
497 static int etm_enable(struct coresight_device *csdev,
498 struct perf_event_attr *attr, u32 mode)
502 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
504 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
506 /* Someone is already using the tracer */
512 ret = etm_enable_sysfs(csdev);
515 ret = etm_enable_perf(csdev, attr);
521 /* The tracer didn't start */
523 local_set(&drvdata->mode, CS_MODE_DISABLED);
528 static void etm_disable_hw(void *info)
531 struct etm_drvdata *drvdata = info;
532 struct etm_config *config = &drvdata->config;
534 CS_UNLOCK(drvdata->base);
535 etm_set_prog(drvdata);
537 /* Read back sequencer and counters for post trace analysis */
538 config->seq_curr_state = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
540 for (i = 0; i < drvdata->nr_cntr; i++)
541 config->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i));
543 etm_set_pwrdwn(drvdata);
544 CS_LOCK(drvdata->base);
546 dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
549 static void etm_disable_perf(struct coresight_device *csdev)
551 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
553 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
556 CS_UNLOCK(drvdata->base);
558 /* Setting the prog bit disables tracing immediately */
559 etm_set_prog(drvdata);
562 * There is no way to know when the tracer will be used again so
563 * power down the tracer.
565 etm_set_pwrdwn(drvdata);
567 CS_LOCK(drvdata->base);
570 static void etm_disable_sysfs(struct coresight_device *csdev)
572 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
575 * Taking hotplug lock here protects from clocks getting disabled
576 * with tracing being left on (crash scenario) if user disable occurs
577 * after cpu online mask indicates the cpu is offline but before the
578 * DYING hotplug callback is serviced by the ETM driver.
581 spin_lock(&drvdata->spinlock);
584 * Executing etm_disable_hw on the cpu whose ETM is being disabled
585 * ensures that register writes occur when cpu is powered.
587 smp_call_function_single(drvdata->cpu, etm_disable_hw, drvdata, 1);
589 spin_unlock(&drvdata->spinlock);
592 dev_info(drvdata->dev, "ETM tracing disabled\n");
595 static void etm_disable(struct coresight_device *csdev)
598 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
601 * For as long as the tracer isn't disabled another entity can't
602 * change its status. As such we can read the status here without
603 * fearing it will change under us.
605 mode = local_read(&drvdata->mode);
608 case CS_MODE_DISABLED:
611 etm_disable_sysfs(csdev);
614 etm_disable_perf(csdev);
622 local_set(&drvdata->mode, CS_MODE_DISABLED);
625 static const struct coresight_ops_source etm_source_ops = {
626 .cpu_id = etm_cpu_id,
627 .trace_id = etm_trace_id,
628 .enable = etm_enable,
629 .disable = etm_disable,
632 static const struct coresight_ops etm_cs_ops = {
633 .source_ops = &etm_source_ops,
636 static int etm_cpu_callback(struct notifier_block *nfb, unsigned long action,
639 unsigned int cpu = (unsigned long)hcpu;
641 if (!etmdrvdata[cpu])
644 switch (action & (~CPU_TASKS_FROZEN)) {
646 spin_lock(&etmdrvdata[cpu]->spinlock);
647 if (!etmdrvdata[cpu]->os_unlock) {
648 etm_os_unlock(etmdrvdata[cpu]);
649 etmdrvdata[cpu]->os_unlock = true;
652 if (local_read(&etmdrvdata[cpu]->mode))
653 etm_enable_hw(etmdrvdata[cpu]);
654 spin_unlock(&etmdrvdata[cpu]->spinlock);
658 if (etmdrvdata[cpu]->boot_enable &&
659 !etmdrvdata[cpu]->sticky_enable)
660 coresight_enable(etmdrvdata[cpu]->csdev);
664 spin_lock(&etmdrvdata[cpu]->spinlock);
665 if (local_read(&etmdrvdata[cpu]->mode))
666 etm_disable_hw(etmdrvdata[cpu]);
667 spin_unlock(&etmdrvdata[cpu]->spinlock);
674 static struct notifier_block etm_cpu_notifier = {
675 .notifier_call = etm_cpu_callback,
678 static bool etm_arch_supported(u8 arch)
695 static void etm_init_arch_data(void *info)
699 struct etm_drvdata *drvdata = info;
701 /* Make sure all registers are accessible */
702 etm_os_unlock(drvdata);
704 CS_UNLOCK(drvdata->base);
706 /* First dummy read */
707 (void)etm_readl(drvdata, ETMPDSR);
708 /* Provide power to ETM: ETMPDCR[3] == 1 */
709 etm_set_pwrup(drvdata);
711 * Clear power down bit since when this bit is set writes to
712 * certain registers might be ignored.
714 etm_clr_pwrdwn(drvdata);
716 * Set prog bit. It will be set from reset but this is included to
719 etm_set_prog(drvdata);
721 /* Find all capabilities */
722 etmidr = etm_readl(drvdata, ETMIDR);
723 drvdata->arch = BMVAL(etmidr, 4, 11);
724 drvdata->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK;
726 drvdata->etmccer = etm_readl(drvdata, ETMCCER);
727 etmccr = etm_readl(drvdata, ETMCCR);
728 drvdata->etmccr = etmccr;
729 drvdata->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
730 drvdata->nr_cntr = BMVAL(etmccr, 13, 15);
731 drvdata->nr_ext_inp = BMVAL(etmccr, 17, 19);
732 drvdata->nr_ext_out = BMVAL(etmccr, 20, 22);
733 drvdata->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
735 etm_set_pwrdwn(drvdata);
736 etm_clr_pwrup(drvdata);
737 CS_LOCK(drvdata->base);
740 static void etm_init_trace_id(struct etm_drvdata *drvdata)
743 * A trace ID of value 0 is invalid, so let's start at some
744 * random value that fits in 7 bits and go from there.
746 drvdata->traceid = 0x10 + drvdata->cpu;
749 static int etm_probe(struct amba_device *adev, const struct amba_id *id)
753 struct device *dev = &adev->dev;
754 struct coresight_platform_data *pdata = NULL;
755 struct etm_drvdata *drvdata;
756 struct resource *res = &adev->res;
757 struct coresight_desc *desc;
758 struct device_node *np = adev->dev.of_node;
760 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
764 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
769 pdata = of_get_coresight_platform_data(dev, np);
771 return PTR_ERR(pdata);
773 adev->dev.platform_data = pdata;
774 drvdata->use_cp14 = of_property_read_bool(np, "arm,cp14");
777 drvdata->dev = &adev->dev;
778 dev_set_drvdata(dev, drvdata);
780 /* Validity for the resource is already checked by the AMBA core */
781 base = devm_ioremap_resource(dev, res);
783 return PTR_ERR(base);
785 drvdata->base = base;
787 spin_lock_init(&drvdata->spinlock);
789 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
790 if (!IS_ERR(drvdata->atclk)) {
791 ret = clk_prepare_enable(drvdata->atclk);
796 drvdata->cpu = pdata ? pdata->cpu : 0;
799 etmdrvdata[drvdata->cpu] = drvdata;
801 if (smp_call_function_single(drvdata->cpu,
802 etm_init_arch_data, drvdata, 1))
803 dev_err(dev, "ETM arch init failed\n");
806 register_hotcpu_notifier(&etm_cpu_notifier);
810 if (etm_arch_supported(drvdata->arch) == false) {
812 goto err_arch_supported;
815 etm_init_trace_id(drvdata);
816 etm_set_default(&drvdata->config);
818 desc->type = CORESIGHT_DEV_TYPE_SOURCE;
819 desc->subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
820 desc->ops = &etm_cs_ops;
823 desc->groups = coresight_etm_groups;
824 drvdata->csdev = coresight_register(desc);
825 if (IS_ERR(drvdata->csdev)) {
826 ret = PTR_ERR(drvdata->csdev);
827 goto err_arch_supported;
830 pm_runtime_put(&adev->dev);
831 dev_info(dev, "%s initialized\n", (char *)id->data);
834 coresight_enable(drvdata->csdev);
835 drvdata->boot_enable = true;
841 if (--etm_count == 0)
842 unregister_hotcpu_notifier(&etm_cpu_notifier);
847 static int etm_runtime_suspend(struct device *dev)
849 struct etm_drvdata *drvdata = dev_get_drvdata(dev);
851 if (drvdata && !IS_ERR(drvdata->atclk))
852 clk_disable_unprepare(drvdata->atclk);
857 static int etm_runtime_resume(struct device *dev)
859 struct etm_drvdata *drvdata = dev_get_drvdata(dev);
861 if (drvdata && !IS_ERR(drvdata->atclk))
862 clk_prepare_enable(drvdata->atclk);
868 static const struct dev_pm_ops etm_dev_pm_ops = {
869 SET_RUNTIME_PM_OPS(etm_runtime_suspend, etm_runtime_resume, NULL)
872 static struct amba_id etm_ids[] = {
893 { /* PTM 1.1 Qualcomm */
901 static struct amba_driver etm_driver = {
903 .name = "coresight-etm3x",
904 .owner = THIS_MODULE,
905 .pm = &etm_dev_pm_ops,
906 .suppress_bind_attrs = true,
912 module_amba_driver(etm_driver);
914 MODULE_LICENSE("GPL v2");
915 MODULE_DESCRIPTION("CoreSight Program Flow Trace driver");