1 /* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/types.h>
17 #include <linux/device.h>
19 #include <linux/err.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/smp.h>
24 #include <linux/sysfs.h>
25 #include <linux/stat.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/cpu.h>
29 #include <linux/coresight.h>
30 #include <linux/amba/bus.h>
31 #include <linux/seq_file.h>
32 #include <linux/uaccess.h>
33 #include <linux/clk.h>
34 #include <asm/sections.h>
36 #include "coresight-etm.h"
38 static int boot_enable;
39 module_param_named(boot_enable, boot_enable, int, S_IRUGO);
41 /* The number of ETM/PTM currently registered */
43 static struct etm_drvdata *etmdrvdata[NR_CPUS];
44 static void etm_init_default_data(struct etm_config *config);
47 * Memory mapped writes to clear os lock are not supported on some processors
48 * and OS lock must be unlocked before any memory mapped access on such
49 * processors, otherwise memory mapped reads/writes will be invalid.
51 static void etm_os_unlock(struct etm_drvdata *drvdata)
53 /* Writing any value to ETMOSLAR unlocks the trace registers */
54 etm_writel(drvdata, 0x0, ETMOSLAR);
55 drvdata->os_unlock = true;
59 static void etm_set_pwrdwn(struct etm_drvdata *drvdata)
63 /* Ensure pending cp14 accesses complete before setting pwrdwn */
66 etmcr = etm_readl(drvdata, ETMCR);
67 etmcr |= ETMCR_PWD_DWN;
68 etm_writel(drvdata, etmcr, ETMCR);
71 static void etm_clr_pwrdwn(struct etm_drvdata *drvdata)
75 etmcr = etm_readl(drvdata, ETMCR);
76 etmcr &= ~ETMCR_PWD_DWN;
77 etm_writel(drvdata, etmcr, ETMCR);
78 /* Ensure pwrup completes before subsequent cp14 accesses */
83 static void etm_set_pwrup(struct etm_drvdata *drvdata)
87 etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
88 etmpdcr |= ETMPDCR_PWD_UP;
89 writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
90 /* Ensure pwrup completes before subsequent cp14 accesses */
95 static void etm_clr_pwrup(struct etm_drvdata *drvdata)
99 /* Ensure pending cp14 accesses complete before clearing pwrup */
102 etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
103 etmpdcr &= ~ETMPDCR_PWD_UP;
104 writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
108 * coresight_timeout_etm - loop until a bit has changed to a specific state.
109 * @drvdata: etm's private data structure.
110 * @offset: address of a register, starting from @addr.
111 * @position: the position of the bit of interest.
112 * @value: the value the bit should have.
114 * Basically the same as @coresight_timeout except for the register access
115 * method where we have to account for CP14 configurations.
117 * Return: 0 as soon as the bit has taken the desired state or -EAGAIN if
118 * TIMEOUT_US has elapsed, which ever happens first.
121 static int coresight_timeout_etm(struct etm_drvdata *drvdata, u32 offset,
122 int position, int value)
127 for (i = TIMEOUT_US; i > 0; i--) {
128 val = etm_readl(drvdata, offset);
129 /* Waiting on the bit to go from 0 to 1 */
131 if (val & BIT(position))
133 /* Waiting on the bit to go from 1 to 0 */
135 if (!(val & BIT(position)))
140 * Delay is arbitrary - the specification doesn't say how long
141 * we are expected to wait. Extra check required to make sure
142 * we don't wait needlessly on the last iteration.
152 static void etm_set_prog(struct etm_drvdata *drvdata)
156 etmcr = etm_readl(drvdata, ETMCR);
157 etmcr |= ETMCR_ETM_PRG;
158 etm_writel(drvdata, etmcr, ETMCR);
160 * Recommended by spec for cp14 accesses to ensure etmcr write is
161 * complete before polling etmsr
164 if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 1)) {
165 dev_err(drvdata->dev,
166 "%s: timeout observed when probing at offset %#x\n",
171 static void etm_clr_prog(struct etm_drvdata *drvdata)
175 etmcr = etm_readl(drvdata, ETMCR);
176 etmcr &= ~ETMCR_ETM_PRG;
177 etm_writel(drvdata, etmcr, ETMCR);
179 * Recommended by spec for cp14 accesses to ensure etmcr write is
180 * complete before polling etmsr
183 if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 0)) {
184 dev_err(drvdata->dev,
185 "%s: timeout observed when probing at offset %#x\n",
190 void etm_set_default(struct etm_config *config)
194 if (WARN_ON_ONCE(!config))
197 config->trigger_event = ETM_DEFAULT_EVENT_VAL;
198 config->enable_event = ETM_HARD_WIRE_RES_A;
200 config->seq_12_event = ETM_DEFAULT_EVENT_VAL;
201 config->seq_21_event = ETM_DEFAULT_EVENT_VAL;
202 config->seq_23_event = ETM_DEFAULT_EVENT_VAL;
203 config->seq_31_event = ETM_DEFAULT_EVENT_VAL;
204 config->seq_32_event = ETM_DEFAULT_EVENT_VAL;
205 config->seq_13_event = ETM_DEFAULT_EVENT_VAL;
206 config->timestamp_event = ETM_DEFAULT_EVENT_VAL;
208 for (i = 0; i < ETM_MAX_CNTR; i++) {
209 config->cntr_rld_val[i] = 0x0;
210 config->cntr_event[i] = ETM_DEFAULT_EVENT_VAL;
211 config->cntr_rld_event[i] = ETM_DEFAULT_EVENT_VAL;
212 config->cntr_val[i] = 0x0;
215 config->seq_curr_state = 0x0;
216 config->ctxid_idx = 0x0;
217 for (i = 0; i < ETM_MAX_CTXID_CMP; i++) {
218 config->ctxid_pid[i] = 0x0;
219 config->ctxid_vpid[i] = 0x0;
222 config->ctxid_mask = 0x0;
225 static void etm_enable_hw(void *info)
229 struct etm_drvdata *drvdata = info;
230 struct etm_config *config = &drvdata->config;
232 CS_UNLOCK(drvdata->base);
235 etm_clr_pwrdwn(drvdata);
236 /* Apply power to trace registers */
237 etm_set_pwrup(drvdata);
238 /* Make sure all registers are accessible */
239 etm_os_unlock(drvdata);
241 etm_set_prog(drvdata);
243 etmcr = etm_readl(drvdata, ETMCR);
244 etmcr &= (ETMCR_PWD_DWN | ETMCR_ETM_PRG);
245 etmcr |= drvdata->port_size;
246 etm_writel(drvdata, config->ctrl | etmcr, ETMCR);
247 etm_writel(drvdata, config->trigger_event, ETMTRIGGER);
248 etm_writel(drvdata, config->startstop_ctrl, ETMTSSCR);
249 etm_writel(drvdata, config->enable_event, ETMTEEVR);
250 etm_writel(drvdata, config->enable_ctrl1, ETMTECR1);
251 etm_writel(drvdata, config->fifofull_level, ETMFFLR);
252 for (i = 0; i < drvdata->nr_addr_cmp; i++) {
253 etm_writel(drvdata, config->addr_val[i], ETMACVRn(i));
254 etm_writel(drvdata, config->addr_acctype[i], ETMACTRn(i));
256 for (i = 0; i < drvdata->nr_cntr; i++) {
257 etm_writel(drvdata, config->cntr_rld_val[i], ETMCNTRLDVRn(i));
258 etm_writel(drvdata, config->cntr_event[i], ETMCNTENRn(i));
259 etm_writel(drvdata, config->cntr_rld_event[i],
261 etm_writel(drvdata, config->cntr_val[i], ETMCNTVRn(i));
263 etm_writel(drvdata, config->seq_12_event, ETMSQ12EVR);
264 etm_writel(drvdata, config->seq_21_event, ETMSQ21EVR);
265 etm_writel(drvdata, config->seq_23_event, ETMSQ23EVR);
266 etm_writel(drvdata, config->seq_31_event, ETMSQ31EVR);
267 etm_writel(drvdata, config->seq_32_event, ETMSQ32EVR);
268 etm_writel(drvdata, config->seq_13_event, ETMSQ13EVR);
269 etm_writel(drvdata, config->seq_curr_state, ETMSQR);
270 for (i = 0; i < drvdata->nr_ext_out; i++)
271 etm_writel(drvdata, ETM_DEFAULT_EVENT_VAL, ETMEXTOUTEVRn(i));
272 for (i = 0; i < drvdata->nr_ctxid_cmp; i++)
273 etm_writel(drvdata, config->ctxid_pid[i], ETMCIDCVRn(i));
274 etm_writel(drvdata, config->ctxid_mask, ETMCIDCMR);
275 etm_writel(drvdata, config->sync_freq, ETMSYNCFR);
276 /* No external input selected */
277 etm_writel(drvdata, 0x0, ETMEXTINSELR);
278 etm_writel(drvdata, config->timestamp_event, ETMTSEVR);
279 /* No auxiliary control selected */
280 etm_writel(drvdata, 0x0, ETMAUXCR);
281 etm_writel(drvdata, drvdata->traceid, ETMTRACEIDR);
282 /* No VMID comparator value selected */
283 etm_writel(drvdata, 0x0, ETMVMIDCVR);
285 /* Ensures trace output is enabled from this ETM */
286 etm_writel(drvdata, config->ctrl | ETMCR_ETM_EN | etmcr, ETMCR);
288 etm_clr_prog(drvdata);
289 CS_LOCK(drvdata->base);
291 dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
294 static int etm_cpu_id(struct coresight_device *csdev)
296 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
301 int etm_get_trace_id(struct etm_drvdata *drvdata)
309 if (!local_read(&drvdata->mode))
310 return drvdata->traceid;
312 pm_runtime_get_sync(drvdata->dev);
314 spin_lock_irqsave(&drvdata->spinlock, flags);
316 CS_UNLOCK(drvdata->base);
317 trace_id = (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK);
318 CS_LOCK(drvdata->base);
320 spin_unlock_irqrestore(&drvdata->spinlock, flags);
321 pm_runtime_put(drvdata->dev);
328 static int etm_trace_id(struct coresight_device *csdev)
330 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
332 return etm_get_trace_id(drvdata);
335 static int etm_enable_sysfs(struct coresight_device *csdev)
337 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
340 spin_lock(&drvdata->spinlock);
343 * Configure the ETM only if the CPU is online. If it isn't online
344 * hw configuration will take place when 'CPU_STARTING' is received
345 * in @etm_cpu_callback.
347 if (cpu_online(drvdata->cpu)) {
348 ret = smp_call_function_single(drvdata->cpu,
349 etm_enable_hw, drvdata, 1);
354 drvdata->sticky_enable = true;
355 spin_unlock(&drvdata->spinlock);
357 dev_info(drvdata->dev, "ETM tracing enabled\n");
361 spin_unlock(&drvdata->spinlock);
365 static int etm_enable(struct coresight_device *csdev, u32 mode)
369 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
371 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
373 /* Someone is already using the tracer */
379 ret = etm_enable_sysfs(csdev);
385 /* The tracer didn't start */
387 local_set(&drvdata->mode, CS_MODE_DISABLED);
392 static void etm_disable_hw(void *info)
395 struct etm_drvdata *drvdata = info;
396 struct etm_config *config = &drvdata->config;
398 CS_UNLOCK(drvdata->base);
399 etm_set_prog(drvdata);
401 /* Read back sequencer and counters for post trace analysis */
402 config->seq_curr_state = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
404 for (i = 0; i < drvdata->nr_cntr; i++)
405 config->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i));
407 etm_set_pwrdwn(drvdata);
408 CS_LOCK(drvdata->base);
410 dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
413 static void etm_disable_sysfs(struct coresight_device *csdev)
415 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
418 * Taking hotplug lock here protects from clocks getting disabled
419 * with tracing being left on (crash scenario) if user disable occurs
420 * after cpu online mask indicates the cpu is offline but before the
421 * DYING hotplug callback is serviced by the ETM driver.
424 spin_lock(&drvdata->spinlock);
427 * Executing etm_disable_hw on the cpu whose ETM is being disabled
428 * ensures that register writes occur when cpu is powered.
430 smp_call_function_single(drvdata->cpu, etm_disable_hw, drvdata, 1);
432 spin_unlock(&drvdata->spinlock);
435 dev_info(drvdata->dev, "ETM tracing disabled\n");
438 static void etm_disable(struct coresight_device *csdev)
441 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
444 * For as long as the tracer isn't disabled another entity can't
445 * change its status. As such we can read the status here without
446 * fearing it will change under us.
448 mode = local_read(&drvdata->mode);
451 case CS_MODE_DISABLED:
454 etm_disable_sysfs(csdev);
462 local_set(&drvdata->mode, CS_MODE_DISABLED);
465 static const struct coresight_ops_source etm_source_ops = {
466 .cpu_id = etm_cpu_id,
467 .trace_id = etm_trace_id,
468 .enable = etm_enable,
469 .disable = etm_disable,
472 static const struct coresight_ops etm_cs_ops = {
473 .source_ops = &etm_source_ops,
476 static int etm_cpu_callback(struct notifier_block *nfb, unsigned long action,
479 unsigned int cpu = (unsigned long)hcpu;
481 if (!etmdrvdata[cpu])
484 switch (action & (~CPU_TASKS_FROZEN)) {
486 spin_lock(&etmdrvdata[cpu]->spinlock);
487 if (!etmdrvdata[cpu]->os_unlock) {
488 etm_os_unlock(etmdrvdata[cpu]);
489 etmdrvdata[cpu]->os_unlock = true;
492 if (local_read(&etmdrvdata[cpu]->mode))
493 etm_enable_hw(etmdrvdata[cpu]);
494 spin_unlock(&etmdrvdata[cpu]->spinlock);
498 if (etmdrvdata[cpu]->boot_enable &&
499 !etmdrvdata[cpu]->sticky_enable)
500 coresight_enable(etmdrvdata[cpu]->csdev);
504 spin_lock(&etmdrvdata[cpu]->spinlock);
505 if (local_read(&etmdrvdata[cpu]->mode))
506 etm_disable_hw(etmdrvdata[cpu]);
507 spin_unlock(&etmdrvdata[cpu]->spinlock);
514 static struct notifier_block etm_cpu_notifier = {
515 .notifier_call = etm_cpu_callback,
518 static bool etm_arch_supported(u8 arch)
535 static void etm_init_arch_data(void *info)
539 struct etm_drvdata *drvdata = info;
541 /* Make sure all registers are accessible */
542 etm_os_unlock(drvdata);
544 CS_UNLOCK(drvdata->base);
546 /* First dummy read */
547 (void)etm_readl(drvdata, ETMPDSR);
548 /* Provide power to ETM: ETMPDCR[3] == 1 */
549 etm_set_pwrup(drvdata);
551 * Clear power down bit since when this bit is set writes to
552 * certain registers might be ignored.
554 etm_clr_pwrdwn(drvdata);
556 * Set prog bit. It will be set from reset but this is included to
559 etm_set_prog(drvdata);
561 /* Find all capabilities */
562 etmidr = etm_readl(drvdata, ETMIDR);
563 drvdata->arch = BMVAL(etmidr, 4, 11);
564 drvdata->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK;
566 drvdata->etmccer = etm_readl(drvdata, ETMCCER);
567 etmccr = etm_readl(drvdata, ETMCCR);
568 drvdata->etmccr = etmccr;
569 drvdata->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
570 drvdata->nr_cntr = BMVAL(etmccr, 13, 15);
571 drvdata->nr_ext_inp = BMVAL(etmccr, 17, 19);
572 drvdata->nr_ext_out = BMVAL(etmccr, 20, 22);
573 drvdata->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
575 etm_set_pwrdwn(drvdata);
576 etm_clr_pwrup(drvdata);
577 CS_LOCK(drvdata->base);
580 static void etm_init_default_data(struct etm_config *config)
582 u32 flags = (1 << 0 | /* instruction execute*/
583 3 << 3 | /* ARM instruction */
584 0 << 5 | /* No data value comparison */
585 0 << 7 | /* No exact mach */
586 0 << 8 | /* Ignore context ID */
587 0 << 10); /* Security ignored */
589 if (WARN_ON_ONCE(!config))
592 config->ctrl = (ETMCR_CYC_ACC | ETMCR_TIMESTAMP_EN);
593 config->enable_ctrl1 = ETMTECR1_ADDR_COMP_1;
594 config->addr_val[0] = (u32) _stext;
595 config->addr_val[1] = (u32) _etext;
596 config->addr_acctype[0] = flags;
597 config->addr_acctype[1] = flags;
598 config->addr_type[0] = ETM_ADDR_TYPE_RANGE;
599 config->addr_type[1] = ETM_ADDR_TYPE_RANGE;
601 etm_set_default(config);
604 static void etm_init_trace_id(struct etm_drvdata *drvdata)
607 * A trace ID of value 0 is invalid, so let's start at some
608 * random value that fits in 7 bits and go from there.
610 drvdata->traceid = 0x10 + drvdata->cpu;
613 static int etm_probe(struct amba_device *adev, const struct amba_id *id)
617 struct device *dev = &adev->dev;
618 struct coresight_platform_data *pdata = NULL;
619 struct etm_drvdata *drvdata;
620 struct resource *res = &adev->res;
621 struct coresight_desc *desc;
622 struct device_node *np = adev->dev.of_node;
624 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
628 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
633 pdata = of_get_coresight_platform_data(dev, np);
635 return PTR_ERR(pdata);
637 adev->dev.platform_data = pdata;
638 drvdata->use_cp14 = of_property_read_bool(np, "arm,cp14");
641 drvdata->dev = &adev->dev;
642 dev_set_drvdata(dev, drvdata);
644 /* Validity for the resource is already checked by the AMBA core */
645 base = devm_ioremap_resource(dev, res);
647 return PTR_ERR(base);
649 drvdata->base = base;
651 spin_lock_init(&drvdata->spinlock);
653 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
654 if (!IS_ERR(drvdata->atclk)) {
655 ret = clk_prepare_enable(drvdata->atclk);
660 drvdata->cpu = pdata ? pdata->cpu : 0;
663 etmdrvdata[drvdata->cpu] = drvdata;
665 if (smp_call_function_single(drvdata->cpu,
666 etm_init_arch_data, drvdata, 1))
667 dev_err(dev, "ETM arch init failed\n");
670 register_hotcpu_notifier(&etm_cpu_notifier);
674 if (etm_arch_supported(drvdata->arch) == false) {
676 goto err_arch_supported;
679 etm_init_trace_id(drvdata);
680 etm_init_default_data(&drvdata->config);
682 desc->type = CORESIGHT_DEV_TYPE_SOURCE;
683 desc->subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
684 desc->ops = &etm_cs_ops;
687 desc->groups = coresight_etm_groups;
688 drvdata->csdev = coresight_register(desc);
689 if (IS_ERR(drvdata->csdev)) {
690 ret = PTR_ERR(drvdata->csdev);
691 goto err_arch_supported;
694 pm_runtime_put(&adev->dev);
695 dev_info(dev, "%s initialized\n", (char *)id->data);
698 coresight_enable(drvdata->csdev);
699 drvdata->boot_enable = true;
705 if (--etm_count == 0)
706 unregister_hotcpu_notifier(&etm_cpu_notifier);
711 static int etm_runtime_suspend(struct device *dev)
713 struct etm_drvdata *drvdata = dev_get_drvdata(dev);
715 if (drvdata && !IS_ERR(drvdata->atclk))
716 clk_disable_unprepare(drvdata->atclk);
721 static int etm_runtime_resume(struct device *dev)
723 struct etm_drvdata *drvdata = dev_get_drvdata(dev);
725 if (drvdata && !IS_ERR(drvdata->atclk))
726 clk_prepare_enable(drvdata->atclk);
732 static const struct dev_pm_ops etm_dev_pm_ops = {
733 SET_RUNTIME_PM_OPS(etm_runtime_suspend, etm_runtime_resume, NULL)
736 static struct amba_id etm_ids[] = {
757 { /* PTM 1.1 Qualcomm */
765 static struct amba_driver etm_driver = {
767 .name = "coresight-etm3x",
768 .owner = THIS_MODULE,
769 .pm = &etm_dev_pm_ops,
770 .suppress_bind_attrs = true,
776 module_amba_driver(etm_driver);
778 MODULE_LICENSE("GPL v2");
779 MODULE_DESCRIPTION("CoreSight Program Flow Trace driver");