1 /* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/types.h>
17 #include <linux/device.h>
19 #include <linux/err.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/smp.h>
24 #include <linux/sysfs.h>
25 #include <linux/stat.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/cpu.h>
29 #include <linux/coresight.h>
30 #include <linux/coresight-pmu.h>
31 #include <linux/amba/bus.h>
32 #include <linux/seq_file.h>
33 #include <linux/uaccess.h>
34 #include <linux/clk.h>
35 #include <linux/perf_event.h>
36 #include <asm/sections.h>
38 #include "coresight-etm.h"
39 #include "coresight-etm-perf.h"
41 static int boot_enable;
42 module_param_named(boot_enable, boot_enable, int, S_IRUGO);
44 /* The number of ETM/PTM currently registered */
46 static struct etm_drvdata *etmdrvdata[NR_CPUS];
49 * Memory mapped writes to clear os lock are not supported on some processors
50 * and OS lock must be unlocked before any memory mapped access on such
51 * processors, otherwise memory mapped reads/writes will be invalid.
53 static void etm_os_unlock(struct etm_drvdata *drvdata)
55 /* Writing any value to ETMOSLAR unlocks the trace registers */
56 etm_writel(drvdata, 0x0, ETMOSLAR);
57 drvdata->os_unlock = true;
61 static void etm_set_pwrdwn(struct etm_drvdata *drvdata)
65 /* Ensure pending cp14 accesses complete before setting pwrdwn */
68 etmcr = etm_readl(drvdata, ETMCR);
69 etmcr |= ETMCR_PWD_DWN;
70 etm_writel(drvdata, etmcr, ETMCR);
73 static void etm_clr_pwrdwn(struct etm_drvdata *drvdata)
77 etmcr = etm_readl(drvdata, ETMCR);
78 etmcr &= ~ETMCR_PWD_DWN;
79 etm_writel(drvdata, etmcr, ETMCR);
80 /* Ensure pwrup completes before subsequent cp14 accesses */
85 static void etm_set_pwrup(struct etm_drvdata *drvdata)
89 etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
90 etmpdcr |= ETMPDCR_PWD_UP;
91 writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
92 /* Ensure pwrup completes before subsequent cp14 accesses */
97 static void etm_clr_pwrup(struct etm_drvdata *drvdata)
101 /* Ensure pending cp14 accesses complete before clearing pwrup */
104 etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
105 etmpdcr &= ~ETMPDCR_PWD_UP;
106 writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
110 * coresight_timeout_etm - loop until a bit has changed to a specific state.
111 * @drvdata: etm's private data structure.
112 * @offset: address of a register, starting from @addr.
113 * @position: the position of the bit of interest.
114 * @value: the value the bit should have.
116 * Basically the same as @coresight_timeout except for the register access
117 * method where we have to account for CP14 configurations.
119 * Return: 0 as soon as the bit has taken the desired state or -EAGAIN if
120 * TIMEOUT_US has elapsed, which ever happens first.
123 static int coresight_timeout_etm(struct etm_drvdata *drvdata, u32 offset,
124 int position, int value)
129 for (i = TIMEOUT_US; i > 0; i--) {
130 val = etm_readl(drvdata, offset);
131 /* Waiting on the bit to go from 0 to 1 */
133 if (val & BIT(position))
135 /* Waiting on the bit to go from 1 to 0 */
137 if (!(val & BIT(position)))
142 * Delay is arbitrary - the specification doesn't say how long
143 * we are expected to wait. Extra check required to make sure
144 * we don't wait needlessly on the last iteration.
154 static void etm_set_prog(struct etm_drvdata *drvdata)
158 etmcr = etm_readl(drvdata, ETMCR);
159 etmcr |= ETMCR_ETM_PRG;
160 etm_writel(drvdata, etmcr, ETMCR);
162 * Recommended by spec for cp14 accesses to ensure etmcr write is
163 * complete before polling etmsr
166 if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 1)) {
167 dev_err(drvdata->dev,
168 "%s: timeout observed when probing at offset %#x\n",
173 static void etm_clr_prog(struct etm_drvdata *drvdata)
177 etmcr = etm_readl(drvdata, ETMCR);
178 etmcr &= ~ETMCR_ETM_PRG;
179 etm_writel(drvdata, etmcr, ETMCR);
181 * Recommended by spec for cp14 accesses to ensure etmcr write is
182 * complete before polling etmsr
185 if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 0)) {
186 dev_err(drvdata->dev,
187 "%s: timeout observed when probing at offset %#x\n",
192 void etm_set_default(struct etm_config *config)
196 if (WARN_ON_ONCE(!config))
200 * Taken verbatim from the TRM:
202 * To trace all memory:
203 * set bit [24] in register 0x009, the ETMTECR1, to 1
204 * set all other bits in register 0x009, the ETMTECR1, to 0
205 * set all bits in register 0x007, the ETMTECR2, to 0
206 * set register 0x008, the ETMTEEVR, to 0x6F (TRUE).
208 config->enable_ctrl1 = BIT(24);
209 config->enable_ctrl2 = 0x0;
210 config->enable_event = ETM_HARD_WIRE_RES_A;
212 config->trigger_event = ETM_DEFAULT_EVENT_VAL;
213 config->enable_event = ETM_HARD_WIRE_RES_A;
215 config->seq_12_event = ETM_DEFAULT_EVENT_VAL;
216 config->seq_21_event = ETM_DEFAULT_EVENT_VAL;
217 config->seq_23_event = ETM_DEFAULT_EVENT_VAL;
218 config->seq_31_event = ETM_DEFAULT_EVENT_VAL;
219 config->seq_32_event = ETM_DEFAULT_EVENT_VAL;
220 config->seq_13_event = ETM_DEFAULT_EVENT_VAL;
221 config->timestamp_event = ETM_DEFAULT_EVENT_VAL;
223 for (i = 0; i < ETM_MAX_CNTR; i++) {
224 config->cntr_rld_val[i] = 0x0;
225 config->cntr_event[i] = ETM_DEFAULT_EVENT_VAL;
226 config->cntr_rld_event[i] = ETM_DEFAULT_EVENT_VAL;
227 config->cntr_val[i] = 0x0;
230 config->seq_curr_state = 0x0;
231 config->ctxid_idx = 0x0;
232 for (i = 0; i < ETM_MAX_CTXID_CMP; i++) {
233 config->ctxid_pid[i] = 0x0;
234 config->ctxid_vpid[i] = 0x0;
237 config->ctxid_mask = 0x0;
240 void etm_config_trace_mode(struct etm_config *config)
246 mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
248 /* excluding kernel AND user space doesn't make sense */
249 if (mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER))
252 /* nothing to do if neither flags are set */
253 if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
256 flags = (1 << 0 | /* instruction execute */
257 3 << 3 | /* ARM instruction */
258 0 << 5 | /* No data value comparison */
259 0 << 7 | /* No exact mach */
260 0 << 8); /* Ignore context ID */
262 /* No need to worry about single address comparators. */
263 config->enable_ctrl2 = 0x0;
265 /* Bit 0 is address range comparator 1 */
266 config->enable_ctrl1 = ETMTECR1_ADDR_COMP_1;
270 * ETMACTRn[13,11] == Non-secure state comparison control
271 * ETMACTRn[12,10] == Secure state comparison control
273 * b00 == Match in all modes in this state
274 * b01 == Do not match in any more in this state
275 * b10 == Match in all modes excepts user mode in this state
276 * b11 == Match only in user mode in this state
279 /* Tracing in secure mode is not supported at this time */
280 flags |= (0 << 12 | 1 << 10);
282 if (mode & ETM_MODE_EXCL_USER) {
283 /* exclude user, match all modes except user mode */
284 flags |= (1 << 13 | 0 << 11);
286 /* exclude kernel, match only in user mode */
287 flags |= (1 << 13 | 1 << 11);
291 * The ETMEEVR register is already set to "hard wire A". As such
292 * all there is to do is setup an address comparator that spans
293 * the entire address range and configure the state and mode bits.
295 config->addr_val[0] = (u32) 0x0;
296 config->addr_val[1] = (u32) ~0x0;
297 config->addr_acctype[0] = flags;
298 config->addr_acctype[1] = flags;
299 config->addr_type[0] = ETM_ADDR_TYPE_RANGE;
300 config->addr_type[1] = ETM_ADDR_TYPE_RANGE;
303 #define ETM3X_SUPPORTED_OPTIONS (ETMCR_CYC_ACC | ETMCR_TIMESTAMP_EN)
305 static int etm_parse_event_config(struct etm_drvdata *drvdata,
306 struct perf_event_attr *attr)
308 struct etm_config *config = &drvdata->config;
313 /* Clear configuration from previous run */
314 memset(config, 0, sizeof(struct etm_config));
316 if (attr->exclude_kernel)
317 config->mode = ETM_MODE_EXCL_KERN;
319 if (attr->exclude_user)
320 config->mode = ETM_MODE_EXCL_USER;
322 /* Always start from the default config */
323 etm_set_default(config);
326 * By default the tracers are configured to trace the whole address
327 * range. Narrow the field only if requested by user space.
330 etm_config_trace_mode(config);
333 * At this time only cycle accurate and timestamp options are
336 if (attr->config & ~ETM3X_SUPPORTED_OPTIONS)
339 config->ctrl = attr->config;
344 static void etm_enable_hw(void *info)
348 struct etm_drvdata *drvdata = info;
349 struct etm_config *config = &drvdata->config;
351 CS_UNLOCK(drvdata->base);
354 etm_clr_pwrdwn(drvdata);
355 /* Apply power to trace registers */
356 etm_set_pwrup(drvdata);
357 /* Make sure all registers are accessible */
358 etm_os_unlock(drvdata);
360 etm_set_prog(drvdata);
362 etmcr = etm_readl(drvdata, ETMCR);
363 /* Clear setting from a previous run if need be */
364 etmcr &= ~ETM3X_SUPPORTED_OPTIONS;
365 etmcr |= drvdata->port_size;
366 etmcr |= ETMCR_ETM_EN;
367 etm_writel(drvdata, config->ctrl | etmcr, ETMCR);
368 etm_writel(drvdata, config->trigger_event, ETMTRIGGER);
369 etm_writel(drvdata, config->startstop_ctrl, ETMTSSCR);
370 etm_writel(drvdata, config->enable_event, ETMTEEVR);
371 etm_writel(drvdata, config->enable_ctrl1, ETMTECR1);
372 etm_writel(drvdata, config->fifofull_level, ETMFFLR);
373 for (i = 0; i < drvdata->nr_addr_cmp; i++) {
374 etm_writel(drvdata, config->addr_val[i], ETMACVRn(i));
375 etm_writel(drvdata, config->addr_acctype[i], ETMACTRn(i));
377 for (i = 0; i < drvdata->nr_cntr; i++) {
378 etm_writel(drvdata, config->cntr_rld_val[i], ETMCNTRLDVRn(i));
379 etm_writel(drvdata, config->cntr_event[i], ETMCNTENRn(i));
380 etm_writel(drvdata, config->cntr_rld_event[i],
382 etm_writel(drvdata, config->cntr_val[i], ETMCNTVRn(i));
384 etm_writel(drvdata, config->seq_12_event, ETMSQ12EVR);
385 etm_writel(drvdata, config->seq_21_event, ETMSQ21EVR);
386 etm_writel(drvdata, config->seq_23_event, ETMSQ23EVR);
387 etm_writel(drvdata, config->seq_31_event, ETMSQ31EVR);
388 etm_writel(drvdata, config->seq_32_event, ETMSQ32EVR);
389 etm_writel(drvdata, config->seq_13_event, ETMSQ13EVR);
390 etm_writel(drvdata, config->seq_curr_state, ETMSQR);
391 for (i = 0; i < drvdata->nr_ext_out; i++)
392 etm_writel(drvdata, ETM_DEFAULT_EVENT_VAL, ETMEXTOUTEVRn(i));
393 for (i = 0; i < drvdata->nr_ctxid_cmp; i++)
394 etm_writel(drvdata, config->ctxid_pid[i], ETMCIDCVRn(i));
395 etm_writel(drvdata, config->ctxid_mask, ETMCIDCMR);
396 etm_writel(drvdata, config->sync_freq, ETMSYNCFR);
397 /* No external input selected */
398 etm_writel(drvdata, 0x0, ETMEXTINSELR);
399 etm_writel(drvdata, config->timestamp_event, ETMTSEVR);
400 /* No auxiliary control selected */
401 etm_writel(drvdata, 0x0, ETMAUXCR);
402 etm_writel(drvdata, drvdata->traceid, ETMTRACEIDR);
403 /* No VMID comparator value selected */
404 etm_writel(drvdata, 0x0, ETMVMIDCVR);
406 etm_clr_prog(drvdata);
407 CS_LOCK(drvdata->base);
409 dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
412 static int etm_cpu_id(struct coresight_device *csdev)
414 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
419 int etm_get_trace_id(struct etm_drvdata *drvdata)
427 if (!local_read(&drvdata->mode))
428 return drvdata->traceid;
430 pm_runtime_get_sync(drvdata->dev);
432 spin_lock_irqsave(&drvdata->spinlock, flags);
434 CS_UNLOCK(drvdata->base);
435 trace_id = (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK);
436 CS_LOCK(drvdata->base);
438 spin_unlock_irqrestore(&drvdata->spinlock, flags);
439 pm_runtime_put(drvdata->dev);
446 static int etm_trace_id(struct coresight_device *csdev)
448 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
450 return etm_get_trace_id(drvdata);
453 static int etm_enable_perf(struct coresight_device *csdev,
454 struct perf_event_attr *attr)
456 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
458 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
461 /* Configure the tracer based on the session's specifics */
462 etm_parse_event_config(drvdata, attr);
464 etm_enable_hw(drvdata);
469 static int etm_enable_sysfs(struct coresight_device *csdev)
471 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
474 spin_lock(&drvdata->spinlock);
477 * Configure the ETM only if the CPU is online. If it isn't online
478 * hw configuration will take place when 'CPU_STARTING' is received
479 * in @etm_cpu_callback.
481 if (cpu_online(drvdata->cpu)) {
482 ret = smp_call_function_single(drvdata->cpu,
483 etm_enable_hw, drvdata, 1);
488 drvdata->sticky_enable = true;
489 spin_unlock(&drvdata->spinlock);
491 dev_info(drvdata->dev, "ETM tracing enabled\n");
495 spin_unlock(&drvdata->spinlock);
499 static int etm_enable(struct coresight_device *csdev,
500 struct perf_event_attr *attr, u32 mode)
504 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
506 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
508 /* Someone is already using the tracer */
514 ret = etm_enable_sysfs(csdev);
517 ret = etm_enable_perf(csdev, attr);
523 /* The tracer didn't start */
525 local_set(&drvdata->mode, CS_MODE_DISABLED);
530 static void etm_disable_hw(void *info)
533 struct etm_drvdata *drvdata = info;
534 struct etm_config *config = &drvdata->config;
536 CS_UNLOCK(drvdata->base);
537 etm_set_prog(drvdata);
539 /* Read back sequencer and counters for post trace analysis */
540 config->seq_curr_state = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
542 for (i = 0; i < drvdata->nr_cntr; i++)
543 config->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i));
545 etm_set_pwrdwn(drvdata);
546 CS_LOCK(drvdata->base);
548 dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
551 static void etm_disable_perf(struct coresight_device *csdev)
553 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
555 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
558 CS_UNLOCK(drvdata->base);
560 /* Setting the prog bit disables tracing immediately */
561 etm_set_prog(drvdata);
564 * There is no way to know when the tracer will be used again so
565 * power down the tracer.
567 etm_set_pwrdwn(drvdata);
569 CS_LOCK(drvdata->base);
572 static void etm_disable_sysfs(struct coresight_device *csdev)
574 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
577 * Taking hotplug lock here protects from clocks getting disabled
578 * with tracing being left on (crash scenario) if user disable occurs
579 * after cpu online mask indicates the cpu is offline but before the
580 * DYING hotplug callback is serviced by the ETM driver.
583 spin_lock(&drvdata->spinlock);
586 * Executing etm_disable_hw on the cpu whose ETM is being disabled
587 * ensures that register writes occur when cpu is powered.
589 smp_call_function_single(drvdata->cpu, etm_disable_hw, drvdata, 1);
591 spin_unlock(&drvdata->spinlock);
594 dev_info(drvdata->dev, "ETM tracing disabled\n");
597 static void etm_disable(struct coresight_device *csdev)
600 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
603 * For as long as the tracer isn't disabled another entity can't
604 * change its status. As such we can read the status here without
605 * fearing it will change under us.
607 mode = local_read(&drvdata->mode);
610 case CS_MODE_DISABLED:
613 etm_disable_sysfs(csdev);
616 etm_disable_perf(csdev);
624 local_set(&drvdata->mode, CS_MODE_DISABLED);
627 static const struct coresight_ops_source etm_source_ops = {
628 .cpu_id = etm_cpu_id,
629 .trace_id = etm_trace_id,
630 .enable = etm_enable,
631 .disable = etm_disable,
634 static const struct coresight_ops etm_cs_ops = {
635 .source_ops = &etm_source_ops,
638 static int etm_cpu_callback(struct notifier_block *nfb, unsigned long action,
641 unsigned int cpu = (unsigned long)hcpu;
643 if (!etmdrvdata[cpu])
646 switch (action & (~CPU_TASKS_FROZEN)) {
648 spin_lock(&etmdrvdata[cpu]->spinlock);
649 if (!etmdrvdata[cpu]->os_unlock) {
650 etm_os_unlock(etmdrvdata[cpu]);
651 etmdrvdata[cpu]->os_unlock = true;
654 if (local_read(&etmdrvdata[cpu]->mode))
655 etm_enable_hw(etmdrvdata[cpu]);
656 spin_unlock(&etmdrvdata[cpu]->spinlock);
660 if (etmdrvdata[cpu]->boot_enable &&
661 !etmdrvdata[cpu]->sticky_enable)
662 coresight_enable(etmdrvdata[cpu]->csdev);
666 spin_lock(&etmdrvdata[cpu]->spinlock);
667 if (local_read(&etmdrvdata[cpu]->mode))
668 etm_disable_hw(etmdrvdata[cpu]);
669 spin_unlock(&etmdrvdata[cpu]->spinlock);
676 static struct notifier_block etm_cpu_notifier = {
677 .notifier_call = etm_cpu_callback,
680 static bool etm_arch_supported(u8 arch)
697 static void etm_init_arch_data(void *info)
701 struct etm_drvdata *drvdata = info;
703 /* Make sure all registers are accessible */
704 etm_os_unlock(drvdata);
706 CS_UNLOCK(drvdata->base);
708 /* First dummy read */
709 (void)etm_readl(drvdata, ETMPDSR);
710 /* Provide power to ETM: ETMPDCR[3] == 1 */
711 etm_set_pwrup(drvdata);
713 * Clear power down bit since when this bit is set writes to
714 * certain registers might be ignored.
716 etm_clr_pwrdwn(drvdata);
718 * Set prog bit. It will be set from reset but this is included to
721 etm_set_prog(drvdata);
723 /* Find all capabilities */
724 etmidr = etm_readl(drvdata, ETMIDR);
725 drvdata->arch = BMVAL(etmidr, 4, 11);
726 drvdata->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK;
728 drvdata->etmccer = etm_readl(drvdata, ETMCCER);
729 etmccr = etm_readl(drvdata, ETMCCR);
730 drvdata->etmccr = etmccr;
731 drvdata->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
732 drvdata->nr_cntr = BMVAL(etmccr, 13, 15);
733 drvdata->nr_ext_inp = BMVAL(etmccr, 17, 19);
734 drvdata->nr_ext_out = BMVAL(etmccr, 20, 22);
735 drvdata->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
737 etm_set_pwrdwn(drvdata);
738 etm_clr_pwrup(drvdata);
739 CS_LOCK(drvdata->base);
742 static void etm_init_trace_id(struct etm_drvdata *drvdata)
744 drvdata->traceid = coresight_get_trace_id(drvdata->cpu);
747 static int etm_probe(struct amba_device *adev, const struct amba_id *id)
751 struct device *dev = &adev->dev;
752 struct coresight_platform_data *pdata = NULL;
753 struct etm_drvdata *drvdata;
754 struct resource *res = &adev->res;
755 struct coresight_desc *desc;
756 struct device_node *np = adev->dev.of_node;
758 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
762 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
767 pdata = of_get_coresight_platform_data(dev, np);
769 return PTR_ERR(pdata);
771 adev->dev.platform_data = pdata;
772 drvdata->use_cp14 = of_property_read_bool(np, "arm,cp14");
775 drvdata->dev = &adev->dev;
776 dev_set_drvdata(dev, drvdata);
778 /* Validity for the resource is already checked by the AMBA core */
779 base = devm_ioremap_resource(dev, res);
781 return PTR_ERR(base);
783 drvdata->base = base;
785 spin_lock_init(&drvdata->spinlock);
787 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
788 if (!IS_ERR(drvdata->atclk)) {
789 ret = clk_prepare_enable(drvdata->atclk);
794 drvdata->cpu = pdata ? pdata->cpu : 0;
797 etmdrvdata[drvdata->cpu] = drvdata;
799 if (smp_call_function_single(drvdata->cpu,
800 etm_init_arch_data, drvdata, 1))
801 dev_err(dev, "ETM arch init failed\n");
804 register_hotcpu_notifier(&etm_cpu_notifier);
808 if (etm_arch_supported(drvdata->arch) == false) {
810 goto err_arch_supported;
813 etm_init_trace_id(drvdata);
814 etm_set_default(&drvdata->config);
816 desc->type = CORESIGHT_DEV_TYPE_SOURCE;
817 desc->subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
818 desc->ops = &etm_cs_ops;
821 desc->groups = coresight_etm_groups;
822 drvdata->csdev = coresight_register(desc);
823 if (IS_ERR(drvdata->csdev)) {
824 ret = PTR_ERR(drvdata->csdev);
825 goto err_arch_supported;
828 ret = etm_perf_symlink(drvdata->csdev, true);
830 coresight_unregister(drvdata->csdev);
831 goto err_arch_supported;
834 pm_runtime_put(&adev->dev);
835 dev_info(dev, "%s initialized\n", (char *)id->data);
838 coresight_enable(drvdata->csdev);
839 drvdata->boot_enable = true;
845 if (--etm_count == 0)
846 unregister_hotcpu_notifier(&etm_cpu_notifier);
851 static int etm_runtime_suspend(struct device *dev)
853 struct etm_drvdata *drvdata = dev_get_drvdata(dev);
855 if (drvdata && !IS_ERR(drvdata->atclk))
856 clk_disable_unprepare(drvdata->atclk);
861 static int etm_runtime_resume(struct device *dev)
863 struct etm_drvdata *drvdata = dev_get_drvdata(dev);
865 if (drvdata && !IS_ERR(drvdata->atclk))
866 clk_prepare_enable(drvdata->atclk);
872 static const struct dev_pm_ops etm_dev_pm_ops = {
873 SET_RUNTIME_PM_OPS(etm_runtime_suspend, etm_runtime_resume, NULL)
876 static struct amba_id etm_ids[] = {
897 { /* PTM 1.1 Qualcomm */
905 static struct amba_driver etm_driver = {
907 .name = "coresight-etm3x",
908 .owner = THIS_MODULE,
909 .pm = &etm_dev_pm_ops,
910 .suppress_bind_attrs = true,
916 module_amba_driver(etm_driver);
918 MODULE_LICENSE("GPL v2");
919 MODULE_DESCRIPTION("CoreSight Program Flow Trace driver");