drivers/hwtracing/coresight/coresight-etb10.c

   1 /* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/init.h>
  16 #include <linux/types.h>
  17 #include <linux/device.h>
  18 #include <linux/io.h>
  19 #include <linux/err.h>
  20 #include <linux/fs.h>
  21 #include <linux/miscdevice.h>
  22 #include <linux/uaccess.h>
  23 #include <linux/slab.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/seq_file.h>
  27 #include <linux/coresight.h>
  28 #include <linux/amba/bus.h>
  29 #include <linux/clk.h>
  30
  31 #include "coresight-priv.h"
  32
  33 #define ETB_RAM_DEPTH_REG       0x004
  34 #define ETB_STATUS_REG          0x00c
  35 #define ETB_RAM_READ_DATA_REG   0x010
  36 #define ETB_RAM_READ_POINTER    0x014
  37 #define ETB_RAM_WRITE_POINTER   0x018
  38 #define ETB_TRG                 0x01c
  39 #define ETB_CTL_REG             0x020
  40 #define ETB_RWD_REG             0x024
  41 #define ETB_FFSR                0x300
  42 #define ETB_FFCR                0x304
  43 #define ETB_ITMISCOP0           0xee0
  44 #define ETB_ITTRFLINACK         0xee4
  45 #define ETB_ITTRFLIN            0xee8
  46 #define ETB_ITATBDATA0          0xeeC
  47 #define ETB_ITATBCTR2           0xef0
  48 #define ETB_ITATBCTR1           0xef4
  49 #define ETB_ITATBCTR0           0xef8
  50
  51 /* register description */
  52 /* STS - 0x00C */
  53 #define ETB_STATUS_RAM_FULL     BIT(0)
  54 /* CTL - 0x020 */
  55 #define ETB_CTL_CAPT_EN         BIT(0)
  56 /* FFCR - 0x304 */
  57 #define ETB_FFCR_EN_FTC         BIT(0)
  58 #define ETB_FFCR_FON_MAN        BIT(6)
  59 #define ETB_FFCR_STOP_FI        BIT(12)
  60 #define ETB_FFCR_STOP_TRIGGER   BIT(13)
  61
  62 #define ETB_FFCR_BIT            6
  63 #define ETB_FFSR_BIT            1
  64 #define ETB_FRAME_SIZE_WORDS    4
  65
  66 /**
  67  * struct etb_drvdata - specifics associated to an ETB component
  68  * @base:       memory mapped base address for this component.
  69  * @dev:        the device entity associated to this component.
  70  * @atclk:      optional clock for the core parts of the ETB.
  71  * @csdev:      component vitals needed by the framework.
  72  * @miscdev:    specifics to handle "/dev/xyz.etb" entry.
  73  * @spinlock:   only one at a time pls.
  74  * @in_use:     synchronise user space access to etb buffer.
  75  * @buf:        area of memory where ETB buffer content gets sent.
  76  * @buffer_depth: size of @buf.
  77  * @enable:     this ETB is being used.
  78  * @trigger_cntr: amount of words to store after a trigger.
  79  */
  80 struct etb_drvdata {
  81         void __iomem            *base;
  82         struct device           *dev;
  83         struct clk              *atclk;
  84         struct coresight_device *csdev;
  85         struct miscdevice       miscdev;
  86         spinlock_t              spinlock;
  87         atomic_t                in_use;
  88         u8                      *buf;
  89         u32                     buffer_depth;
  90         bool                    enable;
  91         u32                     trigger_cntr;
  92 };
  93
  94 static unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdata)
  95 {
  96         u32 depth = 0;
  97
  98         pm_runtime_get_sync(drvdata->dev);
  99
 100         /* RO registers don't need locking */
 101         depth = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG);
 102
 103         pm_runtime_put(drvdata->dev);
 104         return depth;
 105 }
 106
 107 static void etb_enable_hw(struct etb_drvdata *drvdata)
 108 {
 109         int i;
 110         u32 depth;
 111
 112         CS_UNLOCK(drvdata->base);
 113
 114         depth = drvdata->buffer_depth;
 115         /* reset write RAM pointer address */
 116         writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
 117         /* clear entire RAM buffer */
 118         for (i = 0; i < depth; i++)
 119                 writel_relaxed(0x0, drvdata->base + ETB_RWD_REG);
 120
 121         /* reset write RAM pointer address */
 122         writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
 123         /* reset read RAM pointer address */
 124         writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER);
 125
 126         writel_relaxed(drvdata->trigger_cntr, drvdata->base + ETB_TRG);
 127         writel_relaxed(ETB_FFCR_EN_FTC | ETB_FFCR_STOP_TRIGGER,
 128                        drvdata->base + ETB_FFCR);
 129         /* ETB trace capture enable */
 130         writel_relaxed(ETB_CTL_CAPT_EN, drvdata->base + ETB_CTL_REG);
 131
 132         CS_LOCK(drvdata->base);
 133 }
 134
 135 static int etb_enable(struct coresight_device *csdev)
 136 {
 137         struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 138         unsigned long flags;
 139
 140         spin_lock_irqsave(&drvdata->spinlock, flags);
 141         etb_enable_hw(drvdata);
 142         drvdata->enable = true;
 143         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 144
 145         dev_info(drvdata->dev, "ETB enabled\n");
 146         return 0;
 147 }
 148
 149 static void etb_disable_hw(struct etb_drvdata *drvdata)
 150 {
 151         u32 ffcr;
 152
 153         CS_UNLOCK(drvdata->base);
 154
 155         ffcr = readl_relaxed(drvdata->base + ETB_FFCR);
 156         /* stop formatter when a stop has completed */
 157         ffcr |= ETB_FFCR_STOP_FI;
 158         writel_relaxed(ffcr, drvdata->base + ETB_FFCR);
 159         /* manually generate a flush of the system */
 160         ffcr |= ETB_FFCR_FON_MAN;
 161         writel_relaxed(ffcr, drvdata->base + ETB_FFCR);
 162
 163         if (coresight_timeout(drvdata->base, ETB_FFCR, ETB_FFCR_BIT, 0)) {
 164                 dev_err(drvdata->dev,
 165                         "timeout observed when probing at offset %#x\n",
 166                         ETB_FFCR);
 167         }
 168
 169         /* disable trace capture */
 170         writel_relaxed(0x0, drvdata->base + ETB_CTL_REG);
 171
 172         if (coresight_timeout(drvdata->base, ETB_FFSR, ETB_FFSR_BIT, 1)) {
 173                 dev_err(drvdata->dev,
 174                         "timeout observed when probing at offset %#x\n",
 175                         ETB_FFCR);
 176         }
 177
 178         CS_LOCK(drvdata->base);
 179 }
 180
 181 static void etb_dump_hw(struct etb_drvdata *drvdata)
 182 {
 183         int i;
 184         u8 *buf_ptr;
 185         u32 read_data, depth;
 186         u32 read_ptr, write_ptr;
 187         u32 frame_off, frame_endoff;
 188
 189         CS_UNLOCK(drvdata->base);
 190
 191         read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER);
 192         write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER);
 193
 194         frame_off = write_ptr % ETB_FRAME_SIZE_WORDS;
 195         frame_endoff = ETB_FRAME_SIZE_WORDS - frame_off;
 196         if (frame_off) {
 197                 dev_err(drvdata->dev,
 198                         "write_ptr: %lu not aligned to formatter frame size\n",
 199                         (unsigned long)write_ptr);
 200                 dev_err(drvdata->dev, "frameoff: %lu, frame_endoff: %lu\n",
 201                         (unsigned long)frame_off, (unsigned long)frame_endoff);
 202                 write_ptr += frame_endoff;
 203         }
 204
 205         if ((readl_relaxed(drvdata->base + ETB_STATUS_REG)
 206                       & ETB_STATUS_RAM_FULL) == 0)
 207                 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER);
 208         else
 209                 writel_relaxed(write_ptr, drvdata->base + ETB_RAM_READ_POINTER);
 210
 211         depth = drvdata->buffer_depth;
 212         buf_ptr = drvdata->buf;
 213         for (i = 0; i < depth; i++) {
 214                 read_data = readl_relaxed(drvdata->base +
 215                                           ETB_RAM_READ_DATA_REG);
 216                 *buf_ptr++ = read_data >> 0;
 217                 *buf_ptr++ = read_data >> 8;
 218                 *buf_ptr++ = read_data >> 16;
 219                 *buf_ptr++ = read_data >> 24;
 220         }
 221
 222         if (frame_off) {
 223                 buf_ptr -= (frame_endoff * 4);
 224                 for (i = 0; i < frame_endoff; i++) {
 225                         *buf_ptr++ = 0x0;
 226                         *buf_ptr++ = 0x0;
 227                         *buf_ptr++ = 0x0;
 228                         *buf_ptr++ = 0x0;
 229                 }
 230         }
 231
 232         writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER);
 233
 234         CS_LOCK(drvdata->base);
 235 }
 236
 237 static void etb_disable(struct coresight_device *csdev)
 238 {
 239         struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 240         unsigned long flags;
 241
 242         spin_lock_irqsave(&drvdata->spinlock, flags);
 243         etb_disable_hw(drvdata);
 244         etb_dump_hw(drvdata);
 245         drvdata->enable = false;
 246         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 247
 248         dev_info(drvdata->dev, "ETB disabled\n");
 249 }
 250
 251 static const struct coresight_ops_sink etb_sink_ops = {
 252         .enable         = etb_enable,
 253         .disable        = etb_disable,
 254 };
 255
 256 static const struct coresight_ops etb_cs_ops = {
 257         .sink_ops       = &etb_sink_ops,
 258 };
 259
 260 static void etb_dump(struct etb_drvdata *drvdata)
 261 {
 262         unsigned long flags;
 263
 264         spin_lock_irqsave(&drvdata->spinlock, flags);
 265         if (drvdata->enable) {
 266                 etb_disable_hw(drvdata);
 267                 etb_dump_hw(drvdata);
 268                 etb_enable_hw(drvdata);
 269         }
 270         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 271
 272         dev_info(drvdata->dev, "ETB dumped\n");
 273 }
 274
 275 static int etb_open(struct inode *inode, struct file *file)
 276 {
 277         struct etb_drvdata *drvdata = container_of(file->private_data,
 278                                                    struct etb_drvdata, miscdev);
 279
 280         if (atomic_cmpxchg(&drvdata->in_use, 0, 1))
 281                 return -EBUSY;
 282
 283         dev_dbg(drvdata->dev, "%s: successfully opened\n", __func__);
 284         return 0;
 285 }
 286
 287 static ssize_t etb_read(struct file *file, char __user *data,
 288                                 size_t len, loff_t *ppos)
 289 {
 290         u32 depth;
 291         struct etb_drvdata *drvdata = container_of(file->private_data,
 292                                                    struct etb_drvdata, miscdev);
 293
 294         etb_dump(drvdata);
 295
 296         depth = drvdata->buffer_depth;
 297         if (*ppos + len > depth * 4)
 298                 len = depth * 4 - *ppos;
 299
 300         if (copy_to_user(data, drvdata->buf + *ppos, len)) {
 301                 dev_dbg(drvdata->dev, "%s: copy_to_user failed\n", __func__);
 302                 return -EFAULT;
 303         }
 304
 305         *ppos += len;
 306
 307         dev_dbg(drvdata->dev, "%s: %zu bytes copied, %d bytes left\n",
 308                 __func__, len, (int)(depth * 4 - *ppos));
 309         return len;
 310 }
 311
 312 static int etb_release(struct inode *inode, struct file *file)
 313 {
 314         struct etb_drvdata *drvdata = container_of(file->private_data,
 315                                                    struct etb_drvdata, miscdev);
 316         atomic_set(&drvdata->in_use, 0);
 317
 318         dev_dbg(drvdata->dev, "%s: released\n", __func__);
 319         return 0;
 320 }
 321
 322 static const struct file_operations etb_fops = {
 323         .owner          = THIS_MODULE,
 324         .open           = etb_open,
 325         .read           = etb_read,
 326         .release        = etb_release,
 327         .llseek         = no_llseek,
 328 };
 329
 330 static ssize_t status_show(struct device *dev,
 331                            struct device_attribute *attr, char *buf)
 332 {
 333         unsigned long flags;
 334         u32 etb_rdr, etb_sr, etb_rrp, etb_rwp;
 335         u32 etb_trg, etb_cr, etb_ffsr, etb_ffcr;
 336         struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent);
 337
 338         pm_runtime_get_sync(drvdata->dev);
 339         spin_lock_irqsave(&drvdata->spinlock, flags);
 340         CS_UNLOCK(drvdata->base);
 341
 342         etb_rdr = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG);
 343         etb_sr = readl_relaxed(drvdata->base + ETB_STATUS_REG);
 344         etb_rrp = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER);
 345         etb_rwp = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER);
 346         etb_trg = readl_relaxed(drvdata->base + ETB_TRG);
 347         etb_cr = readl_relaxed(drvdata->base + ETB_CTL_REG);
 348         etb_ffsr = readl_relaxed(drvdata->base + ETB_FFSR);
 349         etb_ffcr = readl_relaxed(drvdata->base + ETB_FFCR);
 350
 351         CS_LOCK(drvdata->base);
 352         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 353
 354         pm_runtime_put(drvdata->dev);
 355
 356         return sprintf(buf,
 357                        "Depth:\t\t0x%x\n"
 358                        "Status:\t\t0x%x\n"
 359                        "RAM read ptr:\t0x%x\n"
 360                        "RAM wrt ptr:\t0x%x\n"
 361                        "Trigger cnt:\t0x%x\n"
 362                        "Control:\t0x%x\n"
 363                        "Flush status:\t0x%x\n"
 364                        "Flush ctrl:\t0x%x\n",
 365                        etb_rdr, etb_sr, etb_rrp, etb_rwp,
 366                        etb_trg, etb_cr, etb_ffsr, etb_ffcr);
 367
 368         return -EINVAL;
 369 }
 370 static DEVICE_ATTR_RO(status);
 371
 372 static ssize_t trigger_cntr_show(struct device *dev,
 373                             struct device_attribute *attr, char *buf)
 374 {
 375         struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent);
 376         unsigned long val = drvdata->trigger_cntr;
 377
 378         return sprintf(buf, "%#lx\n", val);
 379 }
 380
 381 static ssize_t trigger_cntr_store(struct device *dev,
 382                              struct device_attribute *attr,
 383                              const char *buf, size_t size)
 384 {
 385         int ret;
 386         unsigned long val;
 387         struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent);
 388
 389         ret = kstrtoul(buf, 16, &val);
 390         if (ret)
 391                 return ret;
 392
 393         drvdata->trigger_cntr = val;
 394         return size;
 395 }
 396 static DEVICE_ATTR_RW(trigger_cntr);
 397
 398 static struct attribute *coresight_etb_attrs[] = {
 399         &dev_attr_trigger_cntr.attr,
 400         &dev_attr_status.attr,
 401         NULL,
 402 };
 403 ATTRIBUTE_GROUPS(coresight_etb);
 404
 405 static int etb_probe(struct amba_device *adev, const struct amba_id *id)
 406 {
 407         int ret;
 408         void __iomem *base;
 409         struct device *dev = &adev->dev;
 410         struct coresight_platform_data *pdata = NULL;
 411         struct etb_drvdata *drvdata;
 412         struct resource *res = &adev->res;
 413         struct coresight_desc *desc;
 414         struct device_node *np = adev->dev.of_node;
 415
 416         if (np) {
 417                 pdata = of_get_coresight_platform_data(dev, np);
 418                 if (IS_ERR(pdata))
 419                         return PTR_ERR(pdata);
 420                 adev->dev.platform_data = pdata;
 421         }
 422
 423         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
 424         if (!drvdata)
 425                 return -ENOMEM;
 426
 427         drvdata->dev = &adev->dev;
 428         drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
 429         if (!IS_ERR(drvdata->atclk)) {
 430                 ret = clk_prepare_enable(drvdata->atclk);
 431                 if (ret)
 432                         return ret;
 433         }
 434         dev_set_drvdata(dev, drvdata);
 435
 436         /* validity for the resource is already checked by the AMBA core */
 437         base = devm_ioremap_resource(dev, res);
 438         if (IS_ERR(base))
 439                 return PTR_ERR(base);
 440
 441         drvdata->base = base;
 442
 443         spin_lock_init(&drvdata->spinlock);
 444
 445         drvdata->buffer_depth = etb_get_buffer_depth(drvdata);
 446         pm_runtime_put(&adev->dev);
 447
 448         if (drvdata->buffer_depth & 0x80000000)
 449                 return -EINVAL;
 450
 451         drvdata->buf = devm_kzalloc(dev,
 452                                     drvdata->buffer_depth * 4, GFP_KERNEL);
 453         if (!drvdata->buf) {
 454                 dev_err(dev, "Failed to allocate %u bytes for buffer data\n",
 455                         drvdata->buffer_depth * 4);
 456                 return -ENOMEM;
 457         }
 458
 459         desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
 460         if (!desc)
 461                 return -ENOMEM;
 462
 463         desc->type = CORESIGHT_DEV_TYPE_SINK;
 464         desc->subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
 465         desc->ops = &etb_cs_ops;
 466         desc->pdata = pdata;
 467         desc->dev = dev;
 468         desc->groups = coresight_etb_groups;
 469         drvdata->csdev = coresight_register(desc);
 470         if (IS_ERR(drvdata->csdev))
 471                 return PTR_ERR(drvdata->csdev);
 472
 473         drvdata->miscdev.name = pdata->name;
 474         drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
 475         drvdata->miscdev.fops = &etb_fops;
 476         ret = misc_register(&drvdata->miscdev);
 477         if (ret)
 478                 goto err_misc_register;
 479
 480         dev_info(dev, "ETB initialized\n");
 481         return 0;
 482
 483 err_misc_register:
 484         coresight_unregister(drvdata->csdev);
 485         return ret;
 486 }
 487
 488 #ifdef CONFIG_PM
 489 static int etb_runtime_suspend(struct device *dev)
 490 {
 491         struct etb_drvdata *drvdata = dev_get_drvdata(dev);
 492
 493         if (drvdata && !IS_ERR(drvdata->atclk))
 494                 clk_disable_unprepare(drvdata->atclk);
 495
 496         return 0;
 497 }
 498
 499 static int etb_runtime_resume(struct device *dev)
 500 {
 501         struct etb_drvdata *drvdata = dev_get_drvdata(dev);
 502
 503         if (drvdata && !IS_ERR(drvdata->atclk))
 504                 clk_prepare_enable(drvdata->atclk);
 505
 506         return 0;
 507 }
 508 #endif
 509
 510 static const struct dev_pm_ops etb_dev_pm_ops = {
 511         SET_RUNTIME_PM_OPS(etb_runtime_suspend, etb_runtime_resume, NULL)
 512 };
 513
 514 static struct amba_id etb_ids[] = {
 515         {
 516                 .id     = 0x0003b907,
 517                 .mask   = 0x0003ffff,
 518         },
 519         { 0, 0},
 520 };
 521
 522 static struct amba_driver etb_driver = {
 523         .drv = {
 524                 .name   = "coresight-etb10",
 525                 .owner  = THIS_MODULE,
 526                 .pm     = &etb_dev_pm_ops,
 527                 .suppress_bind_attrs = true,
 528
 529         },
 530         .probe          = etb_probe,
 531         .id_table       = etb_ids,
 532 };
 533
 534 module_amba_driver(etb_driver);
 535
 536 MODULE_LICENSE("GPL v2");
 537 MODULE_DESCRIPTION("CoreSight Embedded Trace Buffer driver");