drivers/hwtracing/coresight/coresight-etb10.c

   1 /* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <asm/local.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/types.h>
  18 #include <linux/device.h>
  19 #include <linux/io.h>
  20 #include <linux/err.h>
  21 #include <linux/fs.h>
  22 #include <linux/miscdevice.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/coresight.h>
  29 #include <linux/amba/bus.h>
  30 #include <linux/clk.h>
  31
  32 #include "coresight-priv.h"
  33
  34 #define ETB_RAM_DEPTH_REG       0x004
  35 #define ETB_STATUS_REG          0x00c
  36 #define ETB_RAM_READ_DATA_REG   0x010
  37 #define ETB_RAM_READ_POINTER    0x014
  38 #define ETB_RAM_WRITE_POINTER   0x018
  39 #define ETB_TRG                 0x01c
  40 #define ETB_CTL_REG             0x020
  41 #define ETB_RWD_REG             0x024
  42 #define ETB_FFSR                0x300
  43 #define ETB_FFCR                0x304
  44 #define ETB_ITMISCOP0           0xee0
  45 #define ETB_ITTRFLINACK         0xee4
  46 #define ETB_ITTRFLIN            0xee8
  47 #define ETB_ITATBDATA0          0xeeC
  48 #define ETB_ITATBCTR2           0xef0
  49 #define ETB_ITATBCTR1           0xef4
  50 #define ETB_ITATBCTR0           0xef8
  51
  52 /* register description */
  53 /* STS - 0x00C */
  54 #define ETB_STATUS_RAM_FULL     BIT(0)
  55 /* CTL - 0x020 */
  56 #define ETB_CTL_CAPT_EN         BIT(0)
  57 /* FFCR - 0x304 */
  58 #define ETB_FFCR_EN_FTC         BIT(0)
  59 #define ETB_FFCR_FON_MAN        BIT(6)
  60 #define ETB_FFCR_STOP_FI        BIT(12)
  61 #define ETB_FFCR_STOP_TRIGGER   BIT(13)
  62
  63 #define ETB_FFCR_BIT            6
  64 #define ETB_FFSR_BIT            1
  65 #define ETB_FRAME_SIZE_WORDS    4
  66
  67 /**
  68  * struct etb_drvdata - specifics associated to an ETB component
  69  * @base:       memory mapped base address for this component.
  70  * @dev:        the device entity associated to this component.
  71  * @atclk:      optional clock for the core parts of the ETB.
  72  * @csdev:      component vitals needed by the framework.
  73  * @miscdev:    specifics to handle "/dev/xyz.etb" entry.
  74  * @spinlock:   only one at a time pls.
  75  * @reading:    synchronise user space access to etb buffer.
  76  * @mode:       this ETB is being used.
  77  * @buf:        area of memory where ETB buffer content gets sent.
  78  * @buffer_depth: size of @buf.
  79  * @trigger_cntr: amount of words to store after a trigger.
  80  */
  81 struct etb_drvdata {
  82         void __iomem            *base;
  83         struct device           *dev;
  84         struct clk              *atclk;
  85         struct coresight_device *csdev;
  86         struct miscdevice       miscdev;
  87         spinlock_t              spinlock;
  88         local_t                 reading;
  89         local_t                 mode;
  90         u8                      *buf;
  91         u32                     buffer_depth;
  92         u32                     trigger_cntr;
  93 };
  94
  95 static unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdata)
  96 {
  97         u32 depth = 0;
  98
  99         pm_runtime_get_sync(drvdata->dev);
 100
 101         /* RO registers don't need locking */
 102         depth = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG);
 103
 104         pm_runtime_put(drvdata->dev);
 105         return depth;
 106 }
 107
 108 static void etb_enable_hw(struct etb_drvdata *drvdata)
 109 {
 110         int i;
 111         u32 depth;
 112
 113         CS_UNLOCK(drvdata->base);
 114
 115         depth = drvdata->buffer_depth;
 116         /* reset write RAM pointer address */
 117         writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
 118         /* clear entire RAM buffer */
 119         for (i = 0; i < depth; i++)
 120                 writel_relaxed(0x0, drvdata->base + ETB_RWD_REG);
 121
 122         /* reset write RAM pointer address */
 123         writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
 124         /* reset read RAM pointer address */
 125         writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER);
 126
 127         writel_relaxed(drvdata->trigger_cntr, drvdata->base + ETB_TRG);
 128         writel_relaxed(ETB_FFCR_EN_FTC | ETB_FFCR_STOP_TRIGGER,
 129                        drvdata->base + ETB_FFCR);
 130         /* ETB trace capture enable */
 131         writel_relaxed(ETB_CTL_CAPT_EN, drvdata->base + ETB_CTL_REG);
 132
 133         CS_LOCK(drvdata->base);
 134 }
 135
 136 static int etb_enable(struct coresight_device *csdev, u32 mode)
 137 {
 138         u32 val;
 139         unsigned long flags;
 140         struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 141
 142         val = local_cmpxchg(&drvdata->mode,
 143                             CS_MODE_DISABLED, mode);
 144         /*
 145          * When accessing from Perf, a HW buffer can be handled
 146          * by a single trace entity.  In sysFS mode many tracers
 147          * can be logging to the same HW buffer.
 148          */
 149         if (val == CS_MODE_PERF)
 150                 return -EBUSY;
 151
 152         /* Nothing to do, the tracer is already enabled. */
 153         if (val == CS_MODE_SYSFS)
 154                 goto out;
 155
 156         spin_lock_irqsave(&drvdata->spinlock, flags);
 157         etb_enable_hw(drvdata);
 158         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 159
 160 out:
 161         dev_info(drvdata->dev, "ETB enabled\n");
 162         return 0;
 163 }
 164
 165 static void etb_disable_hw(struct etb_drvdata *drvdata)
 166 {
 167         u32 ffcr;
 168
 169         CS_UNLOCK(drvdata->base);
 170
 171         ffcr = readl_relaxed(drvdata->base + ETB_FFCR);
 172         /* stop formatter when a stop has completed */
 173         ffcr |= ETB_FFCR_STOP_FI;
 174         writel_relaxed(ffcr, drvdata->base + ETB_FFCR);
 175         /* manually generate a flush of the system */
 176         ffcr |= ETB_FFCR_FON_MAN;
 177         writel_relaxed(ffcr, drvdata->base + ETB_FFCR);
 178
 179         if (coresight_timeout(drvdata->base, ETB_FFCR, ETB_FFCR_BIT, 0)) {
 180                 dev_err(drvdata->dev,
 181                         "timeout observed when probing at offset %#x\n",
 182                         ETB_FFCR);
 183         }
 184
 185         /* disable trace capture */
 186         writel_relaxed(0x0, drvdata->base + ETB_CTL_REG);
 187
 188         if (coresight_timeout(drvdata->base, ETB_FFSR, ETB_FFSR_BIT, 1)) {
 189                 dev_err(drvdata->dev,
 190                         "timeout observed when probing at offset %#x\n",
 191                         ETB_FFCR);
 192         }
 193
 194         CS_LOCK(drvdata->base);
 195 }
 196
 197 static void etb_dump_hw(struct etb_drvdata *drvdata)
 198 {
 199         int i;
 200         u8 *buf_ptr;
 201         u32 read_data, depth;
 202         u32 read_ptr, write_ptr;
 203         u32 frame_off, frame_endoff;
 204
 205         CS_UNLOCK(drvdata->base);
 206
 207         read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER);
 208         write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER);
 209
 210         frame_off = write_ptr % ETB_FRAME_SIZE_WORDS;
 211         frame_endoff = ETB_FRAME_SIZE_WORDS - frame_off;
 212         if (frame_off) {
 213                 dev_err(drvdata->dev,
 214                         "write_ptr: %lu not aligned to formatter frame size\n",
 215                         (unsigned long)write_ptr);
 216                 dev_err(drvdata->dev, "frameoff: %lu, frame_endoff: %lu\n",
 217                         (unsigned long)frame_off, (unsigned long)frame_endoff);
 218                 write_ptr += frame_endoff;
 219         }
 220
 221         if ((readl_relaxed(drvdata->base + ETB_STATUS_REG)
 222                       & ETB_STATUS_RAM_FULL) == 0)
 223                 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER);
 224         else
 225                 writel_relaxed(write_ptr, drvdata->base + ETB_RAM_READ_POINTER);
 226
 227         depth = drvdata->buffer_depth;
 228         buf_ptr = drvdata->buf;
 229         for (i = 0; i < depth; i++) {
 230                 read_data = readl_relaxed(drvdata->base +
 231                                           ETB_RAM_READ_DATA_REG);
 232                 *buf_ptr++ = read_data >> 0;
 233                 *buf_ptr++ = read_data >> 8;
 234                 *buf_ptr++ = read_data >> 16;
 235                 *buf_ptr++ = read_data >> 24;
 236         }
 237
 238         if (frame_off) {
 239                 buf_ptr -= (frame_endoff * 4);
 240                 for (i = 0; i < frame_endoff; i++) {
 241                         *buf_ptr++ = 0x0;
 242                         *buf_ptr++ = 0x0;
 243                         *buf_ptr++ = 0x0;
 244                         *buf_ptr++ = 0x0;
 245                 }
 246         }
 247
 248         writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER);
 249
 250         CS_LOCK(drvdata->base);
 251 }
 252
 253 static void etb_disable(struct coresight_device *csdev)
 254 {
 255         struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 256         unsigned long flags;
 257
 258         spin_lock_irqsave(&drvdata->spinlock, flags);
 259         etb_disable_hw(drvdata);
 260         etb_dump_hw(drvdata);
 261         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 262
 263         local_set(&drvdata->mode, CS_MODE_DISABLED);
 264
 265         dev_info(drvdata->dev, "ETB disabled\n");
 266 }
 267
 268 static const struct coresight_ops_sink etb_sink_ops = {
 269         .enable         = etb_enable,
 270         .disable        = etb_disable,
 271 };
 272
 273 static const struct coresight_ops etb_cs_ops = {
 274         .sink_ops       = &etb_sink_ops,
 275 };
 276
 277 static void etb_dump(struct etb_drvdata *drvdata)
 278 {
 279         unsigned long flags;
 280
 281         spin_lock_irqsave(&drvdata->spinlock, flags);
 282         if (local_read(&drvdata->mode) == CS_MODE_SYSFS) {
 283                 etb_disable_hw(drvdata);
 284                 etb_dump_hw(drvdata);
 285                 etb_enable_hw(drvdata);
 286         }
 287         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 288
 289         dev_info(drvdata->dev, "ETB dumped\n");
 290 }
 291
 292 static int etb_open(struct inode *inode, struct file *file)
 293 {
 294         struct etb_drvdata *drvdata = container_of(file->private_data,
 295                                                    struct etb_drvdata, miscdev);
 296
 297         if (local_cmpxchg(&drvdata->reading, 0, 1))
 298                 return -EBUSY;
 299
 300         dev_dbg(drvdata->dev, "%s: successfully opened\n", __func__);
 301         return 0;
 302 }
 303
 304 static ssize_t etb_read(struct file *file, char __user *data,
 305                                 size_t len, loff_t *ppos)
 306 {
 307         u32 depth;
 308         struct etb_drvdata *drvdata = container_of(file->private_data,
 309                                                    struct etb_drvdata, miscdev);
 310
 311         etb_dump(drvdata);
 312
 313         depth = drvdata->buffer_depth;
 314         if (*ppos + len > depth * 4)
 315                 len = depth * 4 - *ppos;
 316
 317         if (copy_to_user(data, drvdata->buf + *ppos, len)) {
 318                 dev_dbg(drvdata->dev, "%s: copy_to_user failed\n", __func__);
 319                 return -EFAULT;
 320         }
 321
 322         *ppos += len;
 323
 324         dev_dbg(drvdata->dev, "%s: %zu bytes copied, %d bytes left\n",
 325                 __func__, len, (int)(depth * 4 - *ppos));
 326         return len;
 327 }
 328
 329 static int etb_release(struct inode *inode, struct file *file)
 330 {
 331         struct etb_drvdata *drvdata = container_of(file->private_data,
 332                                                    struct etb_drvdata, miscdev);
 333         local_set(&drvdata->reading, 0);
 334
 335         dev_dbg(drvdata->dev, "%s: released\n", __func__);
 336         return 0;
 337 }
 338
 339 static const struct file_operations etb_fops = {
 340         .owner          = THIS_MODULE,
 341         .open           = etb_open,
 342         .read           = etb_read,
 343         .release        = etb_release,
 344         .llseek         = no_llseek,
 345 };
 346
 347 static ssize_t status_show(struct device *dev,
 348                            struct device_attribute *attr, char *buf)
 349 {
 350         unsigned long flags;
 351         u32 etb_rdr, etb_sr, etb_rrp, etb_rwp;
 352         u32 etb_trg, etb_cr, etb_ffsr, etb_ffcr;
 353         struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent);
 354
 355         pm_runtime_get_sync(drvdata->dev);
 356         spin_lock_irqsave(&drvdata->spinlock, flags);
 357         CS_UNLOCK(drvdata->base);
 358
 359         etb_rdr = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG);
 360         etb_sr = readl_relaxed(drvdata->base + ETB_STATUS_REG);
 361         etb_rrp = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER);
 362         etb_rwp = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER);
 363         etb_trg = readl_relaxed(drvdata->base + ETB_TRG);
 364         etb_cr = readl_relaxed(drvdata->base + ETB_CTL_REG);
 365         etb_ffsr = readl_relaxed(drvdata->base + ETB_FFSR);
 366         etb_ffcr = readl_relaxed(drvdata->base + ETB_FFCR);
 367
 368         CS_LOCK(drvdata->base);
 369         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 370
 371         pm_runtime_put(drvdata->dev);
 372
 373         return sprintf(buf,
 374                        "Depth:\t\t0x%x\n"
 375                        "Status:\t\t0x%x\n"
 376                        "RAM read ptr:\t0x%x\n"
 377                        "RAM wrt ptr:\t0x%x\n"
 378                        "Trigger cnt:\t0x%x\n"
 379                        "Control:\t0x%x\n"
 380                        "Flush status:\t0x%x\n"
 381                        "Flush ctrl:\t0x%x\n",
 382                        etb_rdr, etb_sr, etb_rrp, etb_rwp,
 383                        etb_trg, etb_cr, etb_ffsr, etb_ffcr);
 384
 385         return -EINVAL;
 386 }
 387 static DEVICE_ATTR_RO(status);
 388
 389 static ssize_t trigger_cntr_show(struct device *dev,
 390                             struct device_attribute *attr, char *buf)
 391 {
 392         struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent);
 393         unsigned long val = drvdata->trigger_cntr;
 394
 395         return sprintf(buf, "%#lx\n", val);
 396 }
 397
 398 static ssize_t trigger_cntr_store(struct device *dev,
 399                              struct device_attribute *attr,
 400                              const char *buf, size_t size)
 401 {
 402         int ret;
 403         unsigned long val;
 404         struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent);
 405
 406         ret = kstrtoul(buf, 16, &val);
 407         if (ret)
 408                 return ret;
 409
 410         drvdata->trigger_cntr = val;
 411         return size;
 412 }
 413 static DEVICE_ATTR_RW(trigger_cntr);
 414
 415 static struct attribute *coresight_etb_attrs[] = {
 416         &dev_attr_trigger_cntr.attr,
 417         &dev_attr_status.attr,
 418         NULL,
 419 };
 420 ATTRIBUTE_GROUPS(coresight_etb);
 421
 422 static int etb_probe(struct amba_device *adev, const struct amba_id *id)
 423 {
 424         int ret;
 425         void __iomem *base;
 426         struct device *dev = &adev->dev;
 427         struct coresight_platform_data *pdata = NULL;
 428         struct etb_drvdata *drvdata;
 429         struct resource *res = &adev->res;
 430         struct coresight_desc *desc;
 431         struct device_node *np = adev->dev.of_node;
 432
 433         if (np) {
 434                 pdata = of_get_coresight_platform_data(dev, np);
 435                 if (IS_ERR(pdata))
 436                         return PTR_ERR(pdata);
 437                 adev->dev.platform_data = pdata;
 438         }
 439
 440         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
 441         if (!drvdata)
 442                 return -ENOMEM;
 443
 444         drvdata->dev = &adev->dev;
 445         drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
 446         if (!IS_ERR(drvdata->atclk)) {
 447                 ret = clk_prepare_enable(drvdata->atclk);
 448                 if (ret)
 449                         return ret;
 450         }
 451         dev_set_drvdata(dev, drvdata);
 452
 453         /* validity for the resource is already checked by the AMBA core */
 454         base = devm_ioremap_resource(dev, res);
 455         if (IS_ERR(base))
 456                 return PTR_ERR(base);
 457
 458         drvdata->base = base;
 459
 460         spin_lock_init(&drvdata->spinlock);
 461
 462         drvdata->buffer_depth = etb_get_buffer_depth(drvdata);
 463         pm_runtime_put(&adev->dev);
 464
 465         if (drvdata->buffer_depth & 0x80000000)
 466                 return -EINVAL;
 467
 468         drvdata->buf = devm_kzalloc(dev,
 469                                     drvdata->buffer_depth * 4, GFP_KERNEL);
 470         if (!drvdata->buf) {
 471                 dev_err(dev, "Failed to allocate %u bytes for buffer data\n",
 472                         drvdata->buffer_depth * 4);
 473                 return -ENOMEM;
 474         }
 475
 476         desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
 477         if (!desc)
 478                 return -ENOMEM;
 479
 480         desc->type = CORESIGHT_DEV_TYPE_SINK;
 481         desc->subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
 482         desc->ops = &etb_cs_ops;
 483         desc->pdata = pdata;
 484         desc->dev = dev;
 485         desc->groups = coresight_etb_groups;
 486         drvdata->csdev = coresight_register(desc);
 487         if (IS_ERR(drvdata->csdev))
 488                 return PTR_ERR(drvdata->csdev);
 489
 490         drvdata->miscdev.name = pdata->name;
 491         drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
 492         drvdata->miscdev.fops = &etb_fops;
 493         ret = misc_register(&drvdata->miscdev);
 494         if (ret)
 495                 goto err_misc_register;
 496
 497         dev_info(dev, "ETB initialized\n");
 498         return 0;
 499
 500 err_misc_register:
 501         coresight_unregister(drvdata->csdev);
 502         return ret;
 503 }
 504
 505 #ifdef CONFIG_PM
 506 static int etb_runtime_suspend(struct device *dev)
 507 {
 508         struct etb_drvdata *drvdata = dev_get_drvdata(dev);
 509
 510         if (drvdata && !IS_ERR(drvdata->atclk))
 511                 clk_disable_unprepare(drvdata->atclk);
 512
 513         return 0;
 514 }
 515
 516 static int etb_runtime_resume(struct device *dev)
 517 {
 518         struct etb_drvdata *drvdata = dev_get_drvdata(dev);
 519
 520         if (drvdata && !IS_ERR(drvdata->atclk))
 521                 clk_prepare_enable(drvdata->atclk);
 522
 523         return 0;
 524 }
 525 #endif
 526
 527 static const struct dev_pm_ops etb_dev_pm_ops = {
 528         SET_RUNTIME_PM_OPS(etb_runtime_suspend, etb_runtime_resume, NULL)
 529 };
 530
 531 static struct amba_id etb_ids[] = {
 532         {
 533                 .id     = 0x0003b907,
 534                 .mask   = 0x0003ffff,
 535         },
 536         { 0, 0},
 537 };
 538
 539 static struct amba_driver etb_driver = {
 540         .drv = {
 541                 .name   = "coresight-etb10",
 542                 .owner  = THIS_MODULE,
 543                 .pm     = &etb_dev_pm_ops,
 544                 .suppress_bind_attrs = true,
 545
 546         },
 547         .probe          = etb_probe,
 548         .id_table       = etb_ids,
 549 };
 550
 551 module_amba_driver(etb_driver);
 552
 553 MODULE_LICENSE("GPL v2");
 554 MODULE_DESCRIPTION("CoreSight Embedded Trace Buffer driver");