drivers/hwtracing/coresight/coresight-etb10.c

   1 /* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <asm/local.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/types.h>
  18 #include <linux/device.h>
  19 #include <linux/io.h>
  20 #include <linux/err.h>
  21 #include <linux/fs.h>
  22 #include <linux/miscdevice.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/coresight.h>
  29 #include <linux/amba/bus.h>
  30 #include <linux/clk.h>
  31
  32 #include "coresight-priv.h"
  33
  34 #define ETB_RAM_DEPTH_REG       0x004
  35 #define ETB_STATUS_REG          0x00c
  36 #define ETB_RAM_READ_DATA_REG   0x010
  37 #define ETB_RAM_READ_POINTER    0x014
  38 #define ETB_RAM_WRITE_POINTER   0x018
  39 #define ETB_TRG                 0x01c
  40 #define ETB_CTL_REG             0x020
  41 #define ETB_RWD_REG             0x024
  42 #define ETB_FFSR                0x300
  43 #define ETB_FFCR                0x304
  44 #define ETB_ITMISCOP0           0xee0
  45 #define ETB_ITTRFLINACK         0xee4
  46 #define ETB_ITTRFLIN            0xee8
  47 #define ETB_ITATBDATA0          0xeeC
  48 #define ETB_ITATBCTR2           0xef0
  49 #define ETB_ITATBCTR1           0xef4
  50 #define ETB_ITATBCTR0           0xef8
  51
  52 /* register description */
  53 /* STS - 0x00C */
  54 #define ETB_STATUS_RAM_FULL     BIT(0)
  55 /* CTL - 0x020 */
  56 #define ETB_CTL_CAPT_EN         BIT(0)
  57 /* FFCR - 0x304 */
  58 #define ETB_FFCR_EN_FTC         BIT(0)
  59 #define ETB_FFCR_FON_MAN        BIT(6)
  60 #define ETB_FFCR_STOP_FI        BIT(12)
  61 #define ETB_FFCR_STOP_TRIGGER   BIT(13)
  62
  63 #define ETB_FFCR_BIT            6
  64 #define ETB_FFSR_BIT            1
  65 #define ETB_FRAME_SIZE_WORDS    4
  66
  67 /**
  68  * struct etb_drvdata - specifics associated to an ETB component
  69  * @base:       memory mapped base address for this component.
  70  * @dev:        the device entity associated to this component.
  71  * @atclk:      optional clock for the core parts of the ETB.
  72  * @csdev:      component vitals needed by the framework.
  73  * @miscdev:    specifics to handle "/dev/xyz.etb" entry.
  74  * @spinlock:   only one at a time pls.
  75  * @reading:    synchronise user space access to etb buffer.
  76  * @buf:        area of memory where ETB buffer content gets sent.
  77  * @buffer_depth: size of @buf.
  78  * @enable:     this ETB is being used.
  79  * @trigger_cntr: amount of words to store after a trigger.
  80  */
  81 struct etb_drvdata {
  82         void __iomem            *base;
  83         struct device           *dev;
  84         struct clk              *atclk;
  85         struct coresight_device *csdev;
  86         struct miscdevice       miscdev;
  87         spinlock_t              spinlock;
  88         local_t                 reading;
  89         u8                      *buf;
  90         u32                     buffer_depth;
  91         bool                    enable;
  92         u32                     trigger_cntr;
  93 };
  94
  95 static unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdata)
  96 {
  97         u32 depth = 0;
  98
  99         pm_runtime_get_sync(drvdata->dev);
 100
 101         /* RO registers don't need locking */
 102         depth = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG);
 103
 104         pm_runtime_put(drvdata->dev);
 105         return depth;
 106 }
 107
 108 static void etb_enable_hw(struct etb_drvdata *drvdata)
 109 {
 110         int i;
 111         u32 depth;
 112
 113         CS_UNLOCK(drvdata->base);
 114
 115         depth = drvdata->buffer_depth;
 116         /* reset write RAM pointer address */
 117         writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
 118         /* clear entire RAM buffer */
 119         for (i = 0; i < depth; i++)
 120                 writel_relaxed(0x0, drvdata->base + ETB_RWD_REG);
 121
 122         /* reset write RAM pointer address */
 123         writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
 124         /* reset read RAM pointer address */
 125         writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER);
 126
 127         writel_relaxed(drvdata->trigger_cntr, drvdata->base + ETB_TRG);
 128         writel_relaxed(ETB_FFCR_EN_FTC | ETB_FFCR_STOP_TRIGGER,
 129                        drvdata->base + ETB_FFCR);
 130         /* ETB trace capture enable */
 131         writel_relaxed(ETB_CTL_CAPT_EN, drvdata->base + ETB_CTL_REG);
 132
 133         CS_LOCK(drvdata->base);
 134 }
 135
 136 static int etb_enable(struct coresight_device *csdev)
 137 {
 138         struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 139         unsigned long flags;
 140
 141         spin_lock_irqsave(&drvdata->spinlock, flags);
 142         etb_enable_hw(drvdata);
 143         drvdata->enable = true;
 144         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 145
 146         dev_info(drvdata->dev, "ETB enabled\n");
 147         return 0;
 148 }
 149
 150 static void etb_disable_hw(struct etb_drvdata *drvdata)
 151 {
 152         u32 ffcr;
 153
 154         CS_UNLOCK(drvdata->base);
 155
 156         ffcr = readl_relaxed(drvdata->base + ETB_FFCR);
 157         /* stop formatter when a stop has completed */
 158         ffcr |= ETB_FFCR_STOP_FI;
 159         writel_relaxed(ffcr, drvdata->base + ETB_FFCR);
 160         /* manually generate a flush of the system */
 161         ffcr |= ETB_FFCR_FON_MAN;
 162         writel_relaxed(ffcr, drvdata->base + ETB_FFCR);
 163
 164         if (coresight_timeout(drvdata->base, ETB_FFCR, ETB_FFCR_BIT, 0)) {
 165                 dev_err(drvdata->dev,
 166                         "timeout observed when probing at offset %#x\n",
 167                         ETB_FFCR);
 168         }
 169
 170         /* disable trace capture */
 171         writel_relaxed(0x0, drvdata->base + ETB_CTL_REG);
 172
 173         if (coresight_timeout(drvdata->base, ETB_FFSR, ETB_FFSR_BIT, 1)) {
 174                 dev_err(drvdata->dev,
 175                         "timeout observed when probing at offset %#x\n",
 176                         ETB_FFCR);
 177         }
 178
 179         CS_LOCK(drvdata->base);
 180 }
 181
 182 static void etb_dump_hw(struct etb_drvdata *drvdata)
 183 {
 184         int i;
 185         u8 *buf_ptr;
 186         u32 read_data, depth;
 187         u32 read_ptr, write_ptr;
 188         u32 frame_off, frame_endoff;
 189
 190         CS_UNLOCK(drvdata->base);
 191
 192         read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER);
 193         write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER);
 194
 195         frame_off = write_ptr % ETB_FRAME_SIZE_WORDS;
 196         frame_endoff = ETB_FRAME_SIZE_WORDS - frame_off;
 197         if (frame_off) {
 198                 dev_err(drvdata->dev,
 199                         "write_ptr: %lu not aligned to formatter frame size\n",
 200                         (unsigned long)write_ptr);
 201                 dev_err(drvdata->dev, "frameoff: %lu, frame_endoff: %lu\n",
 202                         (unsigned long)frame_off, (unsigned long)frame_endoff);
 203                 write_ptr += frame_endoff;
 204         }
 205
 206         if ((readl_relaxed(drvdata->base + ETB_STATUS_REG)
 207                       & ETB_STATUS_RAM_FULL) == 0)
 208                 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER);
 209         else
 210                 writel_relaxed(write_ptr, drvdata->base + ETB_RAM_READ_POINTER);
 211
 212         depth = drvdata->buffer_depth;
 213         buf_ptr = drvdata->buf;
 214         for (i = 0; i < depth; i++) {
 215                 read_data = readl_relaxed(drvdata->base +
 216                                           ETB_RAM_READ_DATA_REG);
 217                 *buf_ptr++ = read_data >> 0;
 218                 *buf_ptr++ = read_data >> 8;
 219                 *buf_ptr++ = read_data >> 16;
 220                 *buf_ptr++ = read_data >> 24;
 221         }
 222
 223         if (frame_off) {
 224                 buf_ptr -= (frame_endoff * 4);
 225                 for (i = 0; i < frame_endoff; i++) {
 226                         *buf_ptr++ = 0x0;
 227                         *buf_ptr++ = 0x0;
 228                         *buf_ptr++ = 0x0;
 229                         *buf_ptr++ = 0x0;
 230                 }
 231         }
 232
 233         writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER);
 234
 235         CS_LOCK(drvdata->base);
 236 }
 237
 238 static void etb_disable(struct coresight_device *csdev)
 239 {
 240         struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 241         unsigned long flags;
 242
 243         spin_lock_irqsave(&drvdata->spinlock, flags);
 244         etb_disable_hw(drvdata);
 245         etb_dump_hw(drvdata);
 246         drvdata->enable = false;
 247         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 248
 249         dev_info(drvdata->dev, "ETB disabled\n");
 250 }
 251
 252 static const struct coresight_ops_sink etb_sink_ops = {
 253         .enable         = etb_enable,
 254         .disable        = etb_disable,
 255 };
 256
 257 static const struct coresight_ops etb_cs_ops = {
 258         .sink_ops       = &etb_sink_ops,
 259 };
 260
 261 static void etb_dump(struct etb_drvdata *drvdata)
 262 {
 263         unsigned long flags;
 264
 265         spin_lock_irqsave(&drvdata->spinlock, flags);
 266         if (drvdata->enable) {
 267                 etb_disable_hw(drvdata);
 268                 etb_dump_hw(drvdata);
 269                 etb_enable_hw(drvdata);
 270         }
 271         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 272
 273         dev_info(drvdata->dev, "ETB dumped\n");
 274 }
 275
 276 static int etb_open(struct inode *inode, struct file *file)
 277 {
 278         struct etb_drvdata *drvdata = container_of(file->private_data,
 279                                                    struct etb_drvdata, miscdev);
 280
 281         if (local_cmpxchg(&drvdata->reading, 0, 1))
 282                 return -EBUSY;
 283
 284         dev_dbg(drvdata->dev, "%s: successfully opened\n", __func__);
 285         return 0;
 286 }
 287
 288 static ssize_t etb_read(struct file *file, char __user *data,
 289                                 size_t len, loff_t *ppos)
 290 {
 291         u32 depth;
 292         struct etb_drvdata *drvdata = container_of(file->private_data,
 293                                                    struct etb_drvdata, miscdev);
 294
 295         etb_dump(drvdata);
 296
 297         depth = drvdata->buffer_depth;
 298         if (*ppos + len > depth * 4)
 299                 len = depth * 4 - *ppos;
 300
 301         if (copy_to_user(data, drvdata->buf + *ppos, len)) {
 302                 dev_dbg(drvdata->dev, "%s: copy_to_user failed\n", __func__);
 303                 return -EFAULT;
 304         }
 305
 306         *ppos += len;
 307
 308         dev_dbg(drvdata->dev, "%s: %zu bytes copied, %d bytes left\n",
 309                 __func__, len, (int)(depth * 4 - *ppos));
 310         return len;
 311 }
 312
 313 static int etb_release(struct inode *inode, struct file *file)
 314 {
 315         struct etb_drvdata *drvdata = container_of(file->private_data,
 316                                                    struct etb_drvdata, miscdev);
 317         local_set(&drvdata->reading, 0);
 318
 319         dev_dbg(drvdata->dev, "%s: released\n", __func__);
 320         return 0;
 321 }
 322
 323 static const struct file_operations etb_fops = {
 324         .owner          = THIS_MODULE,
 325         .open           = etb_open,
 326         .read           = etb_read,
 327         .release        = etb_release,
 328         .llseek         = no_llseek,
 329 };
 330
 331 static ssize_t status_show(struct device *dev,
 332                            struct device_attribute *attr, char *buf)
 333 {
 334         unsigned long flags;
 335         u32 etb_rdr, etb_sr, etb_rrp, etb_rwp;
 336         u32 etb_trg, etb_cr, etb_ffsr, etb_ffcr;
 337         struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent);
 338
 339         pm_runtime_get_sync(drvdata->dev);
 340         spin_lock_irqsave(&drvdata->spinlock, flags);
 341         CS_UNLOCK(drvdata->base);
 342
 343         etb_rdr = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG);
 344         etb_sr = readl_relaxed(drvdata->base + ETB_STATUS_REG);
 345         etb_rrp = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER);
 346         etb_rwp = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER);
 347         etb_trg = readl_relaxed(drvdata->base + ETB_TRG);
 348         etb_cr = readl_relaxed(drvdata->base + ETB_CTL_REG);
 349         etb_ffsr = readl_relaxed(drvdata->base + ETB_FFSR);
 350         etb_ffcr = readl_relaxed(drvdata->base + ETB_FFCR);
 351
 352         CS_LOCK(drvdata->base);
 353         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 354
 355         pm_runtime_put(drvdata->dev);
 356
 357         return sprintf(buf,
 358                        "Depth:\t\t0x%x\n"
 359                        "Status:\t\t0x%x\n"
 360                        "RAM read ptr:\t0x%x\n"
 361                        "RAM wrt ptr:\t0x%x\n"
 362                        "Trigger cnt:\t0x%x\n"
 363                        "Control:\t0x%x\n"
 364                        "Flush status:\t0x%x\n"
 365                        "Flush ctrl:\t0x%x\n",
 366                        etb_rdr, etb_sr, etb_rrp, etb_rwp,
 367                        etb_trg, etb_cr, etb_ffsr, etb_ffcr);
 368
 369         return -EINVAL;
 370 }
 371 static DEVICE_ATTR_RO(status);
 372
 373 static ssize_t trigger_cntr_show(struct device *dev,
 374                             struct device_attribute *attr, char *buf)
 375 {
 376         struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent);
 377         unsigned long val = drvdata->trigger_cntr;
 378
 379         return sprintf(buf, "%#lx\n", val);
 380 }
 381
 382 static ssize_t trigger_cntr_store(struct device *dev,
 383                              struct device_attribute *attr,
 384                              const char *buf, size_t size)
 385 {
 386         int ret;
 387         unsigned long val;
 388         struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent);
 389
 390         ret = kstrtoul(buf, 16, &val);
 391         if (ret)
 392                 return ret;
 393
 394         drvdata->trigger_cntr = val;
 395         return size;
 396 }
 397 static DEVICE_ATTR_RW(trigger_cntr);
 398
 399 static struct attribute *coresight_etb_attrs[] = {
 400         &dev_attr_trigger_cntr.attr,
 401         &dev_attr_status.attr,
 402         NULL,
 403 };
 404 ATTRIBUTE_GROUPS(coresight_etb);
 405
 406 static int etb_probe(struct amba_device *adev, const struct amba_id *id)
 407 {
 408         int ret;
 409         void __iomem *base;
 410         struct device *dev = &adev->dev;
 411         struct coresight_platform_data *pdata = NULL;
 412         struct etb_drvdata *drvdata;
 413         struct resource *res = &adev->res;
 414         struct coresight_desc *desc;
 415         struct device_node *np = adev->dev.of_node;
 416
 417         if (np) {
 418                 pdata = of_get_coresight_platform_data(dev, np);
 419                 if (IS_ERR(pdata))
 420                         return PTR_ERR(pdata);
 421                 adev->dev.platform_data = pdata;
 422         }
 423
 424         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
 425         if (!drvdata)
 426                 return -ENOMEM;
 427
 428         drvdata->dev = &adev->dev;
 429         drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
 430         if (!IS_ERR(drvdata->atclk)) {
 431                 ret = clk_prepare_enable(drvdata->atclk);
 432                 if (ret)
 433                         return ret;
 434         }
 435         dev_set_drvdata(dev, drvdata);
 436
 437         /* validity for the resource is already checked by the AMBA core */
 438         base = devm_ioremap_resource(dev, res);
 439         if (IS_ERR(base))
 440                 return PTR_ERR(base);
 441
 442         drvdata->base = base;
 443
 444         spin_lock_init(&drvdata->spinlock);
 445
 446         drvdata->buffer_depth = etb_get_buffer_depth(drvdata);
 447         pm_runtime_put(&adev->dev);
 448
 449         if (drvdata->buffer_depth & 0x80000000)
 450                 return -EINVAL;
 451
 452         drvdata->buf = devm_kzalloc(dev,
 453                                     drvdata->buffer_depth * 4, GFP_KERNEL);
 454         if (!drvdata->buf) {
 455                 dev_err(dev, "Failed to allocate %u bytes for buffer data\n",
 456                         drvdata->buffer_depth * 4);
 457                 return -ENOMEM;
 458         }
 459
 460         desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
 461         if (!desc)
 462                 return -ENOMEM;
 463
 464         desc->type = CORESIGHT_DEV_TYPE_SINK;
 465         desc->subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
 466         desc->ops = &etb_cs_ops;
 467         desc->pdata = pdata;
 468         desc->dev = dev;
 469         desc->groups = coresight_etb_groups;
 470         drvdata->csdev = coresight_register(desc);
 471         if (IS_ERR(drvdata->csdev))
 472                 return PTR_ERR(drvdata->csdev);
 473
 474         drvdata->miscdev.name = pdata->name;
 475         drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
 476         drvdata->miscdev.fops = &etb_fops;
 477         ret = misc_register(&drvdata->miscdev);
 478         if (ret)
 479                 goto err_misc_register;
 480
 481         dev_info(dev, "ETB initialized\n");
 482         return 0;
 483
 484 err_misc_register:
 485         coresight_unregister(drvdata->csdev);
 486         return ret;
 487 }
 488
 489 #ifdef CONFIG_PM
 490 static int etb_runtime_suspend(struct device *dev)
 491 {
 492         struct etb_drvdata *drvdata = dev_get_drvdata(dev);
 493
 494         if (drvdata && !IS_ERR(drvdata->atclk))
 495                 clk_disable_unprepare(drvdata->atclk);
 496
 497         return 0;
 498 }
 499
 500 static int etb_runtime_resume(struct device *dev)
 501 {
 502         struct etb_drvdata *drvdata = dev_get_drvdata(dev);
 503
 504         if (drvdata && !IS_ERR(drvdata->atclk))
 505                 clk_prepare_enable(drvdata->atclk);
 506
 507         return 0;
 508 }
 509 #endif
 510
 511 static const struct dev_pm_ops etb_dev_pm_ops = {
 512         SET_RUNTIME_PM_OPS(etb_runtime_suspend, etb_runtime_resume, NULL)
 513 };
 514
 515 static struct amba_id etb_ids[] = {
 516         {
 517                 .id     = 0x0003b907,
 518                 .mask   = 0x0003ffff,
 519         },
 520         { 0, 0},
 521 };
 522
 523 static struct amba_driver etb_driver = {
 524         .drv = {
 525                 .name   = "coresight-etb10",
 526                 .owner  = THIS_MODULE,
 527                 .pm     = &etb_dev_pm_ops,
 528                 .suppress_bind_attrs = true,
 529
 530         },
 531         .probe          = etb_probe,
 532         .id_table       = etb_ids,
 533 };
 534
 535 module_amba_driver(etb_driver);
 536
 537 MODULE_LICENSE("GPL v2");
 538 MODULE_DESCRIPTION("CoreSight Embedded Trace Buffer driver");