drivers/gpu/rogue_m/services/system/rgx_sunxi/sunxi_init.c

   1 /*************************************************************************/ /*!
   2 @Title          System Configuration
   3 @Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
   4 @License        Dual MIT/GPLv2
   5
   6 The contents of this file are subject to the MIT license as set out below.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining a copy
   9 of this software and associated documentation files (the "Software"), to deal
  10 in the Software without restriction, including without limitation the rights
  11 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12 copies of the Software, and to permit persons to whom the Software is
  13 furnished to do so, subject to the following conditions:
  14
  15 The above copyright notice and this permission notice shall be included in
  16 all copies or substantial portions of the Software.
  17
  18 Alternatively, the contents of this file may be used under the terms of
  19 the GNU General Public License Version 2 ("GPL") in which case the provisions
  20 of GPL are applicable instead of those above.
  21
  22 If you wish to allow use of your version of this file only under the terms of
  23 GPL, and not to allow others to use your version of this file under the terms
  24 of the MIT license, indicate your decision by deleting the provisions above
  25 and replace them with the notice and other provisions required by GPL as set
  26 out in the file called "GPL-COPYING" included in this distribution. If you do
  27 not delete the provisions above, a recipient may use your version of this file
  28 under the terms of either the MIT license or GPL.
  29
  30 This License is also included in this distribution in the file called
  31 "MIT-COPYING".
  32
  33 EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
  34 PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
  35 BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  36 PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
  37 COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  38 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  39 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  40 @Description    System Configuration functions
  41 */ /**************************************************************************/
  42
  43 #if defined(SUPPORT_ION)
  44 #include "ion_sys.h"
  45 #endif /* defined(SUPPORT_ION) */
  46
  47 #include <linux/hardirq.h>
  48 #include <linux/clk.h>
  49 #include <linux/clk-private.h>
  50 #include <linux/io.h>
  51 #include <linux/clk/sunxi_name.h>
  52 #include <linux/clk/sunxi.h>
  53 #include <linux/platform_device.h>
  54 #include <linux/regulator/consumer.h>
  55 #include <linux/delay.h>
  56 #include <mach/irqs.h>
  57 #include <mach/hardware.h>
  58 #include <mach/platform.h>
  59 #include <mach/sys_config.h>
  60 #include "power.h"
  61 #include "sunxi_init.h"
  62 #include "pvrsrv_device.h"
  63 #include "syscommon.h"
  64
  65 #ifdef CONFIG_CPU_BUDGET_THERMAL
  66 #include <linux/cpu_budget_cooling.h>
  67 static int Is_powernow = 0;
  68 #endif /* CONFIG_CPU_BUDGET_THERMAL */
  69
  70 static const IMG_OPP asOPPTable[] =
  71 {
  72 #if defined(PVR_DVFS)
  73         { 824,  240},
  74         { 840,  260},
  75         { 856,  280},
  76         { 872,  300},
  77         { 887,  320},
  78         { 903,  340},
  79         { 919,  360},
  80         { 935,  380},
  81         { 951,  400},
  82         { 996,  420},
  83         { 982,  440},
  84         { 998,  460},
  85         { 1014, 480},
  86         { 1029, 500},
  87         { 1045, 520},
  88         { 1061, 540},
  89 #else
  90         { 700,  48},
  91         { 800, 120},
  92         { 800, 240},
  93         { 900, 320},
  94         { 900, 384},
  95         {1000, 480},
  96         {1100, 528},
  97 #endif
  98 };
  99
 100 #define LEVEL_COUNT (sizeof(asOPPTable) / sizeof(asOPPTable[0]))
 101
 102 #define AXI_CLK_FREQ 320
 103 #define GPU_CTRL "gpuctrl"
 104
 105 static struct clk *gpu_core_clk        = NULL;
 106 static struct clk *gpu_mem_clk         = NULL;
 107 static struct clk *gpu_axi_clk         = NULL;
 108 static struct clk *gpu_pll_clk         = NULL;
 109 static struct clk *gpu_ctrl_clk        = NULL;
 110 static struct regulator *rgx_regulator = NULL;
 111 static char *regulator_id              = "axp22_dcdc2";
 112
 113 #if defined(PVR_DVFS)
 114         #define DEFAULT_MIN_VL_LEVEL 0
 115 #else
 116         #define DEFAULT_MIN_VL_LEVEL 4
 117 #endif
 118
 119 static IMG_UINT32 min_vf_level_val     = DEFAULT_MIN_VL_LEVEL;
 120 static IMG_UINT32 max_vf_level_val     = LEVEL_COUNT - 1;
 121
 122 static PVRSRV_DEVICE_CONFIG* gpsDevConfig = NULL;
 123
 124 long int GetConfigFreq(IMG_VOID)
 125 {
 126     return asOPPTable[min_vf_level_val].ui32Freq*1000*1000;
 127 }
 128
 129 IMG_UINT32 AwClockFreqGet(IMG_HANDLE hSysData)
 130 {
 131         return (IMG_UINT32)clk_get_rate(gpu_core_clk);
 132 }
 133
 134 static IMG_VOID AssertGpuResetSignal(IMG_VOID)
 135 {
 136         if(sunxi_periph_reset_assert(gpu_core_clk))
 137         {
 138                 PVR_DPF((PVR_DBG_ERROR, "Failed to pull down gpu reset!"));
 139         }
 140         if(sunxi_periph_reset_assert(gpu_ctrl_clk))
 141         {
 142                 PVR_DPF((PVR_DBG_ERROR, "Failed to pull down gpu control reset!"));
 143         }
 144 }
 145
 146 static IMG_VOID DeAssertGpuResetSignal(IMG_VOID)
 147 {
 148         if(sunxi_periph_reset_deassert(gpu_ctrl_clk))
 149         {
 150                 PVR_DPF((PVR_DBG_ERROR, "Failed to release gpu control reset!"));
 151         }
 152         if(sunxi_periph_reset_deassert(gpu_core_clk))
 153         {
 154                 PVR_DPF((PVR_DBG_ERROR, "Failed to release gpu reset!"));
 155         }
 156 }
 157
 158 static IMG_VOID RgxEnableClock(IMG_VOID)
 159 {
 160         if(gpu_core_clk->enable_count == 0)
 161         {
 162                 if(clk_prepare_enable(gpu_pll_clk))
 163                 {
 164                         PVR_DPF((PVR_DBG_ERROR, "Failed to enable pll9 clock!"));
 165                 }
 166                 if(clk_prepare_enable(gpu_core_clk))
 167                 {
 168                         PVR_DPF((PVR_DBG_ERROR, "Failed to enable core clock!"));
 169                 }
 170                 if(clk_prepare_enable(gpu_mem_clk))
 171                 {
 172                         PVR_DPF((PVR_DBG_ERROR, "Failed to enable mem clock!"));
 173                 }
 174                 if(clk_prepare_enable(gpu_axi_clk))
 175                 {
 176                         PVR_DPF((PVR_DBG_ERROR, "Failed to enable axi clock!"));
 177                 }
 178                 if(clk_prepare_enable(gpu_ctrl_clk))
 179                 {
 180                         PVR_DPF((PVR_DBG_ERROR, "Failed to enable ctrl clock!"));
 181                 }
 182         }
 183 }
 184
 185 static IMG_VOID RgxDisableClock(IMG_VOID)
 186 {
 187         if(gpu_core_clk->enable_count == 1)
 188         {
 189                 clk_disable_unprepare(gpu_ctrl_clk);
 190                 clk_disable_unprepare(gpu_axi_clk);
 191                 clk_disable_unprepare(gpu_mem_clk);
 192                 clk_disable_unprepare(gpu_core_clk);
 193                 clk_disable_unprepare(gpu_pll_clk);
 194         }
 195 }
 196
 197 static IMG_VOID RgxEnablePower(IMG_VOID)
 198 {
 199         if(!regulator_is_enabled(rgx_regulator))
 200         {
 201                 regulator_enable(rgx_regulator);
 202         }
 203 }
 204
 205 static IMG_VOID RgxDisablePower(IMG_VOID)
 206 {
 207         if(regulator_is_enabled(rgx_regulator))
 208         {
 209                 regulator_disable(rgx_regulator);
 210         }
 211 }
 212
 213 void SetVoltage(IMG_UINT32 ui32Volt)
 214 {
 215         if(regulator_set_voltage(rgx_regulator, ui32Volt*1000, ui32Volt*1000) != 0)
 216         {
 217                 PVR_DPF((PVR_DBG_ERROR, "Failed to set gpu power voltage!"));
 218         }
 219 }
 220
 221 static void SetClkVal(const char clk_name[], int freq)
 222 {
 223         struct clk *clk = NULL;
 224
 225         if(!strcmp(clk_name, "pll"))
 226         {
 227                 clk = gpu_pll_clk;
 228         }
 229         else if(!strcmp(clk_name, "core"))
 230         {
 231                 clk = gpu_core_clk;
 232         }
 233         else if(!strcmp(clk_name, "mem"))
 234         {
 235                 clk = gpu_mem_clk;
 236         }
 237         else
 238         {
 239                 clk = gpu_axi_clk;
 240         }
 241
 242         if(clk_set_rate(clk, freq*1000*1000))
 243     {
 244                 clk = NULL;
 245                 return;
 246     }
 247
 248         if(clk == gpu_pll_clk)
 249         {
 250                 /* delay for gpu pll stability */
 251                 udelay(100);
 252         }
 253
 254         clk = NULL;
 255 }
 256
 257 void SetFrequency(IMG_UINT32 ui32Frequency)
 258 {
 259         SetClkVal("pll", (int) ui32Frequency);
 260 }
 261
 262 static void ParseFexPara(void)
 263 {
 264     script_item_u regulator_id_fex, min_vf_level, max_vf_level;
 265         if(SCIRPT_ITEM_VALUE_TYPE_STR == script_get_item("rgx_para", "regulator_id", &regulator_id_fex))
 266     {
 267         regulator_id = regulator_id_fex.str;
 268     }
 269
 270     if(SCIRPT_ITEM_VALUE_TYPE_INT == script_get_item("rgx_para", "min_vf_level", &min_vf_level))
 271     {
 272         if((min_vf_level.val >= 0 && min_vf_level.val < LEVEL_COUNT))
 273                 {
 274                         min_vf_level_val = min_vf_level.val;
 275                 }
 276     }
 277         else
 278         {
 279                 goto err_out2;
 280         }
 281
 282     if(SCIRPT_ITEM_VALUE_TYPE_INT == script_get_item("rgx_para", "max_vf_level", &max_vf_level))
 283     {
 284                 if(max_vf_level.val >= min_vf_level_val && max_vf_level.val < LEVEL_COUNT)
 285                 {
 286                         max_vf_level_val = max_vf_level.val;
 287                 }
 288     }
 289         else
 290         {
 291                 goto err_out1;
 292         }
 293
 294         return;
 295
 296 err_out1:
 297         min_vf_level_val = DEFAULT_MIN_VL_LEVEL;
 298 err_out2:
 299         regulator_id = "axp22_dcdc2";
 300         return;
 301 }
 302
 303 PVRSRV_ERROR AwPrePowerState(PVRSRV_DEV_POWER_STATE eNewPowerState, PVRSRV_DEV_POWER_STATE eCurrentPowerState, IMG_BOOL bForced)
 304 {
 305         return AwSysPrePowerState(eNewPowerState);
 306 }
 307
 308 PVRSRV_ERROR AwPostPowerState(PVRSRV_DEV_POWER_STATE eNewPowerState, PVRSRV_DEV_POWER_STATE eCurrentPowerState, IMG_BOOL bForced)
 309 {
 310         return AwSysPostPowerState(eNewPowerState);
 311 }
 312
 313 PVRSRV_ERROR AwSysPrePowerState(PVRSRV_SYS_POWER_STATE eNewPowerState)
 314 {
 315         if(eNewPowerState == PVRSRV_SYS_POWER_STATE_ON)
 316         {
 317                 RgxEnablePower();
 318
 319                 mdelay(2);
 320
 321                 /* set external isolation invalid */
 322                 writel(0, SUNXI_R_PRCM_VBASE + GPU_PWROFF_GATING);
 323
 324                 DeAssertGpuResetSignal();
 325
 326                 RgxEnableClock();
 327
 328                 /* set delay for internal power stability */
 329                 writel(0x100, SUNXI_GPU_CTRL_VBASE + 0x18);
 330         }
 331
 332         return PVRSRV_OK;
 333 }
 334
 335 PVRSRV_ERROR AwSysPostPowerState(PVRSRV_SYS_POWER_STATE eNewPowerState)
 336 {
 337         if(eNewPowerState == PVRSRV_SYS_POWER_STATE_OFF)
 338         {
 339                 RgxDisableClock();
 340
 341                 AssertGpuResetSignal();
 342
 343                 /* set external isolation valid */
 344                 writel(1, SUNXI_R_PRCM_VBASE + GPU_PWROFF_GATING);
 345
 346                 RgxDisablePower();
 347         }
 348
 349         return PVRSRV_OK;
 350 }
 351
 352 #ifdef CONFIG_CPU_BUDGET_THERMAL
 353 static void RgxDvfsChange(int vf_level, int up_flag)
 354 {
 355 #if defined (PVR_DVFS)
 356         IMG_DVFS_DEVICE_CFG     *psDVFSDeviceCfg = &gpsDevConfig->sDVFS.sDVFSDeviceCfg;
 357         psDVFSDeviceCfg->ui32FreqMax = asOPPTable[vf_level].ui32Freq;
 358 #else
 359         PVRSRV_ERROR err;
 360         err = PVRSRVDevicePreClockSpeedChange(0, IMG_TRUE, NULL);
 361         if(err == PVRSRV_OK)
 362         {
 363                 if(up_flag == 1)
 364                 {
 365                         SetVoltage(asOPPTable[vf_level].ui32Volt);
 366                         SetClkVal("pll", asOPPTable[vf_level].ui32Freq);
 367                 }
 368                 else
 369                 {
 370                         SetClkVal("pll", asOPPTable[vf_level].ui32Freq);
 371                         SetVoltage(asOPPTable[vf_level].ui32Volt);
 372                 }
 373                 PVRSRVDevicePostClockSpeedChange(0, IMG_TRUE, NULL);
 374         }
 375 #endif
 376 }
 377
 378 static int rgx_throttle_notifier_call(struct notifier_block *nfb, unsigned long mode, void *cmd)
 379 {
 380     int retval = NOTIFY_DONE;
 381         if(mode == BUDGET_GPU_THROTTLE && Is_powernow)
 382     {
 383                         RgxDvfsChange(min_vf_level_val, 0);
 384         Is_powernow = 0;
 385     }
 386     else
 387         {
 388         if(cmd && (*(int *)cmd) == 1 && !Is_powernow)
 389                 {
 390                         RgxDvfsChange(max_vf_level_val, 0);
 391             Is_powernow = 1;
 392         }
 393                 else if(cmd && (*(int *)cmd) == 0 && Is_powernow)
 394                 {
 395                         RgxDvfsChange(min_vf_level_val, 0);
 396             Is_powernow = 0;
 397         }
 398     }
 399
 400         return retval;
 401 }
 402
 403 static struct notifier_block rgx_throttle_notifier = {
 404 .notifier_call = rgx_throttle_notifier_call,
 405 };
 406 #endif /* CONFIG_CPU_BUDGET_THERMAL */
 407
 408 IMG_VOID RgxSunxiDeInit(IMG_VOID)
 409 {
 410 #ifdef CONFIG_CPU_BUDGET_THERMAL
 411         unregister_budget_cooling_notifier(&rgx_throttle_notifier);
 412 #endif /* CONFIG_CPU_BUDGET_THERMAL */
 413         regulator_put(rgx_regulator);
 414         rgx_regulator = NULL;
 415 }
 416
 417 void RgxSunxiInit(PVRSRV_DEVICE_CONFIG* psDevConfig)
 418 {
 419         IMG_UINT32 vf_level_val;
 420
 421         ParseFexPara();
 422
 423         rgx_regulator = regulator_get(NULL, regulator_id);
 424         if (IS_ERR(rgx_regulator))
 425         {
 426                 PVR_DPF((PVR_DBG_ERROR, "Failed to get rgx regulator!"));
 427         rgx_regulator = NULL;
 428                 return;
 429         }
 430
 431         gpu_core_clk = clk_get(NULL, GPUCORE_CLK);
 432         gpu_mem_clk  = clk_get(NULL, GPUMEM_CLK);
 433         gpu_axi_clk  = clk_get(NULL, GPUAXI_CLK);
 434         gpu_pll_clk  = clk_get(NULL, PLL9_CLK);
 435         gpu_ctrl_clk = clk_get(NULL, GPU_CTRL);
 436
 437         gpsDevConfig = psDevConfig;
 438
 439 #if defined(PVR_DVFS)
 440         gpsDevConfig->sDVFS.sDVFSDeviceCfg.pasOPPTable = asOPPTable;
 441         gpsDevConfig->sDVFS.sDVFSDeviceCfg.ui32OPPTableSize = LEVEL_COUNT;
 442         gpsDevConfig->sDVFS.sDVFSDeviceCfg.ui32FreqMin = asOPPTable[min_vf_level_val].ui32Freq;
 443         gpsDevConfig->sDVFS.sDVFSDeviceCfg.ui32FreqMax = asOPPTable[max_vf_level_val].ui32Freq;
 444         gpsDevConfig->sDVFS.sDVFSDeviceCfg.pfnSetFrequency = SetFrequency;
 445         gpsDevConfig->sDVFS.sDVFSDeviceCfg.pfnSetVoltage = SetVoltage;
 446 #endif
 447
 448         vf_level_val = min_vf_level_val;
 449
 450         SetVoltage(asOPPTable[vf_level_val].ui32Volt);
 451
 452         SetClkVal("pll", asOPPTable[vf_level_val].ui32Freq);
 453         SetClkVal("core", asOPPTable[vf_level_val].ui32Freq);
 454         SetClkVal("mem", asOPPTable[vf_level_val].ui32Freq);
 455         SetClkVal("axi", AXI_CLK_FREQ);
 456
 457         (void) AwSysPrePowerState(PVRSRV_SYS_POWER_STATE_ON);
 458
 459 #ifdef CONFIG_CPU_BUDGET_THERMAL
 460         register_budget_cooling_notifier(&rgx_throttle_notifier);
 461 #endif /* CONFIG_CPU_BUDGET_THERMAL */
 462 }