drivers/gpu/rogue_m/services/server/include/pvrsrv_device.h

   1 /**************************************************************************/ /*!
   2 @File
   3 @Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
   4 @License        Dual MIT/GPLv2
   5
   6 The contents of this file are subject to the MIT license as set out below.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining a copy
   9 of this software and associated documentation files (the "Software"), to deal
  10 in the Software without restriction, including without limitation the rights
  11 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12 copies of the Software, and to permit persons to whom the Software is
  13 furnished to do so, subject to the following conditions:
  14
  15 The above copyright notice and this permission notice shall be included in
  16 all copies or substantial portions of the Software.
  17
  18 Alternatively, the contents of this file may be used under the terms of
  19 the GNU General Public License Version 2 ("GPL") in which case the provisions
  20 of GPL are applicable instead of those above.
  21
  22 If you wish to allow use of your version of this file only under the terms of
  23 GPL, and not to allow others to use your version of this file under the terms
  24 of the MIT license, indicate your decision by deleting the provisions above
  25 and replace them with the notice and other provisions required by GPL as set
  26 out in the file called "GPL-COPYING" included in this distribution. If you do
  27 not delete the provisions above, a recipient may use your version of this file
  28 under the terms of either the MIT license or GPL.
  29
  30 This License is also included in this distribution in the file called
  31 "MIT-COPYING".
  32
  33 EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
  34 PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
  35 BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  36 PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
  37 COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  38 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  39 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  40 */ /***************************************************************************/
  41
  42 #ifndef __PVRSRV_DEVICE_H__
  43 #define __PVRSRV_DEVICE_H__
  44
  45 #include "servicesext.h"
  46 #include "pvrsrv_device_types.h"
  47 #include "img_types.h"
  48 #include "ra.h"
  49 #include "physheap.h"
  50 #include "rgx_fwif_km.h"
  51 #include "pmr.h"
  52 #include "lock.h"
  53 #include "pvr_dvfs.h"
  54
  55 typedef struct _PVRSRV_DEVICE_CONFIG_ PVRSRV_DEVICE_CONFIG;
  56
  57 /*! The CPU physical base of the LMA physical heap is used as the base for
  58  *  device memory physical heap allocations */
  59 #define PVRSRV_DEVICE_CONFIG_LMA_USE_CPU_ADDR   (1<<0)
  60
  61 /*
  62  *  The maximum number of physical heaps associated
  63  *  with a device
  64  */
  65 typedef enum
  66 {
  67         PVRSRV_DEVICE_PHYS_HEAP_GPU_LOCAL = 0,
  68         PVRSRV_DEVICE_PHYS_HEAP_CPU_LOCAL = 1,
  69         PVRSRV_DEVICE_PHYS_HEAP_LAST
  70 }PVRSRV_DEVICE_PHYS_HEAP;
  71
  72 typedef enum
  73 {
  74         PVRSRV_DEVICE_IRQ_ACTIVE_SYSDEFAULT = 0,
  75         PVRSRV_DEVICE_IRQ_ACTIVE_LOW,
  76         PVRSRV_DEVICE_IRQ_ACTIVE_HIGH
  77 }PVRSRV_DEVICE_IRQ_ACTIVE_LEVEL;
  78
  79 typedef IMG_VOID (*PFN_MISR)(IMG_VOID *pvData);
  80
  81 typedef IMG_BOOL (*PFN_LISR)(IMG_VOID *pvData);
  82
  83 typedef IMG_UINT32 (*PFN_SYS_DEV_CLK_FREQ_GET)(IMG_HANDLE hSysData);
  84
  85 typedef PVRSRV_ERROR (*PFN_SYS_DEV_PRE_POWER)(PVRSRV_DEV_POWER_STATE eNewPowerState,
  86                                               PVRSRV_DEV_POWER_STATE eCurrentPowerState,
  87                                                                                           IMG_BOOL bForced);
  88
  89
  90 typedef PVRSRV_ERROR (*PFN_SYS_DEV_POST_POWER)(PVRSRV_DEV_POWER_STATE eNewPowerState,
  91                                                PVRSRV_DEV_POWER_STATE eCurrentPowerState,
  92                                                                                            IMG_BOOL bForced);
  93
  94 typedef IMG_VOID (*PFN_SYS_DEV_INTERRUPT_HANDLED)(PVRSRV_DEVICE_CONFIG *psDevConfig);
  95
  96 typedef PVRSRV_ERROR (*PFN_SYS_DEV_CHECK_MEM_ALLOC_SIZE)(struct _PVRSRV_DEVICE_NODE_ *psDevNode,
  97                                                                                                                  IMG_UINT64 ui64MemSize);
  98
  99 struct _PVRSRV_DEVICE_CONFIG_
 100 {
 101         /*! Configuration flags */
 102         IMG_UINT32                      uiFlags;
 103
 104         /*! Name of the device (used when registering the IRQ) */
 105         IMG_CHAR                        *pszName;
 106
 107         /*! Type of device this is */
 108         PVRSRV_DEVICE_TYPE              eDeviceType;
 109
 110         /*! Register bank address */
 111         IMG_CPU_PHYADDR                 sRegsCpuPBase;
 112         /*! Register bank size */
 113         IMG_UINT32                      ui32RegsSize;
 114         /*! Device interrupt number */
 115         IMG_UINT32                      ui32IRQ;
 116
 117         /*! The device interrupt is shared */
 118         IMG_BOOL                        bIRQIsShared;
 119
 120         /*! IRQ polarity */
 121         PVRSRV_DEVICE_IRQ_ACTIVE_LEVEL  eIRQActiveLevel;
 122
 123         /*! Device specific data handle */
 124         IMG_HANDLE                      hDevData;
 125
 126         /*! System specific data. This gets passed into system callback functions */
 127         IMG_HANDLE                      hSysData;
 128
 129         /*! ID of the Physical memory heap to use
 130          *! The first entry (aui32PhysHeapID[PVRSRV_DEVICE_PHYS_HEAP_GPU_LOCAL])  will be used for allocations
 131          *!  where the PVRSRV_MEMALLOCFLAG_CPU_LOCAL flag is not set. Normally this will be the PhysHeapID
 132          *!  of an LMA heap (but the configuration could specify a UMA heap here, if desired)
 133          *! The second entry (aui32PhysHeapID[PVRSRV_DEVICE_PHYS_HEAP_CPU_LOCAL]) will be used for allocations
 134          *!  where the PVRSRV_MEMALLOCFLAG_CPU_LOCAL flag is set. Normally this will be the PhysHeapID
 135          *!  of a UMA heap (but the configuration could specify an LMA heap here, if desired)
 136          *! In the event of there being only one Physical Heap, the configuration should specify the
 137          *!  same heap details in both entries */
 138         IMG_UINT32                      aui32PhysHeapID[PVRSRV_DEVICE_PHYS_HEAP_LAST];
 139
 140         /*! Callback to inform the device we about to change power state */
 141         PFN_SYS_DEV_PRE_POWER           pfnPrePowerState;
 142
 143         /*! Callback to inform the device we have finished the power state change */
 144         PFN_SYS_DEV_POST_POWER          pfnPostPowerState;
 145
 146         /*! Callback to obtain the clock frequency from the device */
 147         PFN_SYS_DEV_CLK_FREQ_GET        pfnClockFreqGet;
 148
 149         /*! Callback to inform the device that an interrupt has been handled */
 150         PFN_SYS_DEV_INTERRUPT_HANDLED   pfnInterruptHandled;
 151
 152         /*! Callback to handle memory budgeting */
 153         PFN_SYS_DEV_CHECK_MEM_ALLOC_SIZE        pfnCheckMemAllocSize;
 154
 155         /*! Current breakpoint data master */
 156         RGXFWIF_DM                      eBPDM;
 157         /*! A Breakpoint has been set */
 158         IMG_BOOL                        bBPSet;
 159
 160 #if defined(PVR_DVFS)
 161         PVRSRV_DVFS                     sDVFS;
 162 #endif
 163 };
 164
 165 typedef PVRSRV_ERROR (*PFN_SYSTEM_PRE_POWER_STATE)(PVRSRV_SYS_POWER_STATE eNewPowerState);
 166 typedef PVRSRV_ERROR (*PFN_SYSTEM_POST_POWER_STATE)(PVRSRV_SYS_POWER_STATE eNewPowerState);
 167
 168 typedef enum _PVRSRV_SYSTEM_SNOOP_MODE_ {
 169         PVRSRV_SYSTEM_SNOOP_NONE = 0,
 170         PVRSRV_SYSTEM_SNOOP_CPU_ONLY,
 171         PVRSRV_SYSTEM_SNOOP_DEVICE_ONLY,
 172         PVRSRV_SYSTEM_SNOOP_CROSS,
 173 } PVRSRV_SYSTEM_SNOOP_MODE;
 174
 175 typedef struct _PVRSRV_SYSTEM_CONFIG_
 176 {
 177         IMG_UINT32                              uiSysFlags;
 178         IMG_CHAR                                *pszSystemName;
 179         IMG_UINT32                              uiDeviceCount;
 180         PVRSRV_DEVICE_CONFIG    *pasDevices;
 181         PFN_SYSTEM_PRE_POWER_STATE pfnSysPrePowerState;
 182         PFN_SYSTEM_POST_POWER_STATE pfnSysPostPowerState;
 183         PVRSRV_SYSTEM_SNOOP_MODE eCacheSnoopingMode;
 184
 185         PHYS_HEAP_CONFIG                *pasPhysHeaps;
 186         IMG_UINT32                              ui32PhysHeapCount;
 187
 188         IMG_UINT32              *pui32BIFTilingHeapConfigs;
 189         IMG_UINT32              ui32BIFTilingHeapCount;
 190 } PVRSRV_SYSTEM_CONFIG;
 191
 192
 193 #endif /* __PVRSRV_DEVICE_H__*/