drivers/gpu/rogue_m/services/server/include/devicemem_server_utils.h

   1 /**************************************************************************/ /*!
   2 @File
   3 @Title          Device Memory Management
   4 @Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
   5 @Description    Header file utilities that are specific to device memory functions
   6 @License        Dual MIT/GPLv2
   7
   8 The contents of this file are subject to the MIT license as set out below.
   9
  10 Permission is hereby granted, free of charge, to any person obtaining a copy
  11 of this software and associated documentation files (the "Software"), to deal
  12 in the Software without restriction, including without limitation the rights
  13 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  14 copies of the Software, and to permit persons to whom the Software is
  15 furnished to do so, subject to the following conditions:
  16
  17 The above copyright notice and this permission notice shall be included in
  18 all copies or substantial portions of the Software.
  19
  20 Alternatively, the contents of this file may be used under the terms of
  21 the GNU General Public License Version 2 ("GPL") in which case the provisions
  22 of GPL are applicable instead of those above.
  23
  24 If you wish to allow use of your version of this file only under the terms of
  25 GPL, and not to allow others to use your version of this file under the terms
  26 of the MIT license, indicate your decision by deleting the provisions above
  27 and replace them with the notice and other provisions required by GPL as set
  28 out in the file called "GPL-COPYING" included in this distribution. If you do
  29 not delete the provisions above, a recipient may use your version of this file
  30 under the terms of either the MIT license or GPL.
  31
  32 This License is also included in this distribution in the file called
  33 "MIT-COPYING".
  34
  35 EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
  36 PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
  37 BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  38 PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
  39 COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  40 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  41 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  42 */ /***************************************************************************/
  43
  44 #include "img_defs.h"
  45 #include "img_types.h"
  46 #include "pvrsrv_memallocflags.h"
  47 #include "pvrsrv.h"
  48
  49 static INLINE IMG_UINT32 DevmemCPUCacheMode(PVRSRV_MEMALLOCFLAGS_T ulFlags)
  50 {
  51         IMG_UINT32 ui32CPUCacheMode = ulFlags & PVRSRV_MEMALLOCFLAG_CPU_CACHE_MODE_MASK;
  52         IMG_UINT32 ui32Ret;
  53
  54         PVR_ASSERT(ui32CPUCacheMode == (ulFlags & PVRSRV_MEMALLOCFLAG_CPU_CACHE_MODE_MASK));
  55
  56         switch (ui32CPUCacheMode)
  57         {
  58                 case PVRSRV_MEMALLOCFLAG_CPU_UNCACHED:
  59                         ui32Ret = PVRSRV_MEMALLOCFLAG_CPU_UNCACHED;
  60                         break;
  61
  62                 case PVRSRV_MEMALLOCFLAG_CPU_WRITE_COMBINE:
  63                         ui32Ret = PVRSRV_MEMALLOCFLAG_CPU_WRITE_COMBINE;
  64                         break;
  65
  66                 case PVRSRV_MEMALLOCFLAG_CPU_CACHE_INCOHERENT:
  67                         ui32Ret = PVRSRV_MEMALLOCFLAG_CPU_CACHED;
  68                         break;
  69
  70                 case PVRSRV_MEMALLOCFLAG_CPU_CACHE_COHERENT:
  71                         /* Fall through */
  72                 case PVRSRV_MEMALLOCFLAG_CPU_CACHED_CACHE_COHERENT:
  73                         /*
  74                                 If the allocation needs to be coherent what we end up doing
  75                                 depends on the snooping features of the system
  76                         */
  77                         if (PVRSRVSystemSnoopingOfCPUCache())
  78                         {
  79                                 /*
  80                                         If the system has CPU cache snooping (tested above)
  81                                         then the allocation should be cached ...
  82                                 */
  83                                 ui32Ret = PVRSRV_MEMALLOCFLAG_CPU_CACHED;
  84                         }
  85                         else
  86                         {
  87                                 /* ... otherwise it should be uncached */
  88                                 ui32Ret = PVRSRV_MEMALLOCFLAG_CPU_UNCACHED;
  89                         }
  90                         break;
  91
  92                 default:
  93                         PVR_LOG(("DevmemCPUCacheMode: Unknown CPU cache mode 0x%08x", ui32CPUCacheMode));
  94                         PVR_ASSERT(0);
  95                         /*
  96                                 We should never get here, but if we do then setting the mode
  97                                 to uncached is the safest thing to do.
  98                         */
  99                         ui32Ret = PVRSRV_MEMALLOCFLAG_CPU_UNCACHED;
 100                         break;
 101         }
 102
 103         return ui32Ret;
 104 }
 105
 106 static INLINE IMG_UINT32 DevmemDeviceCacheMode(PVRSRV_MEMALLOCFLAGS_T ulFlags)
 107 {
 108         IMG_UINT32 ui32DeviceCacheMode = ulFlags & PVRSRV_MEMALLOCFLAG_GPU_CACHE_MODE_MASK;
 109         IMG_UINT32 ui32Ret;
 110
 111         PVR_ASSERT(ui32DeviceCacheMode == (ulFlags & PVRSRV_MEMALLOCFLAG_GPU_CACHE_MODE_MASK));
 112
 113         switch (ui32DeviceCacheMode)
 114         {
 115                 case PVRSRV_MEMALLOCFLAG_GPU_UNCACHED:
 116                         ui32Ret = PVRSRV_MEMALLOCFLAG_GPU_UNCACHED;
 117                         break;
 118
 119                 case PVRSRV_MEMALLOCFLAG_GPU_WRITE_COMBINE:
 120                         ui32Ret = PVRSRV_MEMALLOCFLAG_GPU_WRITE_COMBINE;
 121                         break;
 122
 123                 case PVRSRV_MEMALLOCFLAG_GPU_CACHE_INCOHERENT:
 124                         ui32Ret = PVRSRV_MEMALLOCFLAG_GPU_CACHED;
 125                         break;
 126
 127                 case PVRSRV_MEMALLOCFLAG_GPU_CACHE_COHERENT:
 128                         /* Fall through */
 129                 case PVRSRV_MEMALLOCFLAG_GPU_CACHED_CACHE_COHERENT:
 130                         /*
 131                                 If the allocation needs to be coherent what we end up doing
 132                                 depends on the snooping features of the system
 133                         */
 134                         if (PVRSRVSystemSnoopingOfDeviceCache())
 135                         {
 136                                 /*
 137                                         If the system has GPU cache snooping (tested above)
 138                                         then the allocation should be cached ...
 139                                 */
 140                                 ui32Ret = PVRSRV_MEMALLOCFLAG_GPU_CACHED;
 141                         }
 142                         else
 143                         {
 144                                 /* ... otherwise it should be uncached */
 145                                 ui32Ret = PVRSRV_MEMALLOCFLAG_GPU_UNCACHED;
 146                         }
 147                         break;
 148
 149                 default:
 150                         PVR_LOG(("DevmemDeviceCacheMode: Unknown device cache mode 0x%08x", ui32DeviceCacheMode));
 151                         PVR_ASSERT(0);
 152                         /*
 153                                 We should never get here, but if we do then setting the mode
 154                                 to uncached is the safest thing to do.
 155                         */
 156                         ui32Ret = PVRSRV_MEMALLOCFLAG_GPU_UNCACHED;
 157                         break;
 158         }
 159
 160         return ui32Ret;
 161 }
 162
 163 static INLINE IMG_BOOL DevmemCPUCacheCoherency(PVRSRV_MEMALLOCFLAGS_T ulFlags)
 164 {
 165         IMG_UINT32 ui32CPUCacheMode = ulFlags & PVRSRV_MEMALLOCFLAG_CPU_CACHE_MODE_MASK;
 166         IMG_BOOL bRet = IMG_FALSE;
 167
 168         PVR_ASSERT(ui32CPUCacheMode == (ulFlags & PVRSRV_MEMALLOCFLAG_CPU_CACHE_MODE_MASK));
 169
 170         if ((ui32CPUCacheMode == PVRSRV_MEMALLOCFLAG_CPU_CACHE_COHERENT) ||
 171                 (ui32CPUCacheMode == PVRSRV_MEMALLOCFLAG_CPU_CACHED_CACHE_COHERENT))
 172         {
 173                 bRet = PVRSRVSystemSnoopingOfDeviceCache();
 174         }
 175         return bRet;
 176 }
 177
 178 static INLINE IMG_BOOL DevmemDeviceCacheCoherency(PVRSRV_MEMALLOCFLAGS_T ulFlags)
 179 {
 180         IMG_UINT32 ui32DeviceCacheMode = ulFlags & PVRSRV_MEMALLOCFLAG_GPU_CACHE_MODE_MASK;
 181         IMG_BOOL bRet = IMG_FALSE;
 182
 183         PVR_ASSERT(ui32DeviceCacheMode == (ulFlags & PVRSRV_MEMALLOCFLAG_GPU_CACHE_MODE_MASK));
 184
 185         if ((ui32DeviceCacheMode == PVRSRV_MEMALLOCFLAG_GPU_CACHE_COHERENT) ||
 186                 (ui32DeviceCacheMode == PVRSRV_MEMALLOCFLAG_GPU_CACHED_CACHE_COHERENT))
 187         {
 188                 bRet = PVRSRVSystemSnoopingOfCPUCache();
 189         }
 190         return bRet;
 191 }