drivers/gpu/rogue_m/services/server/devices/rgx/rgxdevice.h

   1 /*************************************************************************/ /*!
   2 @File
   3 @Title          RGX device node header file
   4 @Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
   5 @Description    Header for the RGX device node
   6 @License        Dual MIT/GPLv2
   7
   8 The contents of this file are subject to the MIT license as set out below.
   9
  10 Permission is hereby granted, free of charge, to any person obtaining a copy
  11 of this software and associated documentation files (the "Software"), to deal
  12 in the Software without restriction, including without limitation the rights
  13 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  14 copies of the Software, and to permit persons to whom the Software is
  15 furnished to do so, subject to the following conditions:
  16
  17 The above copyright notice and this permission notice shall be included in
  18 all copies or substantial portions of the Software.
  19
  20 Alternatively, the contents of this file may be used under the terms of
  21 the GNU General Public License Version 2 ("GPL") in which case the provisions
  22 of GPL are applicable instead of those above.
  23
  24 If you wish to allow use of your version of this file only under the terms of
  25 GPL, and not to allow others to use your version of this file under the terms
  26 of the MIT license, indicate your decision by deleting the provisions above
  27 and replace them with the notice and other provisions required by GPL as set
  28 out in the file called "GPL-COPYING" included in this distribution. If you do
  29 not delete the provisions above, a recipient may use your version of this file
  30 under the terms of either the MIT license or GPL.
  31
  32 This License is also included in this distribution in the file called
  33 "MIT-COPYING".
  34
  35 EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
  36 PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
  37 BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  38 PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
  39 COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  40 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  41 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  42 */ /**************************************************************************/
  43
  44 #if !defined(__RGXDEVICE_H__)
  45 #define __RGXDEVICE_H__
  46
  47 #include "img_types.h"
  48 #include "pvrsrv_device_types.h"
  49 #include "mmu_common.h"
  50 #include "rgx_fwif_km.h"
  51 #include "rgx_fwif.h"
  52 #include "rgxscript.h"
  53 #include "cache_external.h"
  54 #include "device.h"
  55 #include "osfunc.h"
  56
  57 typedef struct _RGX_SERVER_COMMON_CONTEXT_ RGX_SERVER_COMMON_CONTEXT;
  58
  59 typedef struct {
  60         DEVMEM_MEMDESC          *psFWFrameworkMemDesc;
  61         IMG_DEV_VIRTADDR        *psMCUFenceAddr;
  62 } RGX_COMMON_CONTEXT_INFO;
  63
  64
  65 /*!
  66  ******************************************************************************
  67  * Device state flags
  68  *****************************************************************************/
  69 #define RGXKM_DEVICE_STATE_ZERO_FREELIST                        (0x1 << 0)              /*!< Zeroing the physical pages of reconstructed free lists */
  70 #define RGXKM_DEVICE_STATE_FTRACE_EN                            (0x1 << 1)              /*!< Used to enable device FTrace thread to consume HWPerf data */
  71 #define RGXKM_DEVICE_STATE_DISABLE_DW_LOGGING_EN        (0x1 << 2)              /*!< Used to disable the Devices Watchdog logging */
  72
  73
  74 /*!
  75  ******************************************************************************
  76  * GPU DVFS Table
  77  *****************************************************************************/
  78
  79 #define RGX_GPU_DVFS_TABLE_SIZE            100                      /* DVFS Table size */
  80 #define RGX_GPU_DVFS_GET_INDEX(clockfreq)  ((clockfreq) / 10000000) /* Assuming different GPU clocks are separated by at least 10MHz
  81                                                                      * WARNING: this macro must be used only with nominal values of
  82                                                                      * the GPU clock speed (the ones provided by the customer code) */
  83 #define RGX_GPU_DVFS_FIRST_CALIBRATION_TIME_US       25000          /* Time required to calibrate a clock frequency the first time */
  84 #define RGX_GPU_DVFS_TRANSITION_CALIBRATION_TIME_US  150000         /* Time required for a recalibration after a DVFS transition */
  85 #define RGX_GPU_DVFS_PERIODIC_CALIBRATION_TIME_US    10000000       /* Time before the next periodic calibration and correlation */
  86
  87 typedef struct _RGX_GPU_DVFS_TABLE_
  88 {
  89         IMG_UINT64 ui64CalibrationCRTimestamp;              /*!< CR timestamp used to calibrate GPU frequencies (beginning of a calibration period) */
  90         IMG_UINT64 ui64CalibrationOSTimestamp;              /*!< OS timestamp used to calibrate GPU frequencies (beginning of a calibration period) */
  91         IMG_UINT64 ui64CalibrationCRTimediff;               /*!< CR timediff used to calibrate GPU frequencies (calibration period) */
  92         IMG_UINT64 ui64CalibrationOSTimediff;               /*!< OS timediff used to calibrate GPU frequencies (calibration period) */
  93         IMG_UINT32 ui32CalibrationPeriod;                   /*!< Threshold used to determine whether the current GPU frequency should be calibrated */
  94         IMG_UINT32 ui32CurrentDVFSId;                       /*!< Current table entry index */
  95         IMG_BOOL   bAccumulatePeriod;                       /*!< Accumulate many consecutive periods to get a better calibration at the end */
  96         IMG_UINT32 aui32DVFSClock[RGX_GPU_DVFS_TABLE_SIZE]; /*!< DVFS clocks table (clocks in Hz) */
  97 } RGX_GPU_DVFS_TABLE;
  98
  99
 100 /*!
 101  ******************************************************************************
 102  * GPU utilisation statistics
 103  *****************************************************************************/
 104
 105 typedef struct _RGXFWIF_GPU_UTIL_STATS_
 106 {
 107         IMG_BOOL   bValid;                /* If TRUE, statistics are valid.
 108                                              FALSE if the driver couldn't get reliable stats. */
 109         IMG_UINT64 ui64GpuStatActiveHigh; /* GPU active high statistic */
 110         IMG_UINT64 ui64GpuStatActiveLow;  /* GPU active low (i.e. TLA active only) statistic */
 111         IMG_UINT64 ui64GpuStatBlocked;    /* GPU blocked statistic */
 112         IMG_UINT64 ui64GpuStatIdle;       /* GPU idle statistic */
 113         IMG_UINT64 ui64GpuStatCumulative; /* Sum of active/blocked/idle stats */
 114
 115 #if defined(GPU_UTIL_SLC_STALL_COUNTERS)
 116         IMG_UINT32 ui32SLCStallsRatio;    /* SLC Read/Write stalls ratio expressed in 0,01% units */
 117 #endif
 118 #if defined(PVR_POWER_ACTOR) && defined (PVR_DVFS)
 119         IMG_UINT32 ui32GpuEnergy;         /* GPU dynamic energy */
 120 #endif
 121 } RGXFWIF_GPU_UTIL_STATS;
 122
 123
 124 typedef struct _RGX_REG_CONFIG_
 125 {
 126         IMG_BOOL                        bEnabled;
 127         RGXFWIF_PWR_EVT         ePowerIslandToPush;
 128         IMG_UINT32              ui32NumRegRecords;
 129 } RGX_REG_CONFIG;
 130
 131 typedef struct _PVRSRV_STUB_PBDESC_ PVRSRV_STUB_PBDESC;
 132
 133 /* there is a corresponding define in rgxapi.h */
 134 #define RGX_MAX_TIMER_QUERIES 16
 135
 136 /*!
 137  ******************************************************************************
 138  * RGX Device info
 139  *****************************************************************************/
 140
 141 typedef struct _PVRSRV_RGXDEV_INFO_
 142 {
 143         PVRSRV_DEVICE_TYPE              eDeviceType;
 144         PVRSRV_DEVICE_CLASS             eDeviceClass;
 145         PVRSRV_DEVICE_NODE              *psDeviceNode;
 146
 147         IMG_UINT8                               ui8VersionMajor;
 148         IMG_UINT8                               ui8VersionMinor;
 149         IMG_UINT32                              ui32CoreConfig;
 150         IMG_UINT32                              ui32CoreFlags;
 151
 152         IMG_BOOL                bFirmwareInitialised;
 153         IMG_BOOL                                bPDPEnabled;
 154
 155         /* Kernel mode linear address of device registers */
 156         IMG_PVOID                               pvRegsBaseKM;
 157
 158         /* FIXME: The alloc for this should go through OSAllocMem in future */
 159         IMG_HANDLE                              hRegMapping;
 160
 161         /* System physical address of device registers*/
 162         IMG_CPU_PHYADDR                 sRegsPhysBase;
 163         /*  Register region size in bytes */
 164         IMG_UINT32                              ui32RegSize;
 165
 166         PVRSRV_STUB_PBDESC              *psStubPBDescListKM;
 167
 168         /* Firmware memory context info */
 169         DEVMEM_CONTEXT                  *psKernelDevmemCtx;
 170         DEVMEM_HEAP                             *psFirmwareHeap;
 171         MMU_CONTEXT                             *psKernelMMUCtx;
 172         IMG_UINT32                              ui32KernelCatBaseIdReg;
 173         IMG_UINT32                              ui32KernelCatBaseId;
 174         IMG_UINT32                              ui32KernelCatBaseReg;
 175         IMG_UINT32                              ui32KernelCatBaseWordSize;
 176         IMG_UINT32                              ui32KernelCatBaseAlignShift;
 177         IMG_UINT32                              ui32KernelCatBaseShift;
 178         IMG_UINT64                              ui64KernelCatBaseMask;
 179
 180         IMG_VOID                                *pvDeviceMemoryHeap;
 181
 182         /* Kernel CCBs */
 183         DEVMEM_MEMDESC                  *apsKernelCCBCtlMemDesc[RGXFWIF_DM_MAX];        /*!< memdesc for kernel CCB control */
 184         RGXFWIF_CCB_CTL                 *apsKernelCCBCtl[RGXFWIF_DM_MAX];                       /*!< kernel CCB control kernel mapping */
 185         DEVMEM_MEMDESC                  *apsKernelCCBMemDesc[RGXFWIF_DM_MAX];           /*!< memdesc for kernel CCB */
 186         IMG_UINT8                               *apsKernelCCB[RGXFWIF_DM_MAX];                          /*!< kernel CCB kernel mapping */
 187
 188         /* Firmware CCBs */
 189         DEVMEM_MEMDESC                  *apsFirmwareCCBCtlMemDesc[RGXFWIF_DM_MAX];      /*!< memdesc for Firmware CCB control */
 190         RGXFWIF_CCB_CTL                 *apsFirmwareCCBCtl[RGXFWIF_DM_MAX];                     /*!< kernel CCB control Firmware mapping */
 191         DEVMEM_MEMDESC                  *apsFirmwareCCBMemDesc[RGXFWIF_DM_MAX];         /*!< memdesc for Firmware CCB */
 192         IMG_UINT8                               *apsFirmwareCCB[RGXFWIF_DM_MAX];                                /*!< kernel CCB Firmware mapping */
 193
 194         /*
 195                 if we don't preallocate the pagetables we must
 196                 insert newly allocated page tables dynamically
 197         */
 198         IMG_VOID                                *pvMMUContextList;
 199
 200         IMG_UINT32                              ui32ClkGateStatusReg;
 201         IMG_UINT32                              ui32ClkGateStatusMask;
 202         RGX_SCRIPTS                             *psScripts;
 203
 204         DEVMEM_MEMDESC                  *psRGXFWCodeMemDesc;
 205         DEVMEM_EXPORTCOOKIE             sRGXFWCodeExportCookie;
 206
 207         DEVMEM_MEMDESC                  *psRGXFWDataMemDesc;
 208         DEVMEM_EXPORTCOOKIE             sRGXFWDataExportCookie;
 209
 210         DEVMEM_MEMDESC                  *psRGXFWCorememMemDesc;
 211         DEVMEM_EXPORTCOOKIE             sRGXFWCorememExportCookie;
 212
 213         DEVMEM_MEMDESC                  *psRGXFWIfTraceBufCtlMemDesc;
 214         RGXFWIF_TRACEBUF                *psRGXFWIfTraceBuf;
 215
 216         DEVMEM_MEMDESC                  *psRGXFWIfHWRInfoBufCtlMemDesc;
 217         RGXFWIF_HWRINFOBUF              *psRGXFWIfHWRInfoBuf;
 218
 219         DEVMEM_MEMDESC                  *psRGXFWIfGpuUtilFWCbCtlMemDesc;
 220         RGXFWIF_GPU_UTIL_FWCB   *psRGXFWIfGpuUtilFWCb;
 221
 222         DEVMEM_MEMDESC                  *psRGXFWIfHWPerfBufMemDesc;
 223         IMG_BYTE                                *psRGXFWIfHWPerfBuf;
 224         IMG_UINT32                              ui32RGXFWIfHWPerfBufSize; /* in bytes */
 225
 226         DEVMEM_MEMDESC                  *psRGXFWIfCorememDataStoreMemDesc;
 227
 228         DEVMEM_MEMDESC                  *psRGXFWIfRegCfgMemDesc;
 229
 230         DEVMEM_MEMDESC                  *psRGXFWIfHWPerfCountersMemDesc;
 231         DEVMEM_EXPORTCOOKIE     sRGXFWHWPerfCountersExportCookie;
 232         DEVMEM_MEMDESC                  *psRGXFWIfInitMemDesc;
 233
 234         DEVMEM_MEMDESC                  *psRGXFWIfRuntimeCfgMemDesc;
 235         RGXFWIF_RUNTIME_CFG             *psRGXFWIfRuntimeCfg;
 236
 237 #if defined(RGXFW_ALIGNCHECKS)
 238         DEVMEM_MEMDESC                  *psRGXFWAlignChecksMemDesc;
 239 #endif
 240
 241         DEVMEM_MEMDESC                  *psRGXFWSigTAChecksMemDesc;
 242         IMG_UINT32                              ui32SigTAChecksSize;
 243
 244         DEVMEM_MEMDESC                  *psRGXFWSig3DChecksMemDesc;
 245         IMG_UINT32                              ui32Sig3DChecksSize;
 246
 247 #if defined(RGX_FEATURE_RAY_TRACING)
 248         DEVMEM_MEMDESC                  *psRGXFWSigRTChecksMemDesc;
 249         IMG_UINT32                              ui32SigRTChecksSize;
 250
 251         DEVMEM_MEMDESC                  *psRGXFWSigSHChecksMemDesc;
 252         IMG_UINT32                              ui32SigSHChecksSize;
 253 #endif
 254
 255         IMG_VOID                                *pvLISRData;
 256         IMG_VOID                                *pvMISRData;
 257         IMG_VOID                                *pvAPMISRData;
 258
 259         DEVMEM_MEMDESC                  *psRGXFaultAddressMemDesc;
 260
 261 #if defined(FIX_HW_BRN_37200)
 262         DEVMEM_MEMDESC                  *psRGXFWHWBRN37200MemDesc;
 263 #endif
 264
 265 #if defined(RGX_FEATURE_SLC_VIVT)
 266         DEVMEM_MEMDESC                  *psSLC3FenceMemDesc;
 267 #endif
 268
 269 #if defined (PDUMP)
 270         IMG_BOOL                                abDumpedKCCBCtlAlready[RGXFWIF_DM_MAX];
 271
 272 #endif
 273
 274         /*! Handles to the lock and stream objects used to transport
 275          * HWPerf data to user side clients. See RGXHWPerfInit() RGXHWPerfDeinit().
 276          * Set during initialisation if the application hint turns bit 7
 277          * 'Enable HWPerf' on in the ConfigFlags sent to the FW. FW stores this
 278          * bit in the RGXFW_CTL.ui32StateFlags member. They may also get
 279          * set by the API RGXCtrlHWPerf(). Thus these members may be 0 if HWPerf is
 280          * not enabled as these members are created on demand and destroyed at
 281          * driver unload.
 282          */
 283         POS_LOCK                                hLockHWPerfStream;
 284         IMG_HANDLE                              hHWPerfStream;
 285 #if defined(SUPPORT_GPUTRACE_EVENTS)
 286         IMG_HANDLE                              hGPUTraceCmdCompleteHandle;
 287         IMG_BOOL                                bFTraceGPUEventsEnabled;
 288         IMG_HANDLE                              hGPUTraceTLConnection;
 289         IMG_HANDLE                              hGPUTraceTLStream;
 290         IMG_UINT64                              ui64LastSampledTimeCorrOSTimeStamp;
 291 #endif
 292
 293         /* If we do 10 deferred memory allocations per second, then the ID would warp around after 13 years */
 294         IMG_UINT32                              ui32ZSBufferCurrID;     /*!< ID assigned to the next deferred devmem allocation */
 295         IMG_UINT32                              ui32FreelistCurrID;     /*!< ID assigned to the next freelist */
 296         IMG_UINT32                              ui32RPMFreelistCurrID;  /*!< ID assigned to the next RPM freelist */
 297
 298         POS_LOCK                                hLockZSBuffer;          /*!< Lock to protect simultaneous access to ZSBuffers */
 299         DLLIST_NODE                             sZSBufferHead;          /*!< List of on-demand ZSBuffers */
 300         POS_LOCK                                hLockFreeList;          /*!< Lock to protect simultaneous access to Freelists */
 301         DLLIST_NODE                             sFreeListHead;          /*!< List of growable Freelists */
 302         POS_LOCK                                hLockRPMFreeList;       /*!< Lock to protect simultaneous access to RPM Freelists */
 303         DLLIST_NODE                             sRPMFreeListHead;       /*!< List of growable RPM Freelists */
 304         PSYNC_PRIM_CONTEXT              hSyncPrimContext;
 305         PVRSRV_CLIENT_SYNC_PRIM *psPowSyncPrim;
 306
 307         IMG_UINT32                              ui32ActivePMReqOk;
 308         IMG_UINT32                              ui32ActivePMReqDenied;
 309         IMG_UINT32                              ui32ActivePMReqTotal;
 310
 311         IMG_HANDLE                              hProcessQueuesMISR;
 312
 313         IMG_UINT32                              ui32DeviceFlags;        /*!< Flags to track general device state  */
 314
 315         /* Poll data for detecting firmware fatal errors */
 316         IMG_UINT32  aui32CrLastPollAddr[RGXFW_THREAD_NUM];
 317         IMG_UINT32  ui32KCCBCmdsExecutedLastTime;
 318         IMG_BOOL    bKCCBCmdsWaitingLastTime;
 319         IMG_UINT32  ui32GEOTimeoutsLastTime;
 320
 321         /* Client stall detection */
 322         IMG_BOOL        bStalledClient;
 323
 324         /* Timer Queries */
 325         IMG_UINT32        ui32ActiveQueryId;       /*!< id of the active line */
 326         IMG_BOOL          bSaveStart;              /*!< save the start time of the next kick on the device*/
 327         IMG_BOOL          bSaveEnd;                /*!< save the end time of the next kick on the device*/
 328
 329         DEVMEM_MEMDESC    * psStartTimeMemDesc;    /*!< memdesc for Start Times */
 330         RGXFWIF_TIMESTAMP * pasStartTimeById;      /*!< CPU mapping of the above */
 331
 332         DEVMEM_MEMDESC    * psEndTimeMemDesc;      /*!< memdesc for End Timer */
 333         RGXFWIF_TIMESTAMP * pasEndTimeById;        /*!< CPU mapping of the above */
 334
 335         IMG_UINT32        aui32ScheduledOnId[RGX_MAX_TIMER_QUERIES];      /*!< kicks Scheduled on QueryId */
 336         DEVMEM_MEMDESC    * psCompletedMemDesc;    /*!< kicks Completed on QueryId */
 337         IMG_UINT32        * pui32CompletedById;    /*!< CPU mapping of the above */
 338
 339         /* GPU DVFS Table */
 340         RGX_GPU_DVFS_TABLE  *psGpuDVFSTable;
 341
 342         /* Pointer to function returning the GPU utilisation statistics since the last
 343          * time the function was called. Supports different users at the same time.
 344          *
 345          * psReturnStats [out]: GPU utilisation statistics (active high/active low/idle/blocked)
 346          *                      in microseconds since the last time the function was called
 347          *                      by a specific user (identified by hGpuUtilUser)
 348          *
 349          * Returns PVRSRV_OK in case the call completed without errors,
 350          * some other value otherwise.
 351          */
 352         PVRSRV_ERROR (*pfnGetGpuUtilStats) (PVRSRV_DEVICE_NODE *psDeviceNode,
 353                                             IMG_HANDLE hGpuUtilUser,
 354                                             RGXFWIF_GPU_UTIL_STATS *psReturnStats);
 355
 356         PVRSRV_ERROR (*pfnRegisterGpuUtilStats) (IMG_HANDLE *phGpuUtilUser);
 357         PVRSRV_ERROR (*pfnUnregisterGpuUtilStats) (IMG_HANDLE hGpuUtilUser);
 358
 359         POS_LOCK    hGPUUtilLock;
 360
 361         /* Register configuration */
 362         RGX_REG_CONFIG          sRegCongfig;
 363
 364         IMG_BOOL                                bIgnoreFurtherIRQs;
 365         DLLIST_NODE                             sMemoryContextList;
 366
 367         POSWR_LOCK              hRenderCtxListLock;
 368         POSWR_LOCK              hComputeCtxListLock;
 369         POSWR_LOCK              hTransferCtxListLock;
 370         POSWR_LOCK              hRaytraceCtxListLock;
 371         POSWR_LOCK              hMemoryCtxListLock;
 372
 373         /* Linked lists of contexts on this device */
 374         DLLIST_NODE             sRenderCtxtListHead;
 375         DLLIST_NODE             sComputeCtxtListHead;
 376         DLLIST_NODE             sTransferCtxtListHead;
 377         DLLIST_NODE             sRaytraceCtxtListHead;
 378
 379         DLLIST_NODE             sCommonCtxtListHead;
 380         IMG_UINT32                      ui32CommonCtxtCurrentID;                        /*!< ID assigned to the next common context */
 381
 382 #if defined(SUPPORT_PAGE_FAULT_DEBUG)
 383         POS_LOCK                                hDebugFaultInfoLock;            /*!< Lock to protect the debug fault info list */
 384         POS_LOCK                                hMMUCtxUnregLock;       /*!< Lock to protect list of unregistered MMU contexts */
 385 #endif
 386 } PVRSRV_RGXDEV_INFO;
 387
 388
 389
 390 typedef struct _RGX_TIMING_INFORMATION_
 391 {
 392         /*! GPU default core clock speed in Hz */
 393         IMG_UINT32                      ui32CoreClockSpeed;
 394
 395         /*! Active Power Management: GPU actively requests the host driver to be powered off */
 396         IMG_BOOL                        bEnableActivePM;
 397
 398         /*! Enable the GPU to power off internal Power Islands independently from the host driver */
 399         IMG_BOOL                        bEnableRDPowIsland;
 400
 401         /*! Active Power Management: Delay between the GPU idle and the request to the host */
 402         IMG_UINT32                      ui32ActivePMLatencyms;
 403
 404 } RGX_TIMING_INFORMATION;
 405
 406 typedef struct _RGX_DATA_
 407 {
 408         /*! Timing information */
 409         RGX_TIMING_INFORMATION  *psRGXTimingInfo;
 410         IMG_BOOL bHasTDMetaCodePhysHeap;
 411         IMG_UINT32 uiTDMetaCodePhysHeapID;
 412         IMG_BOOL bHasTDSecureBufPhysHeap;
 413         IMG_UINT32 uiTDSecureBufPhysHeapID;
 414 } RGX_DATA;
 415
 416
 417 /*
 418         RGX PDUMP register bank name (prefix)
 419 */
 420 #define RGX_PDUMPREG_NAME               "RGXREG"
 421
 422 #endif /* __RGXDEVICE_H__ */