drivers/gpu/rogue_m/services/include/rgx_fwif_shared.h

   1 /*************************************************************************/ /*!
   2 @File
   3 @Title          RGX firmware interface structures
   4 @Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
   5 @Description    RGX firmware interface structures shared by both host client
   6                 and host server
   7 @License        Dual MIT/GPLv2
   8
   9 The contents of this file are subject to the MIT license as set out below.
  10
  11 Permission is hereby granted, free of charge, to any person obtaining a copy
  12 of this software and associated documentation files (the "Software"), to deal
  13 in the Software without restriction, including without limitation the rights
  14 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  15 copies of the Software, and to permit persons to whom the Software is
  16 furnished to do so, subject to the following conditions:
  17
  18 The above copyright notice and this permission notice shall be included in
  19 all copies or substantial portions of the Software.
  20
  21 Alternatively, the contents of this file may be used under the terms of
  22 the GNU General Public License Version 2 ("GPL") in which case the provisions
  23 of GPL are applicable instead of those above.
  24
  25 If you wish to allow use of your version of this file only under the terms of
  26 GPL, and not to allow others to use your version of this file under the terms
  27 of the MIT license, indicate your decision by deleting the provisions above
  28 and replace them with the notice and other provisions required by GPL as set
  29 out in the file called "GPL-COPYING" included in this distribution. If you do
  30 not delete the provisions above, a recipient may use your version of this file
  31 under the terms of either the MIT license or GPL.
  32
  33 This License is also included in this distribution in the file called
  34 "MIT-COPYING".
  35
  36 EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
  37 PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
  38 BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  39 PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
  40 COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  41 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  42 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  43 */ /**************************************************************************/
  44
  45 #if !defined (__RGX_FWIF_SHARED_H__)
  46 #define __RGX_FWIF_SHARED_H__
  47
  48 #include "img_types.h"
  49 #include "rgx_common.h"
  50 #include "devicemem_typedefs.h"
  51
  52
  53 /*!
  54  ******************************************************************************
  55  * Device state flags
  56  *****************************************************************************/
  57 #define RGXKMIF_DEVICE_STATE_ZERO_FREELIST                      (0x1 << 0)              /*!< Zeroing the physical pages of reconstructed free lists */
  58 #define RGXKMIF_DEVICE_STATE_FTRACE_EN                          (0x1 << 1)              /*!< Used to enable device FTrace thread to consume HWPerf data */
  59 #define RGXKMIF_DEVICE_STATE_DISABLE_DW_LOGGING_EN      (0x1 << 2)              /*!< Used to disable the Devices Watchdog logging */
  60
  61 /* Required memory alignment for 64-bit variables accessible by Meta
  62   (the gcc meta aligns 64-bit vars to 64-bit; therefore, mem shared between
  63    the host and meta that contains 64-bit vars has to maintain this aligment)*/
  64 #define RGXFWIF_FWALLOC_ALIGN   sizeof(IMG_UINT64)
  65
  66 typedef struct _RGXFWIF_DEV_VIRTADDR_
  67 {
  68         IMG_UINT32      ui32Addr;
  69 } RGXFWIF_DEV_VIRTADDR;
  70
  71 typedef struct _RGXFWIF_DMA_ADDR_
  72 {
  73         IMG_DEV_VIRTADDR        RGXFW_ALIGN psDevVirtAddr;
  74
  75 #if defined(RGX_FIRMWARE)
  76         IMG_PBYTE               pbyFWAddr;
  77 #else
  78         RGXFWIF_DEV_VIRTADDR    pbyFWAddr;
  79 #endif
  80 } UNCACHED_ALIGN RGXFWIF_DMA_ADDR;
  81
  82 typedef IMG_UINT8       RGXFWIF_CCCB;
  83
  84 #if defined(RGX_FIRMWARE)
  85 /* Compiling the actual firmware - use a fully typed pointer */
  86 typedef RGXFWIF_CCCB                                    *PRGXFWIF_CCCB;
  87 typedef struct _RGXFWIF_CCCB_CTL_               *PRGXFWIF_CCCB_CTL;
  88 typedef struct _RGXFWIF_RENDER_TARGET_  *PRGXFWIF_RENDER_TARGET;
  89 typedef struct _RGXFWIF_HWRTDATA_               *PRGXFWIF_HWRTDATA;
  90 typedef struct _RGXFWIF_FREELIST_               *PRGXFWIF_FREELIST;
  91 typedef struct _RGXFWIF_RAY_FRAME_DATA_ *PRGXFWIF_RAY_FRAME_DATA;
  92 typedef struct _RGXFWIF_RPM_FREELIST_   *PRGXFWIF_RPM_FREELIST;
  93 typedef struct _RGXFWIF_RTA_CTL_                *PRGXFWIF_RTA_CTL;
  94 typedef IMG_UINT32                                              *PRGXFWIF_UFO_ADDR;
  95 typedef struct _RGXFWIF_CLEANUP_CTL_    *PRGXFWIF_CLEANUP_CTL;
  96 #else
  97 /* Compiling the host driver - use a firmware device virtual pointer */
  98 typedef RGXFWIF_DEV_VIRTADDR    PRGXFWIF_CCCB;
  99 typedef RGXFWIF_DEV_VIRTADDR    PRGXFWIF_CCCB_CTL;
 100 typedef RGXFWIF_DEV_VIRTADDR    PRGXFWIF_RENDER_TARGET;
 101 typedef RGXFWIF_DEV_VIRTADDR    PRGXFWIF_HWRTDATA;
 102 typedef RGXFWIF_DEV_VIRTADDR    PRGXFWIF_FREELIST;
 103 typedef RGXFWIF_DEV_VIRTADDR    PRGXFWIF_RAY_FRAME_DATA;
 104 typedef RGXFWIF_DEV_VIRTADDR    PRGXFWIF_RPM_FREELIST;
 105 typedef RGXFWIF_DEV_VIRTADDR    PRGXFWIF_RTA_CTL;
 106 typedef RGXFWIF_DEV_VIRTADDR    PRGXFWIF_UFO_ADDR;
 107 typedef RGXFWIF_DEV_VIRTADDR    PRGXFWIF_CLEANUP_CTL;
 108 #endif /* RGX_FIRMWARE */
 109
 110
 111 /* FIXME PRGXFWIF_UFO_ADDR and RGXFWIF_UFO should move back into rgx_fwif_client.h */
 112 typedef struct _RGXFWIF_UFO_
 113 {
 114         PRGXFWIF_UFO_ADDR       puiAddrUFO;
 115         IMG_UINT32                      ui32Value;
 116 } RGXFWIF_UFO;
 117
 118
 119 /*!
 120         Last reset reason for a context.
 121 */
 122 typedef enum _RGXFWIF_CONTEXT_RESET_REASON_
 123 {
 124         RGXFWIF_CONTEXT_RESET_REASON_NONE                                       = 0,    /*!< No reset reason recorded */
 125         RGXFWIF_CONTEXT_RESET_REASON_GUILTY_LOCKUP                      = 1,    /*!< Caused a reset due to locking up */
 126         RGXFWIF_CONTEXT_RESET_REASON_INNOCENT_LOCKUP            = 2,    /*!< Affected by another context locking up */
 127         RGXFWIF_CONTEXT_RESET_REASON_GUILTY_OVERRUNING          = 3,    /*!< Overran the global deadline */
 128         RGXFWIF_CONTEXT_RESET_REASON_INNOCENT_OVERRUNING        = 4,    /*!< Affected by another context overrunning */
 129 } RGXFWIF_CONTEXT_RESET_REASON;
 130
 131
 132 /*!
 133         HWRTData state the render is in
 134 */
 135 typedef enum
 136 {
 137         RGXFWIF_RTDATA_STATE_NONE = 0,
 138         RGXFWIF_RTDATA_STATE_KICKTA,
 139         RGXFWIF_RTDATA_STATE_KICKTAFIRST,
 140         RGXFWIF_RTDATA_STATE_TAFINISHED,
 141         RGXFWIF_RTDATA_STATE_KICK3D,
 142         RGXFWIF_RTDATA_STATE_3DFINISHED,
 143         RGXFWIF_RTDATA_STATE_TAOUTOFMEM,
 144         RGXFWIF_RTDATA_STATE_PARTIALRENDERFINISHED,
 145         RGXFWIF_RTDATA_STATE_HWR                                        /*!< In case of HWR, we can't set the RTDATA state to NONE,
 146                                                                                                          as this will cause any TA to become a first TA.
 147                                                                                                          To ensure all related TA's are skipped, we use the HWR state */
 148 } RGXFWIF_RTDATA_STATE;
 149
 150 typedef struct _RGXFWIF_CLEANUP_CTL_
 151 {
 152         IMG_UINT32                              ui32SubmittedCommands;  /*!< Number of commands received by the FW */
 153         IMG_UINT32                              ui32ExecutedCommands;   /*!< Number of commands executed by the FW */
 154 } UNCACHED_ALIGN RGXFWIF_CLEANUP_CTL;
 155
 156
 157 /*!
 158  ******************************************************************************
 159  * Client CCB control for RGX
 160  *****************************************************************************/
 161 typedef struct _RGXFWIF_CCCB_CTL_
 162 {
 163         IMG_UINT32                              ui32WriteOffset;        /*!< write offset into array of commands (MUST be aligned to 16 bytes!) */
 164         IMG_UINT32                              ui32ReadOffset;         /*!< read offset into array of commands */
 165         IMG_UINT32                              ui32DepOffset;          /*!< Dependency offset */
 166         IMG_UINT32                              ui32WrapMask;           /*!< Offset wrapping mask (Total capacity of the CCB - 1) */
 167 } UNCACHED_ALIGN RGXFWIF_CCCB_CTL;
 168
 169 typedef enum
 170 {
 171         RGXFW_LOCAL_FREELIST = 0,
 172         RGXFW_GLOBAL_FREELIST = 1,
 173 #if defined(SUPPORT_MMU_FREELIST)
 174         RGXFW_MMU_FREELIST = 2,
 175 #endif
 176         RGXFW_MAX_FREELISTS
 177 } RGXFW_FREELIST_TYPE;
 178
 179 typedef struct _RGXFWIF_RTA_CTL_
 180 {
 181         IMG_UINT32                              ui32RenderTargetIndex;          //Render number
 182         IMG_UINT32                              ui32CurrentRenderTarget;        //index in RTA
 183         IMG_UINT32                              ui32ActiveRenderTargets;        //total active RTs
 184         IMG_UINT32                              ui32CumulActiveRenderTargets;   //total active RTs from the first TA kick, for OOM
 185 #if defined(RGX_FIRMWARE)
 186         IMG_UINT32                              *paui32ValidRenderTargets;      //Array of valid RT indices
 187         IMG_UINT32                              *paui32NumRenders;  //Array of number of occurred partial renders per render target
 188 #else
 189         RGXFWIF_DEV_VIRTADDR                    paui32ValidRenderTargets;  //Array of valid RT indices
 190         RGXFWIF_DEV_VIRTADDR                    paui32NumRenders;  //Array of number of occurred partial renders per render target
 191 #endif
 192         IMG_UINT16                              ui16MaxRTs;   //Number of render targets in the array
 193 } UNCACHED_ALIGN RGXFWIF_RTA_CTL;
 194
 195 typedef struct _RGXFWIF_FREELIST_
 196 {
 197         IMG_DEV_VIRTADDR        RGXFW_ALIGN psFreeListDevVAddr;
 198         IMG_UINT64                      RGXFW_ALIGN ui64CurrentDevVAddr;
 199         IMG_UINT32                      ui32CurrentStackTop;
 200         IMG_UINT32                      ui32MaxPages;
 201         IMG_UINT32                      ui32GrowPages;
 202         IMG_UINT32                      ui32CurrentPages;
 203         IMG_UINT32                      ui32AllocatedPageCount;
 204         IMG_UINT32                      ui32AllocatedMMUPageCount;
 205         IMG_UINT32                      ui32HWRCounter;
 206         IMG_UINT32                      ui32FreeListID;
 207         IMG_BOOL                        bGrowPending;
 208 } UNCACHED_ALIGN RGXFWIF_FREELIST;
 209
 210 #if defined(RGX_FEATURE_RAY_TRACING)
 211 typedef enum
 212 {
 213         RGXFW_RPM_SHF_FREELIST = 0,
 214         RGXFW_RPM_SHG_FREELIST = 1,
 215 } RGXFW_RPM_FREELIST_TYPE;
 216
 217 #define         RGXFW_MAX_RPM_FREELISTS         (2)
 218
 219 typedef struct _RGXFWIF_RPM_FREELIST_
 220 {
 221         IMG_DEV_VIRTADDR        RGXFW_ALIGN sFreeListDevVAddr;          /*!< device base address */
 222         IMG_DEV_VIRTADDR        RGXFW_ALIGN sRPMPageListDevVAddr;       /*!< device base address for RPM pages in-use */
 223         IMG_UINT32                      sSyncAddr;                              /*!< Free list sync object for OOM event */
 224         IMG_UINT32                      ui32MaxPages;                   /*!< maximum size */
 225         IMG_UINT32                      ui32GrowPages;                  /*!< grow size = maximum pages which may be added later */
 226         IMG_UINT32                      ui32CurrentPages;               /*!< number of pages */
 227         IMG_UINT32                      ui32ReadOffset;                 /*!< head: where to read alloc'd pages */
 228         IMG_UINT32                      ui32WriteOffset;                /*!< tail: where to write de-alloc'd pages */
 229         IMG_BOOL                        bReadToggle;                    /*!< toggle bit for circular buffer */
 230         IMG_BOOL                        bWriteToggle;
 231         IMG_UINT32                      ui32AllocatedPageCount; /*!< TODO: not sure yet if this is useful */
 232         IMG_UINT32                      ui32HWRCounter;
 233         IMG_UINT32                      ui32FreeListID;                 /*!< unique ID per device, e.g. rolling counter */
 234         IMG_BOOL                        bGrowPending;                   /*!< FW is waiting for host to grow the freelist */
 235 } UNCACHED_ALIGN RGXFWIF_RPM_FREELIST;
 236
 237 typedef struct _RGXFWIF_RAY_FRAME_DATA_
 238 {
 239         /* state manager for shared state between vertex and ray processing */
 240
 241         /* TODO: not sure if this will be useful, link it here for now */
 242         IMG_UINT32              sRPMFreeLists[RGXFW_MAX_RPM_FREELISTS];
 243
 244         IMG_BOOL                bAbortOccurred;
 245
 246         /* cleanup state.
 247          * Both the SHG and RTU must complete or discard any outstanding work
 248          * which references this frame data.
 249          */
 250         RGXFWIF_CLEANUP_CTL             sCleanupStateSHG;
 251         RGXFWIF_CLEANUP_CTL             sCleanupStateRTU;
 252         IMG_UINT32                              ui32CleanupStatus;
 253 #define HWFRAMEDATA_SHG_CLEAN   (1 << 0)
 254 #define HWFRAMEDATA_RTU_CLEAN   (1 << 1)
 255
 256 } UNCACHED_ALIGN RGXFWIF_RAY_FRAME_DATA;
 257 #endif
 258
 259 typedef struct _RGXFWIF_RENDER_TARGET_
 260 {
 261         IMG_DEV_VIRTADDR        RGXFW_ALIGN psVHeapTableDevVAddr; /*!< VHeap Data Store */
 262         IMG_BOOL                        bTACachesNeedZeroing;                     /*!< Whether RTC and TPC caches (on mem) need to be zeroed on next first TA kick */
 263
 264 } UNCACHED_ALIGN RGXFWIF_RENDER_TARGET;
 265
 266
 267 typedef struct _RGXFWIF_HWRTDATA_
 268 {
 269         RGXFWIF_RTDATA_STATE    eState;
 270
 271         IMG_UINT32                              ui32NumPartialRenders; /*!< Number of partial renders. Used to setup ZLS bits correctly */
 272         IMG_DEV_VIRTADDR                RGXFW_ALIGN psPMMListDevVAddr; /*!< MList Data Store */
 273
 274 #if defined(RGX_FEATURE_SCALABLE_TE_ARCH)
 275         IMG_UINT64                              RGXFW_ALIGN ui64VCECatBase[4];
 276         IMG_UINT64                              RGXFW_ALIGN ui64VCELastCatBase[4];
 277         IMG_UINT64                              RGXFW_ALIGN ui64TECatBase[4];
 278         IMG_UINT64                              RGXFW_ALIGN ui64TELastCatBase[4];
 279 #else
 280         IMG_UINT64                              RGXFW_ALIGN ui64VCECatBase;
 281         IMG_UINT64                              RGXFW_ALIGN ui64VCELastCatBase;
 282         IMG_UINT64                              RGXFW_ALIGN ui64TECatBase;
 283         IMG_UINT64                              RGXFW_ALIGN ui64TELastCatBase;
 284 #endif
 285         IMG_UINT64                              RGXFW_ALIGN ui64AlistCatBase;
 286         IMG_UINT64                              RGXFW_ALIGN ui64AlistLastCatBase;
 287
 288 #if defined(SUPPORT_VFP)
 289         IMG_DEV_VIRTADDR                RGXFW_ALIGN sVFPPageTableAddr;
 290 #endif
 291         IMG_UINT64                              RGXFW_ALIGN ui64PMAListStackPointer;
 292         IMG_UINT32                              ui32PMMListStackPointer;
 293
 294         PRGXFWIF_FREELIST               RGXFW_ALIGN apsFreeLists[RGXFW_MAX_FREELISTS];
 295         IMG_UINT32                              aui32FreeListHWRSnapshot[RGXFW_MAX_FREELISTS];
 296
 297         PRGXFWIF_RENDER_TARGET  psParentRenderTarget;
 298
 299         RGXFWIF_CLEANUP_CTL             sTACleanupState;
 300         RGXFWIF_CLEANUP_CTL             s3DCleanupState;
 301         IMG_UINT32                              ui32CleanupStatus;
 302 #define HWRTDATA_TA_CLEAN       (1 << 0)
 303 #define HWRTDATA_3D_CLEAN       (1 << 1)
 304
 305         PRGXFWIF_RTA_CTL                psRTACtl;
 306
 307         IMG_UINT32                              bHasLastTA;
 308         IMG_BOOL                                bPartialRendered;
 309
 310         IMG_UINT32                              ui32PPPScreen;
 311         IMG_UINT32                              ui32PPPGridOffset;
 312         IMG_UINT64                              RGXFW_ALIGN ui64PPPMultiSampleCtl;
 313         IMG_UINT32                              ui32TPCStride;
 314         IMG_DEV_VIRTADDR                RGXFW_ALIGN sTailPtrsDevVAddr;
 315         IMG_UINT32                              ui32TPCSize;
 316         IMG_UINT32                              ui32TEScreen;
 317         IMG_UINT32                              ui32MTileStride;
 318         IMG_UINT32                              ui32TEAA;
 319         IMG_UINT32                              ui32TEMTILE1;
 320         IMG_UINT32                              ui32TEMTILE2;
 321         IMG_UINT32                              ui32ISPMergeLowerX;
 322         IMG_UINT32                              ui32ISPMergeLowerY;
 323         IMG_UINT32                              ui32ISPMergeUpperX;
 324         IMG_UINT32                              ui32ISPMergeUpperY;
 325         IMG_UINT32                              ui32ISPMergeScaleX;
 326         IMG_UINT32                              ui32ISPMergeScaleY;
 327 } UNCACHED_ALIGN RGXFWIF_HWRTDATA;
 328
 329 typedef enum
 330 {
 331         RGXFWIF_ZSBUFFER_UNBACKED = 0,
 332         RGXFWIF_ZSBUFFER_BACKED,
 333         RGXFWIF_ZSBUFFER_BACKING_PENDING,
 334         RGXFWIF_ZSBUFFER_UNBACKING_PENDING,
 335 }RGXFWIF_ZSBUFFER_STATE;
 336
 337 typedef struct _RGXFWIF_ZSBUFFER_
 338 {
 339         IMG_UINT32                              ui32ZSBufferID;                         /*!< Buffer ID*/
 340         IMG_BOOL                                bOnDemand;                                      /*!< Needs On-demand ZS Buffer allocation */
 341         RGXFWIF_ZSBUFFER_STATE  eState;                                         /*!< Z/S-Buffer state */
 342         RGXFWIF_CLEANUP_CTL             sCleanupState;                          /*!< Cleanup state */
 343 } UNCACHED_ALIGN RGXFWIF_FWZSBUFFER;
 344
 345 /* Number of BIF tiling configurations / heaps */
 346 #define RGXFWIF_NUM_BIF_TILING_CONFIGS 4
 347
 348 /*!
 349  *****************************************************************************
 350  * RGX Compatibility checks
 351  *****************************************************************************/
 352 /* WARNING: RGXFWIF_COMPCHECKS_BVNC_V_LEN_MAX can be increased only and
 353                 always equal to (N * sizeof(IMG_UINT32) - 1) */
 354 #define RGXFWIF_COMPCHECKS_BVNC_V_LEN_MAX 3 /* WARNING: Do not change this macro without changing
 355                         accesses from dword to byte in function rgx_bvnc_packed() */
 356
 357 /* WARNING: Whenever the layout of RGXFWIF_COMPCHECKS_BVNC is a subject of change,
 358         following define should be increased by 1 to indicate to compatibility logic,
 359         that layout has changed */
 360 #define RGXFWIF_COMPCHECKS_LAYOUT_VERSION 1
 361
 362 typedef struct _RGXFWIF_COMPCHECKS_BVNC_
 363 {
 364         IMG_UINT32      ui32LayoutVersion; /* WARNING: This field must be defined as first one in this structure */
 365         IMG_UINT32  ui32VLenMax;
 366         IMG_UINT32      ui32BNC;
 367         IMG_CHAR        aszV[RGXFWIF_COMPCHECKS_BVNC_V_LEN_MAX + 1];
 368 } UNCACHED_ALIGN RGXFWIF_COMPCHECKS_BVNC;
 369
 370 #define RGXFWIF_COMPCHECKS_BVNC_DECLARE_AND_INIT(name) RGXFWIF_COMPCHECKS_BVNC name = { RGXFWIF_COMPCHECKS_LAYOUT_VERSION, RGXFWIF_COMPCHECKS_BVNC_V_LEN_MAX }
 371 #define RGXFWIF_COMPCHECKS_BVNC_INIT(name) do { (name).ui32LayoutVersion = RGXFWIF_COMPCHECKS_LAYOUT_VERSION; \
 372                                                                                                 (name).ui32VLenMax = RGXFWIF_COMPCHECKS_BVNC_V_LEN_MAX; } while (0)
 373
 374 typedef struct _RGXFWIF_COMPCHECKS_
 375 {
 376         RGXFWIF_COMPCHECKS_BVNC         sHWBVNC;                        /*!< hardware BNC (from the RGX registers) */
 377         RGXFWIF_COMPCHECKS_BVNC         sFWBVNC;                        /*!< firmware BNC */
 378         IMG_UINT32                                      ui32METAVersion;
 379         IMG_UINT32                                      ui32DDKVersion;         /*!< software DDK version */
 380         IMG_UINT32                                      ui32DDKBuild;           /*!< software DDK build no. */
 381         IMG_UINT32                                      ui32BuildOptions;       /*!< build options bit-field */
 382         IMG_BOOL                                        bUpdated;                       /*!< Information is valid */
 383 } UNCACHED_ALIGN RGXFWIF_COMPCHECKS;
 384
 385
 386 #define GET_CCB_SPACE(WOff, ROff, CCBSize) \
 387         ((((ROff) - (WOff)) + ((CCBSize) - 1)) & ((CCBSize) - 1))
 388
 389 #define UPDATE_CCB_OFFSET(Off, PacketSize, CCBSize) \
 390         (Off) = (((Off) + (PacketSize)) & ((CCBSize) - 1))
 391
 392 #define RESERVED_CCB_SPACE              (sizeof(IMG_UINT32))
 393
 394
 395 /* Defines relating to the per-context CCBs */
 396 #define RGX_CCB_SIZE_LOG2                       (16) /* 64kB */
 397 #define RGX_CCB_ALLOCGRAN                       (64)
 398 #define RGX_CCB_TYPE_TASK                       (1 << 31)
 399 #define RGX_CCB_FWALLOC_ALIGN(size)     (((size) + (RGXFWIF_FWALLOC_ALIGN-1)) & ~(RGXFWIF_FWALLOC_ALIGN - 1))
 400
 401 /*!
 402  ******************************************************************************
 403  * Client CCB commands for RGX
 404  *****************************************************************************/
 405 typedef enum _RGXFWIF_CCB_CMD_TYPE_
 406 {
 407         RGXFWIF_CCB_CMD_TYPE_TA                 = 201 | RGX_CCB_TYPE_TASK,
 408         RGXFWIF_CCB_CMD_TYPE_3D                 = 202 | RGX_CCB_TYPE_TASK,
 409         RGXFWIF_CCB_CMD_TYPE_CDM                = 203 | RGX_CCB_TYPE_TASK,
 410         RGXFWIF_CCB_CMD_TYPE_TQ_3D              = 204 | RGX_CCB_TYPE_TASK,
 411         RGXFWIF_CCB_CMD_TYPE_TQ_2D              = 205 | RGX_CCB_TYPE_TASK,
 412         RGXFWIF_CCB_CMD_TYPE_3D_PR              = 206 | RGX_CCB_TYPE_TASK,
 413         RGXFWIF_CCB_CMD_TYPE_NULL               = 207 | RGX_CCB_TYPE_TASK,
 414         RGXFWIF_CCB_CMD_TYPE_SHG                = 208 | RGX_CCB_TYPE_TASK,
 415         RGXFWIF_CCB_CMD_TYPE_RTU                = 209 | RGX_CCB_TYPE_TASK,
 416         RGXFWIF_CCB_CMD_TYPE_RTU_FC               = 210 | RGX_CCB_TYPE_TASK,
 417         RGXFWIF_CCB_CMD_TYPE_PRE_TIMESTAMP = 211 | RGX_CCB_TYPE_TASK,
 418
 419 /* Leave a gap between CCB specific commands and generic commands */
 420         RGXFWIF_CCB_CMD_TYPE_FENCE          = 212,
 421         RGXFWIF_CCB_CMD_TYPE_UPDATE         = 213,
 422         RGXFWIF_CCB_CMD_TYPE_RMW_UPDATE     = 214,
 423         RGXFWIF_CCB_CMD_TYPE_FENCE_PR       = 215,
 424         RGXFWIF_CCB_CMD_TYPE_PRIORITY       = 216,
 425 /* Pre and Post timestamp commands are supposed to sandwich the DM cmd. The
 426    padding code with the CCB wrap upsets the FW if we don't have the task type
 427    bit cleared for POST_TIMESTAMPs. That's why we have 2 different cmd types.
 428 */
 429         RGXFWIF_CCB_CMD_TYPE_POST_TIMESTAMP = 217,
 430         RGXFWIF_CCB_CMD_TYPE_UNFENCED_UPDATE = 218,
 431         RGXFWIF_CCB_CMD_TYPE_UNFENCED_RMW_UPDATE = 219,
 432
 433         RGXFWIF_CCB_CMD_TYPE_PADDING    = 220,
 434 } RGXFWIF_CCB_CMD_TYPE;
 435
 436 typedef struct _RGXFWIF_CCB_CMD_HEADER_
 437 {
 438         RGXFWIF_CCB_CMD_TYPE    eCmdType;
 439         IMG_UINT32                              ui32CmdSize;
 440 } RGXFWIF_CCB_CMD_HEADER;
 441
 442 typedef enum _RGXFWIF_PWR_EVT_
 443 {
 444         RGXFWIF_PWR_EVT_PWR_ON,                 /* Sidekick power event */
 445         RGXFWIF_PWR_EVT_DUST_CHANGE,            /* Rascal / dust power event */
 446         RGXFWIF_PWR_EVT_ALL                     /* Applies to all power events. Keep as last element */
 447 } RGXFWIF_PWR_EVT;
 448
 449 typedef struct _RGXFWIF_REG_CFG_REC_
 450 {
 451         IMG_UINT64              ui64Addr;
 452         IMG_UINT64              ui64Value;
 453 } RGXFWIF_REG_CFG_REC;
 454
 455
 456 typedef struct _RGXFWIF_TIME_CORR_
 457 {
 458         IMG_UINT64 RGXFW_ALIGN ui64OSTimeStamp;
 459         IMG_UINT64 RGXFW_ALIGN ui64CRTimeStamp;
 460         IMG_UINT32             ui32CoreClockSpeed;
 461
 462         /* Utility variable used to convert CR timer deltas to OS timer deltas (nS),
 463          * where the deltas are relative to the timestamps above:
 464          * deltaOS = (deltaCR * K) >> decimal_shift, see full explanation below */
 465         IMG_UINT32             ui32CRDeltaToOSDeltaKNs;
 466 } UNCACHED_ALIGN RGXFWIF_TIME_CORR;
 467
 468 typedef struct _RGXFWIF_TIMESTAMP_
 469 {
 470         RGXFWIF_TIME_CORR      sTimeCorr;
 471         IMG_UINT64 RGXFW_ALIGN ui64Timestamp;
 472 } UNCACHED_ALIGN RGXFWIF_TIMESTAMP;
 473
 474
 475 /* These macros are used to help converting FW timestamps to the Host time domain.
 476  * On the FW the RGX_CR_TIMER counter is used to keep track of the time;
 477  * it increments by 1 every 256 GPU clock ticks, so the general formula
 478  * to perform the conversion is:
 479  *
 480  * [ GPU clock speed in Hz, if (scale == 10^9) then deltaOS is in nS,
 481  *   otherwise if (scale == 10^6) then deltaOS is in uS ]
 482  *
 483  *             deltaCR * 256                                   256 * scale
 484  *  deltaOS = --------------- * scale = deltaCR * K    [ K = --------------- ]
 485  *             GPUclockspeed                                  GPUclockspeed
 486  *
 487  * The actual K is multiplied by 2^20 (and deltaCR * K is divided by 2^20)
 488  * to get some better accuracy and to avoid returning 0 in the integer
 489  * division 256000000/GPUfreq if GPUfreq is greater than 256MHz.
 490  * This is the same as keeping K as a decimal number.
 491  *
 492  * The maximum deltaOS is slightly more than 5hrs for all GPU frequencies
 493  * (deltaCR * K is more or less a costant), and it's relative to
 494  * the base OS timestamp sampled as a part of the timer correlation data.
 495  * This base is refreshed on GPU power-on, DVFS transition and
 496  * periodic frequency calibration (executed every few seconds if the FW is
 497  * doing some work), so as long as the GPU is doing something and one of these
 498  * events is triggered then deltaCR * K will not overflow and deltaOS will be
 499  * correct.
 500  */
 501
 502 #define RGXFWIF_CRDELTA_TO_OSDELTA_ACCURACY_SHIFT  (20)
 503
 504 #define RGXFWIF_GET_CRDELTA_TO_OSDELTA_K_NS(clockfreq, remainder) \
 505         OSDivide64((256000000ULL << RGXFWIF_CRDELTA_TO_OSDELTA_ACCURACY_SHIFT), \
 506                    ((clockfreq) + 500) / 1000, \
 507                    &(remainder))
 508
 509 #define RGXFWIF_GET_DELTA_OSTIME_NS(deltaCR, K) \
 510         ( ((deltaCR) * (K)) >> RGXFWIF_CRDELTA_TO_OSDELTA_ACCURACY_SHIFT)
 511
 512 #define RGXFWIF_GET_DELTA_OSTIME_US(deltacr, clockfreq, remainder) \
 513         OSDivide64r64((deltacr) * 256000, ((clockfreq) + 500) / 1000, &(remainder))
 514
 515 /* Use this macro to get a more realistic GPU core clock speed than
 516  * the one given by the upper layers (used when doing GPU frequency
 517  * calibration)
 518  */
 519 #define RGXFWIF_GET_GPU_CLOCK_FREQUENCY_HZ(deltacr_us, deltaos_us, remainder) \
 520         OSDivide64((deltacr_us) * 256000000, (deltaos_us), &(remainder))
 521
 522 #endif /*  __RGX_FWIF_SHARED_H__ */
 523
 524 /******************************************************************************
 525  End of file (rgx_fwif_shared.h)
 526 ******************************************************************************/
 527
 528