drivers/gpu/rogue_m/services/include/rgx_fwif_km.h

   1 /*************************************************************************/ /*!
   2 @File
   3 @Title          RGX firmware interface structures used by pvrsrvkm
   4 @Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
   5 @Description    RGX firmware interface structures used by pvrsrvkm
   6 @License        Dual MIT/GPLv2
   7
   8 The contents of this file are subject to the MIT license as set out below.
   9
  10 Permission is hereby granted, free of charge, to any person obtaining a copy
  11 of this software and associated documentation files (the "Software"), to deal
  12 in the Software without restriction, including without limitation the rights
  13 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  14 copies of the Software, and to permit persons to whom the Software is
  15 furnished to do so, subject to the following conditions:
  16
  17 The above copyright notice and this permission notice shall be included in
  18 all copies or substantial portions of the Software.
  19
  20 Alternatively, the contents of this file may be used under the terms of
  21 the GNU General Public License Version 2 ("GPL") in which case the provisions
  22 of GPL are applicable instead of those above.
  23
  24 If you wish to allow use of your version of this file only under the terms of
  25 GPL, and not to allow others to use your version of this file under the terms
  26 of the MIT license, indicate your decision by deleting the provisions above
  27 and replace them with the notice and other provisions required by GPL as set
  28 out in the file called "GPL-COPYING" included in this distribution. If you do
  29 not delete the provisions above, a recipient may use your version of this file
  30 under the terms of either the MIT license or GPL.
  31
  32 This License is also included in this distribution in the file called
  33 "MIT-COPYING".
  34
  35 EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
  36 PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
  37 BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  38 PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
  39 COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  40 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  41 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  42 */ /**************************************************************************/
  43
  44 #if !defined (__RGX_FWIF_KM_H__)
  45 #define __RGX_FWIF_KM_H__
  46
  47 #include "img_types.h"
  48 #include "rgx_fwif_shared.h"
  49 #include "rgxdefs_km.h"
  50 #include "pvr_debug.h"
  51 #include "dllist.h"
  52
  53 #if defined(RGX_FIRMWARE)
  54 /* Compiling the actual firmware - use a fully typed pointer */
  55 typedef struct _RGXFWIF_HOST_CTL_                       *PRGXFWIF_HOST_CTL;
  56 typedef struct _RGXFWIF_CCB_CTL_                        *PRGXFWIF_CCB_CTL;
  57 typedef IMG_UINT8                                                       *PRGXFWIF_CCB;
  58 typedef struct _RGXFWIF_FWMEMCONTEXT_           *PRGXFWIF_FWMEMCONTEXT;
  59 typedef struct _RGXFWIF_FWRENDERCONTEXT_        *PRGXFWIF_FWRENDERCONTEXT;
  60 typedef struct _RGXFWIF_FWTQ2DCONTEXT_          *PRGXFWIF_FWTQ2DCONTEXT;
  61 typedef struct _RGXFWIF_FWTQ3DCONTEXT_          *PRGXFWIF_FWTQ3DCONTEXT;
  62 typedef struct _RGXFWIF_FWCOMPUTECONTEXT_       *PRGXFWIF_FWCOMPUTECONTEXT;
  63 typedef struct _RGXFWIF_FWCOMMONCONTEXT_        *PRGXFWIF_FWCOMMONCONTEXT;
  64 typedef struct _RGXFWIF_ZSBUFFER_                       *PRGXFWIF_ZSBUFFER;
  65 typedef IMG_UINT32                                                      *PRGXFWIF_SIGBUFFER;
  66 typedef struct _RGXFWIF_INIT_                           *PRGXFWIF_INIT;
  67 typedef struct _RGXFWIF_RUNTIME_CFG                     *PRGXFWIF_RUNTIME_CFG;
  68 typedef struct _RGXFW_UNITTESTS_                        *PRGXFW_UNITTESTS;
  69 typedef struct _RGXFWIF_TRACEBUF_                       *PRGXFWIF_TRACEBUF;
  70 typedef IMG_UINT8                                                       *PRGXFWIF_HWPERFINFO;
  71 typedef struct _RGXFWIF_HWRINFOBUF_                     *PRGXFWIF_HWRINFOBUF;
  72 typedef struct _RGXFWIF_GPU_UTIL_FWCB_          *PRGXFWIF_GPU_UTIL_FWCB;
  73 typedef struct _RGXFWIF_REG_CFG_                *PRGXFWIF_REG_CFG;
  74 typedef IMG_UINT8                                                       *PRGXFWIF_COMMONCTX_STATE;
  75 typedef struct _RGXFWIF_TACTX_STATE_            *PRGXFWIF_TACTX_STATE;
  76 typedef struct _RGXFWIF_3DCTX_STATE_            *PRGXFWIF_3DCTX_STATE;
  77 typedef struct _RGXFWIF_COMPUTECTX_STATE_       *PRGXFWIF_COMPUTECTX_STATE;
  78 typedef struct _RGXFWIF_VRDMCTX_STATE_          *PRGXFWIF_VRDMCTX_STATE;
  79 typedef IMG_UINT8                                                       *PRGXFWIF_RF_CMD;
  80 typedef struct _RGXFWIF_COMPCHECKS_                     *PRGXFWIF_COMPCHECKS;
  81 typedef struct _RGX_HWPERF_CONFIG_CNTBLK_       *PRGX_HWPERF_CONFIG_CNTBLK;
  82 typedef IMG_UINT32                          *PRGX_HWPERF_SELECT_CUSTOM_CNTRS;
  83 typedef DLLIST_NODE                                                     RGXFWIF_DLLIST_NODE;
  84 typedef struct _RGXFWIF_HWPERF_CTL_                     *PRGXFWIF_HWPERF_CTL;
  85 #else
  86 /* Compiling the host driver - use a firmware device virtual pointer */
  87 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_HOST_CTL;
  88 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_CCB_CTL;
  89 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_CCB;
  90 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_FWMEMCONTEXT;
  91 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_FWRENDERCONTEXT;
  92 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_FWTQ2DCONTEXT;
  93 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_FWTQ3DCONTEXT;
  94 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_FWCOMPUTECONTEXT;
  95 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_FWCOMMONCONTEXT;
  96 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_ZSBUFFER;
  97 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_SIGBUFFER;
  98 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_INIT;
  99 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_RUNTIME_CFG;
 100 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFW_UNITTESTS;
 101 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_TRACEBUF;
 102 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_HWPERFINFO;
 103 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_HWRINFOBUF;
 104 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_GPU_UTIL_FWCB;
 105 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_REG_CFG;
 106 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_COMMONCTX_STATE;
 107 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_RF_CMD;
 108 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_COMPCHECKS;
 109 typedef RGXFWIF_DEV_VIRTADDR                            PRGX_HWPERF_CONFIG_CNTBLK;
 110 typedef RGXFWIF_DEV_VIRTADDR                PRGX_HWPERF_SELECT_CUSTOM_CNTRS;
 111 typedef struct {RGXFWIF_DEV_VIRTADDR p;
 112                                   RGXFWIF_DEV_VIRTADDR n;}      RGXFWIF_DLLIST_NODE;
 113 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_HWPERF_CTL;
 114 #endif /* RGX_FIRMWARE */
 115
 116 /*!
 117  * This number is used to represent an invalid page catalogue physical address
 118  */
 119 #define RGXFWIF_INVALID_PC_PHYADDR 0xFFFFFFFFFFFFFFFFLLU
 120
 121 /*!
 122         Firmware memory context.
 123 */
 124 typedef struct _RGXFWIF_FWMEMCONTEXT_
 125 {
 126         IMG_DEV_PHYADDR                 RGXFW_ALIGN sPCDevPAddr;        /*!< device physical address of context's page catalogue */
 127         IMG_INT32                               uiPageCatBaseRegID;     /*!< associated page catalog base register (-1 == unallocated) */
 128         IMG_UINT32                              uiBreakpointAddr; /*!< breakpoint address */
 129         IMG_UINT32                              uiBPHandlerAddr;  /*!< breakpoint handler address */
 130         IMG_UINT32                              uiBreakpointCtl; /*!< DM and enable control for BP */
 131
 132 #if defined(SUPPORT_GPUVIRT_VALIDATION)
 133     IMG_UINT32              ui32OSid;
 134 #endif
 135
 136 } UNCACHED_ALIGN RGXFWIF_FWMEMCONTEXT;
 137
 138
 139 /*!
 140  *      FW context state flags
 141  */
 142 #define RGXFWIF_CONTEXT_TAFLAGS_NEED_RESUME                     (0x00000001)
 143 #define RGXFWIF_CONTEXT_RENDERFLAGS_NEED_RESUME         (0x00000002)
 144 #define RGXFWIF_CONTEXT_CDMFLAGS_NEED_RESUME            (0x00000004)
 145 #define RGXFWIF_CONTEXT_SHGFLAGS_NEED_RESUME            (0x00000008)
 146 #define RGXFWIF_CONTEXT_ALLFLAGS_NEED_RESUME            (0x0000000F)
 147
 148
 149 typedef struct _RGXFWIF_TACTX_STATE_
 150 {
 151         /* FW-accessible TA state which must be written out to memory on context store */
 152         IMG_UINT64      RGXFW_ALIGN uTAReg_VDM_CALL_STACK_POINTER;               /* To store in mid-TA */
 153         IMG_UINT64      RGXFW_ALIGN uTAReg_VDM_CALL_STACK_POINTER_Init;  /* Initial value (in case is 'lost' due to a lock-up */
 154         IMG_UINT64      RGXFW_ALIGN uTAReg_VDM_BATCH;
 155         IMG_UINT64      RGXFW_ALIGN uTAReg_VBS_SO_PRIM0;
 156         IMG_UINT64      RGXFW_ALIGN uTAReg_VBS_SO_PRIM1;
 157         IMG_UINT64      RGXFW_ALIGN uTAReg_VBS_SO_PRIM2;
 158         IMG_UINT64      RGXFW_ALIGN uTAReg_VBS_SO_PRIM3;
 159 } UNCACHED_ALIGN RGXFWIF_TACTX_STATE;
 160
 161
 162 typedef struct _RGXFWIF_3DCTX_STATE_
 163 {
 164         /* FW-accessible ISP state which must be written out to memory on context store */
 165 #if !defined(RGX_FEATURE_S7_TOP_INFRASTRUCTURE)
 166         IMG_UINT32      RGXFW_ALIGN au3DReg_ISP_STORE[8];
 167 #else
 168         IMG_UINT32      RGXFW_ALIGN au3DReg_ISP_STORE[32];
 169 #endif
 170         IMG_UINT64      RGXFW_ALIGN u3DReg_PM_DEALLOCATED_MASK_STATUS;
 171         IMG_UINT64      RGXFW_ALIGN u3DReg_PM_PDS_MTILEFREE_STATUS;
 172 } UNCACHED_ALIGN RGXFWIF_3DCTX_STATE;
 173
 174
 175
 176 typedef struct _RGXFWIF_COMPUTECTX_STATE_
 177 {
 178         IMG_UINT64      RGXFW_ALIGN     ui64Padding;
 179 } RGXFWIF_COMPUTECTX_STATE;
 180
 181
 182 typedef struct _RGXFWIF_VRDMCTX_STATE_
 183 {
 184         /* FW-accessible TA state which must be written out to memory on context store */
 185         IMG_UINT64      RGXFW_ALIGN uVRDMReg_VRM_CALL_STACK_POINTER;
 186         IMG_UINT64      RGXFW_ALIGN uVRDMReg_VRM_BATCH;
 187
 188         /* Number of kicks on this context */
 189         IMG_UINT32  ui32NumKicks;
 190 } UNCACHED_ALIGN RGXFWIF_VRDMCTX_STATE;
 191
 192
 193 typedef struct _RGXFWIF_FWCOMMONCONTEXT_
 194 {
 195         /*
 196                 Used by bg and irq context
 197         */
 198         /* CCB details for this firmware context */
 199         PRGXFWIF_CCCB_CTL               psCCBCtl;                               /*!< CCB control */
 200         PRGXFWIF_CCCB                   psCCB;                                  /*!< CCB base */
 201
 202         /*
 203                 Used by the bg context only
 204         */
 205         RGXFWIF_DLLIST_NODE             RGXFW_ALIGN sWaitingNode;                       /*!< List entry for the waiting list */
 206
 207         /*
 208                 Used by the irq context only
 209         */
 210         RGXFWIF_DLLIST_NODE             sRunNode;                               /*!< List entry for the run list */
 211
 212         PRGXFWIF_FWMEMCONTEXT   psFWMemContext;                 /*!< Memory context */
 213
 214         /* Context suspend state */
 215         PRGXFWIF_COMMONCTX_STATE        RGXFW_ALIGN psContextState;             /*!< TA/3D context suspend state, read/written by FW */
 216
 217         /* Framework state
 218          */
 219         PRGXFWIF_RF_CMD         RGXFW_ALIGN psRFCmd;            /*!< Register updates for Framework */
 220
 221         /*
 222          *      Flags e.g. for context switching
 223          */
 224         IMG_UINT32                              ui32Flags;
 225         IMG_UINT32                              ui32Priority;
 226         IMG_UINT32                              ui32PrioritySeqNum;
 227         IMG_UINT64              RGXFW_ALIGN     ui64MCUFenceAddr;
 228
 229         /* References to the host side originators */
 230         IMG_UINT32                              ui32ServerCommonContextID;                      /*!< the Server Common Context */
 231         IMG_UINT32                              ui32PID;                                                        /*!< associated process ID */
 232
 233         /* Statistic updates waiting to be passed back to the host... */
 234         IMG_BOOL                                bStatsPending;                                          /*!< True when some stats are pending */
 235         IMG_INT32                               i32StatsNumStores;                                      /*!< Number of stores on this context since last update */
 236         IMG_INT32                               i32StatsNumOutOfMemory;                         /*!< Number of OOMs on this context since last update */
 237         IMG_INT32                               i32StatsNumPartialRenders;                      /*!< Number of PRs on this context since last update */
 238 } UNCACHED_ALIGN RGXFWIF_FWCOMMONCONTEXT;
 239
 240 /*!
 241         Firmware render context.
 242 */
 243 typedef struct _RGXFWIF_FWRENDERCONTEXT_
 244 {
 245         RGXFWIF_FWCOMMONCONTEXT sTAContext;                             /*!< Firmware context for the TA */
 246         RGXFWIF_FWCOMMONCONTEXT s3DContext;                             /*!< Firmware context for the 3D */
 247
 248         /*
 249          * Note: The following fields keep track of OOM and partial render statistics.
 250          * Because these data structures are allocated cache-incoherent,
 251          * and because these fields are updated by the firmware,
 252          * the host will read valid values only after an SLC flush/inval.
 253          * This is only guaranteed to happen while destroying the render-context.
 254          */
 255         IMG_UINT32                      ui32TotalNumPartialRenders; /*!< Total number of partial renders */
 256         IMG_UINT32                      ui32TotalNumOutOfMemory;        /*!< Total number of OOMs */
 257
 258 } UNCACHED_ALIGN RGXFWIF_FWRENDERCONTEXT;
 259
 260 /*!
 261         Firmware render context.
 262 */
 263 typedef struct _RGXFWIF_FWRAYCONTEXT_
 264 {
 265         RGXFWIF_FWCOMMONCONTEXT sSHGContext;                            /*!< Firmware context for the SHG */
 266         RGXFWIF_FWCOMMONCONTEXT sRTUContext;                            /*!< Firmware context for the RTU */
 267         PRGXFWIF_CCCB_CTL               psCCBCtl[DPX_MAX_RAY_CONTEXTS];
 268         PRGXFWIF_CCCB                   psCCB[DPX_MAX_RAY_CONTEXTS];
 269         IMG_UINT32                              ui32NextFC;
 270         IMG_UINT32                              ui32ActiveFCMask;
 271 } UNCACHED_ALIGN RGXFWIF_FWRAYCONTEXT;
 272
 273 #define RGXFWIF_INVALID_FRAME_CONTEXT (0xFFFFFFFF)
 274
 275 /*!
 276     BIF requester selection
 277 */
 278 typedef enum _RGXFWIF_BIFREQ_
 279 {
 280         RGXFWIF_BIFREQ_TA               = 0,
 281         RGXFWIF_BIFREQ_3D               = 1,
 282         RGXFWIF_BIFREQ_CDM              = 2,
 283         RGXFWIF_BIFREQ_2D               = 3,
 284         RGXFWIF_BIFREQ_HOST             = 4,
 285         RGXFWIF_BIFREQ_RTU              = 5,
 286         RGXFWIF_BIFREQ_SHG              = 6,
 287         RGXFWIF_BIFREQ_MAX              = 7
 288 } RGXFWIF_BIFREQ;
 289
 290 typedef enum _RGXFWIF_PM_DM_
 291 {
 292         RGXFWIF_PM_DM_TA        = 0,
 293         RGXFWIF_PM_DM_3D        = 1,
 294 } RGXFWIF_PM_DM;
 295
 296 typedef enum _RGXFWIF_RPM_DM_
 297 {
 298         RGXFWIF_RPM_DM_SHF      = 0,
 299         RGXFWIF_RPM_DM_SHG      = 1,
 300         RGXFWIF_RPM_DM_MAX,
 301 } RGXFWIF_RPM_DM;
 302
 303 /*!
 304  ******************************************************************************
 305  * Kernel CCB control for RGX
 306  *****************************************************************************/
 307 typedef struct _RGXFWIF_CCB_CTL_
 308 {
 309         volatile IMG_UINT32             ui32WriteOffset;                /*!< write offset into array of commands (MUST be aligned to 16 bytes!) */
 310         volatile IMG_UINT32             ui32ReadOffset;                 /*!< read offset into array of commands */
 311         IMG_UINT32                              ui32WrapMask;                   /*!< Offset wrapping mask (Total capacity of the CCB - 1) */
 312         IMG_UINT32                              ui32CmdSize;                    /*!< size of each command in bytes */
 313 } UNCACHED_ALIGN RGXFWIF_CCB_CTL;
 314
 315 /*!
 316  ******************************************************************************
 317  * Kernel CCB command structure for RGX
 318  *****************************************************************************/
 319 #if !defined(RGX_FEATURE_SLC_VIVT)
 320
 321 #define RGXFWIF_MMUCACHEDATA_FLAGS_PT      (0x1) /* BIF_CTRL_INVAL_PT_EN */
 322 #define RGXFWIF_MMUCACHEDATA_FLAGS_PD      (0x2) /* BIF_CTRL_INVAL_PD_EN */
 323 #define RGXFWIF_MMUCACHEDATA_FLAGS_PC      (0x4) /* BIF_CTRL_INVAL_PC_EN */
 324 #define RGXFWIF_MMUCACHEDATA_FLAGS_PMTLB   (0x10) /* can't use PM_TLB0 bit from BIFPM_CTRL reg because it collides with PT bit from BIF_CTRL reg */
 325 #define RGXFWIF_MMUCACHEDATA_FLAGS_TLB     (RGXFWIF_MMUCACHEDATA_FLAGS_PMTLB | 0x8) /* BIF_CTRL_INVAL_TLB1_EN */
 326 #define RGXFWIF_MMUCACHEDATA_FLAGS_CTX(C)  (0x0) /* not used */
 327 #define RGXFWIF_MMUCACHEDATA_FLAGS_CTX_ALL (0x0) /* not used */
 328
 329 #else /* RGX_FEATURE_SLC_VIVT */
 330 #define RGXFWIF_MMUCACHEDATA_FLAGS_PT      (0x1) /* MMU_CTRL_INVAL_PT_EN */
 331 #define RGXFWIF_MMUCACHEDATA_FLAGS_PD      (0x2) /* MMU_CTRL_INVAL_PD_EN */
 332 #define RGXFWIF_MMUCACHEDATA_FLAGS_PC      (0x4) /* MMU_CTRL_INVAL_PC_EN */
 333 #define RGXFWIF_MMUCACHEDATA_FLAGS_PMTLB   (0x0) /* not used */
 334 #define RGXFWIF_MMUCACHEDATA_FLAGS_TLB     (0x0) /* not used */
 335 #define RGXFWIF_MMUCACHEDATA_FLAGS_CTX(C)  ((C) << 0x3) /* MMU_CTRL_INVAL_CONTEXT_SHIFT */
 336 #define RGXFWIF_MMUCACHEDATA_FLAGS_CTX_ALL (0x800) /* MMU_CTRL_INVAL_ALL_CONTEXTS_EN */
 337 #endif
 338
 339 typedef struct _RGXFWIF_MMUCACHEDATA_
 340 {
 341         PRGXFWIF_FWMEMCONTEXT           psMemoryContext;
 342         IMG_UINT32                                      ui32Flags;
 343         IMG_UINT32                                      ui32CacheSequenceNum;
 344 } RGXFWIF_MMUCACHEDATA;
 345
 346 typedef struct _RGXFWIF_SLCBPCTLDATA_
 347 {
 348         IMG_BOOL               bSetBypassed;        /*!< Should SLC be/not be bypassed for indicated units? */
 349         IMG_UINT32             uiFlags;             /*!< Units to enable/disable */
 350 } RGXFWIF_SLCBPCTLDATA;
 351
 352 #define RGXFWIF_BPDATA_FLAGS_WRITE      (1 << 0)
 353 #define RGXFWIF_BPDATA_FLAGS_CTL        (1 << 1)
 354 #define RGXFWIF_BPDATA_FLAGS_REGS       (1 << 2)
 355
 356 typedef struct _RGXFWIF_FWBPDATA_
 357 {
 358         PRGXFWIF_FWMEMCONTEXT   psFWMemContext;                 /*!< Memory context */
 359         IMG_UINT32              ui32BPAddr;                     /*!< Breakpoint address */
 360         IMG_UINT32              ui32HandlerAddr;                /*!< Breakpoint handler */
 361         IMG_UINT32              ui32BPDM;                       /*!< Breakpoint control */
 362         IMG_BOOL                bEnable;
 363         IMG_UINT32              ui32Flags;
 364         IMG_UINT32              ui32TempRegs;           /*!< Number of temporary registers to overallocate */
 365         IMG_UINT32              ui32SharedRegs;         /*!< Number of shared registers to overallocate */
 366 } RGXFWIF_BPDATA;
 367
 368 #define RGXFWIF_KCCB_CMD_KICK_DATA_MAX_NUM_CLEANUP_CTLS 4
 369
 370 typedef struct _RGXFWIF_KCCB_CMD_KICK_DATA_
 371 {
 372         PRGXFWIF_FWCOMMONCONTEXT        psContext;                      /*!< address of the firmware context */
 373         IMG_UINT32                                      ui32CWoffUpdate;        /*!< Client CCB woff update */
 374         IMG_UINT32              ui32NumCleanupCtl;              /*!< number of CleanupCtl pointers attached */
 375         PRGXFWIF_CLEANUP_CTL    apsCleanupCtl[RGXFWIF_KCCB_CMD_KICK_DATA_MAX_NUM_CLEANUP_CTLS]; /*!< CleanupCtl structures associated with command */
 376 } RGXFWIF_KCCB_CMD_KICK_DATA;
 377
 378 typedef struct _RGXFWIF_KCCB_CMD_FENCE_DATA_
 379 {
 380         IMG_UINT32 uiSyncObjDevVAddr;
 381         IMG_UINT32 uiUpdateVal;
 382 } RGXFWIF_KCCB_CMD_SYNC_DATA;
 383
 384 typedef enum _RGXFWIF_CLEANUP_TYPE_
 385 {
 386         RGXFWIF_CLEANUP_FWCOMMONCONTEXT,                /*!< FW common context cleanup */
 387         RGXFWIF_CLEANUP_HWRTDATA,                               /*!< FW HW RT data cleanup */
 388         RGXFWIF_CLEANUP_FREELIST,                               /*!< FW freelist cleanup */
 389         RGXFWIF_CLEANUP_ZSBUFFER,                               /*!< FW ZS Buffer cleanup */
 390         RGXFWIF_CLEANUP_HWFRAMEDATA,                    /*!< FW RPM/RTU frame data */
 391         RGXFWIF_CLEANUP_RPM_FREELIST,                   /*!< FW RPM freelist */
 392 } RGXFWIF_CLEANUP_TYPE;
 393
 394 #define RGXFWIF_CLEANUP_RUN             (1 << 0)        /*!< The requested cleanup command has run on the FW */
 395 #define RGXFWIF_CLEANUP_BUSY    (1 << 1)        /*!< The requested resource is busy */
 396
 397 typedef struct _RGXFWIF_CLEANUP_REQUEST_
 398 {
 399         RGXFWIF_CLEANUP_TYPE                    eCleanupType;                   /*!< Cleanup type */
 400         union {
 401                 PRGXFWIF_FWCOMMONCONTEXT        psContext;                              /*!< FW common context to cleanup */
 402                 PRGXFWIF_HWRTDATA                       psHWRTData;                             /*!< HW RT to cleanup */
 403                 PRGXFWIF_FREELIST                       psFreelist;                             /*!< Freelist to cleanup */
 404                 PRGXFWIF_ZSBUFFER                       psZSBuffer;                             /*!< ZS Buffer to cleanup */
 405 #if defined(RGX_FEATURE_RAY_TRACING)
 406                 PRGXFWIF_RAY_FRAME_DATA         psHWFrameData;                  /*!< RPM/RTU frame data to cleanup */
 407                 PRGXFWIF_RPM_FREELIST           psRPMFreelist;                  /*!< RPM Freelist to cleanup */
 408 #endif
 409         } uCleanupData;
 410         IMG_UINT32                                              uiSyncObjDevVAddr;              /*!< sync primitive used to indicate state of the request */
 411 } RGXFWIF_CLEANUP_REQUEST;
 412
 413 typedef enum _RGXFWIF_POWER_TYPE_
 414 {
 415         RGXFWIF_POW_OFF_REQ = 1,
 416         RGXFWIF_POW_FORCED_IDLE_REQ,
 417         RGXFWIF_POW_NUMDUST_CHANGE,
 418         RGXFWIF_POW_APM_LATENCY_CHANGE
 419 } RGXFWIF_POWER_TYPE;
 420
 421 typedef struct _RGXFWIF_POWER_REQUEST_
 422 {
 423         RGXFWIF_POWER_TYPE                              ePowType;                               /*!< Type of power request */
 424         union
 425         {
 426                 IMG_UINT32                                      ui32NumOfDusts;                 /*!< Number of active Dusts */
 427                 IMG_BOOL                                        bForced;                                /*!< If the operation is mandatory */
 428                 IMG_BOOL                                        bCancelForcedIdle;              /*!< If the operation is to cancel previously forced idle */
 429                 IMG_UINT32                                      ui32ActivePMLatencyms;          /*!< Number of milliseconds to set APM latency */
 430         } uPoweReqData;
 431 } RGXFWIF_POWER_REQUEST;
 432
 433 typedef struct _RGXFWIF_SLCFLUSHINVALDATA_
 434 {
 435         PRGXFWIF_FWCOMMONCONTEXT psContext; /*!< Context to fence on (only useful when bDMContext == TRUE) */
 436         IMG_BOOL    bInval;                 /*!< Invalidate the cache as well as flushing */
 437         IMG_BOOL    bDMContext;             /*!< The data to flush/invalidate belongs to a specific DM context */
 438         RGXFWIF_DM  eDM;                    /*!< DM to flush entries for (only useful when bDMContext == TRUE) */
 439 } RGXFWIF_SLCFLUSHINVALDATA;
 440
 441 typedef struct _RGXFWIF_HWPERF_CTRL_
 442 {
 443         IMG_BOOL                                bToggle;        /*!< Toggle masked bits or apply full mask? */
 444         IMG_UINT64      RGXFW_ALIGN     ui64Mask;   /*!< Mask of events to toggle */
 445 } RGXFWIF_HWPERF_CTRL;
 446
 447 typedef struct _RGXFWIF_HWPERF_CONFIG_ENABLE_BLKS_
 448 {
 449         IMG_UINT32                              ui32NumBlocks;  /*!< Number of RGX_HWPERF_CONFIG_CNTBLK in the array */
 450         PRGX_HWPERF_CONFIG_CNTBLK pasBlockConfigs;      /*!< Address of the RGX_HWPERF_CONFIG_CNTBLK array */
 451 } RGXFWIF_HWPERF_CONFIG_ENABLE_BLKS;
 452
 453 typedef struct _RGXFWIF_CORECLKSPEEDCHANGE_DATA_
 454 {
 455         IMG_UINT32      ui32NewClockSpeed;                      /*!< New clock speed */
 456 } RGXFWIF_CORECLKSPEEDCHANGE_DATA;
 457
 458 #define RGXFWIF_HWPERF_CTRL_BLKS_MAX    16
 459
 460 typedef struct _RGXFWIF_HWPERF_CTRL_BLKS_
 461 {
 462         IMG_BOOL        bEnable;
 463         IMG_UINT32      ui32NumBlocks;                              /*!< Number of block IDs in the array */
 464         IMG_UINT16      aeBlockIDs[RGXFWIF_HWPERF_CTRL_BLKS_MAX];   /*!< Array of RGX_HWPERF_CNTBLK_ID values */
 465 } RGXFWIF_HWPERF_CTRL_BLKS;
 466
 467
 468 typedef struct _RGXFWIF_HWPERF_SELECT_CUSTOM_CNTRS_
 469 {
 470         IMG_UINT16 ui16CustomBlock;
 471         IMG_UINT16 ui16NumCounters;
 472         PRGX_HWPERF_SELECT_CUSTOM_CNTRS pui32CustomCounterIDs;
 473 } RGXFWIF_HWPERF_SELECT_CUSTOM_CNTRS;
 474
 475 typedef struct _RGXFWIF_ZSBUFFER_BACKING_DATA_
 476 {
 477         IMG_UINT32                              psZSBufferFWDevVAddr;                           /*!< ZS-Buffer FW address */
 478         IMG_UINT32                              bDone;                                                          /*!< action backing/unbacking succeeded */
 479 } RGXFWIF_ZSBUFFER_BACKING_DATA;
 480
 481 /*
 482  * Flags to pass in the unused bits of the page size grow request
 483  */
 484 #define RGX_FREELIST_GSDATA_RPM_RESTART_EN              (1 << 31)               /*!< Restart RPM after freelist grow command */
 485 #define RGX_FREELIST_GSDATA_RPM_PAGECNT_MASK    (0x3FFFFFU)             /*!< Mask for page count. */
 486
 487 typedef struct _RGXFWIF_FREELIST_GS_DATA_
 488 {
 489         IMG_UINT32                              psFreeListFWDevVAddr;                           /*!< Freelist FW address */
 490         IMG_UINT32                              ui32DeltaSize;                                          /*!< Amount of the Freelist change */
 491         IMG_UINT32                              ui32NewSize;                                            /*!< New amount of pages on the freelist */
 492 } RGXFWIF_FREELIST_GS_DATA;
 493
 494 #define RGXFWIF_FREELISTS_RECONSTRUCTION_FAILED_FLAG 0x80000000
 495
 496 typedef struct _RGXFWIF_FREELISTS_RECONSTRUCTION_DATA_
 497 {
 498         IMG_UINT32                      ui32FreelistsCount;
 499         IMG_UINT32                      aui32FreelistIDs[MAX_HW_TA3DCONTEXTS * RGXFW_MAX_FREELISTS];
 500 } RGXFWIF_FREELISTS_RECONSTRUCTION_DATA;
 501
 502 /*!
 503  ******************************************************************************
 504  * Register configuration structures
 505  *****************************************************************************/
 506
 507 #define RGXFWIF_REG_CFG_MAX_SIZE 512
 508
 509 typedef enum _RGXFWIF_REGDATA_CMD_TYPE_
 510 {
 511         RGXFWIF_REGCFG_CMD_ADD                          = 101,
 512         RGXFWIF_REGCFG_CMD_CLEAR                        = 102,
 513         RGXFWIF_REGCFG_CMD_ENABLE                       = 103,
 514         RGXFWIF_REGCFG_CMD_DISABLE                      = 104
 515 } RGXFWIF_REGDATA_CMD_TYPE;
 516
 517 typedef struct _RGXFWIF_REGCONFIG_DATA_
 518 {
 519         RGXFWIF_REGDATA_CMD_TYPE        eCmdType;
 520         RGXFWIF_PWR_EVT                 eRegConfigPI;
 521         RGXFWIF_REG_CFG_REC RGXFW_ALIGN         sRegConfig;
 522
 523 } RGXFWIF_REGCONFIG_DATA;
 524
 525 typedef struct _RGXFWIF_REG_CFG_
 526 {
 527         IMG_UINT32                      ui32NumRegsSidekick;
 528         IMG_UINT32                      ui32NumRegsRascalDust;
 529         RGXFWIF_REG_CFG_REC     RGXFW_ALIGN     asRegConfigs[RGXFWIF_REG_CFG_MAX_SIZE];
 530 } UNCACHED_ALIGN RGXFWIF_REG_CFG;
 531
 532 typedef enum _RGXFWIF_KCCB_CMD_TYPE_
 533 {
 534         RGXFWIF_KCCB_CMD_KICK                                           = 101,
 535         RGXFWIF_KCCB_CMD_MMUCACHE                                       = 102,
 536         RGXFWIF_KCCB_CMD_BP                                                     = 104,
 537         RGXFWIF_KCCB_CMD_SLCBPCTL                               = 106, /*!< slc bypass control. Requires sSLCBPCtlData. For validation */
 538         RGXFWIF_KCCB_CMD_SYNC                                   = 107, /*!< host sync command. Requires sSyncData. */
 539         RGXFWIF_KCCB_CMD_SLCFLUSHINVAL                          = 108, /*!< slc flush and invalidation request */
 540         RGXFWIF_KCCB_CMD_CLEANUP                                        = 109, /*!< Requests cleanup of a FW resource (type specified in the command data) */
 541         RGXFWIF_KCCB_CMD_POW                                            = 110, /*!< Power request */
 542         RGXFWIF_KCCB_CMD_HWPERF_CTRL_EVENTS                     = 111, /*!< Control the HWPerf event generation behaviour */
 543         RGXFWIF_KCCB_CMD_HWPERF_CONFIG_ENABLE_BLKS      = 112, /*!< Configure, clear and enable multiple HWPerf blocks */
 544         RGXFWIF_KCCB_CMD_HWPERF_CTRL_BLKS                       = 113, /*!< Enable or disable multiple HWPerf blocks (reusing existing configuration) */
 545         RGXFWIF_KCCB_CMD_CORECLKSPEEDCHANGE                     = 114, /*!< CORE clock speed change event */
 546         RGXFWIF_KCCB_CMD_ZSBUFFER_BACKING_UPDATE        = 115, /*!< Backing for on-demand ZS-Buffer done */
 547         RGXFWIF_KCCB_CMD_ZSBUFFER_UNBACKING_UPDATE      = 116, /*!< Unbacking for on-demand ZS-Buffer done */
 548         RGXFWIF_KCCB_CMD_FREELIST_GROW_UPDATE           = 117, /*!< Freelist Grow done */
 549         RGXFWIF_KCCB_CMD_FREELIST_SHRINK_UPDATE         = 118, /*!< Freelist Shrink done */
 550         RGXFWIF_KCCB_CMD_FREELISTS_RECONSTRUCTION_UPDATE        = 119, /*!< Freelists Reconstruction done */
 551         RGXFWIF_KCCB_CMD_HEALTH_CHECK               = 120, /*!< Health check request */
 552         RGXFWIF_KCCB_CMD_REGCONFIG                  = 121,
 553         RGXFWIF_KCCB_CMD_HWPERF_SELECT_CUSTOM_CNTRS = 122, /*!< Configure the custom counters for HWPerf */
 554         RGXFWIF_KCCB_CMD_HWPERF_CONFIG_ENABLE_BLKS_DIRECT       = 123, /*!< Configure, clear and enable multiple HWPerf blocks during the init process*/
 555
 556 #if defined(RGX_FEATURE_RAY_TRACING)
 557         RGXFWIF_FWCCB_CMD_DOPPLER_MEMORY_GROW           = 130,
 558 #endif
 559 } RGXFWIF_KCCB_CMD_TYPE;
 560
 561 /* Kernel CCB command packet */
 562 typedef struct _RGXFWIF_KCCB_CMD_
 563 {
 564         RGXFWIF_KCCB_CMD_TYPE                                   eCmdType;                       /*!< Command type */
 565         union
 566         {
 567                 RGXFWIF_KCCB_CMD_KICK_DATA                      sCmdKickData;                   /*!< Data for Kick command */
 568                 RGXFWIF_MMUCACHEDATA                            sMMUCacheData;                  /*!< Data for MMUCACHE command */
 569                 RGXFWIF_BPDATA                                          sBPData;                                /*!< Data for Breakpoint Commands */
 570                 RGXFWIF_SLCBPCTLDATA                            sSLCBPCtlData;                  /*!< Data for SLC Bypass Control */
 571                 RGXFWIF_KCCB_CMD_SYNC_DATA                      sSyncData;              /*!< Data for host sync commands */
 572                 RGXFWIF_SLCFLUSHINVALDATA                       sSLCFlushInvalData;             /*!< Data for SLC Flush/Inval commands */
 573                 RGXFWIF_CLEANUP_REQUEST                         sCleanupData;                   /*!< Data for cleanup commands */
 574                 RGXFWIF_POWER_REQUEST                           sPowData;                               /*!< Data for power request commands */
 575                 RGXFWIF_HWPERF_CTRL                                     sHWPerfCtrl;                    /*!< Data for HWPerf control command */
 576                 RGXFWIF_HWPERF_CONFIG_ENABLE_BLKS       sHWPerfCfgEnableBlks;   /*!< Data for HWPerf configure, clear and enable performance counter block command */
 577                 RGXFWIF_HWPERF_CTRL_BLKS                        sHWPerfCtrlBlks;                /*!< Data for HWPerf enable or disable performance counter block commands */
 578                 RGXFWIF_HWPERF_SELECT_CUSTOM_CNTRS  sHWPerfSelectCstmCntrs; /*!< Data for HWPerf configure the custom counters to read */
 579                 RGXFWIF_CORECLKSPEEDCHANGE_DATA         sCORECLKSPEEDCHANGEData;/*!< Data for CORE clock speed change */
 580                 RGXFWIF_ZSBUFFER_BACKING_DATA           sZSBufferBackingData;   /*!< Feedback for Z/S Buffer backing/unbacking */
 581                 RGXFWIF_FREELIST_GS_DATA                        sFreeListGSData;                /*!< Feedback for Freelist grow/shrink */
 582                 RGXFWIF_FREELISTS_RECONSTRUCTION_DATA   sFreeListsReconstructionData;   /*!< Feedback for Freelists reconstruction */
 583                 RGXFWIF_REGCONFIG_DATA                          sRegConfigData;                 /*!< Data for custom register configuration */
 584         } UNCACHED_ALIGN uCmdData;
 585 } UNCACHED_ALIGN RGXFWIF_KCCB_CMD;
 586
 587 RGX_FW_STRUCT_SIZE_ASSERT(RGXFWIF_KCCB_CMD);
 588
 589 /*!
 590  ******************************************************************************
 591  * Firmware CCB command structure for RGX
 592  *****************************************************************************/
 593
 594 typedef struct _RGXFWIF_FWCCB_CMD_ZSBUFFER_BACKING_DATA_
 595 {
 596         IMG_UINT32                              ui32ZSBufferID;
 597         IMG_BOOL                                bPopulate;
 598 } RGXFWIF_FWCCB_CMD_ZSBUFFER_BACKING_DATA;
 599
 600 typedef struct _RGXFWIF_FWCCB_CMD_FREELIST_GS_DATA_
 601 {
 602         IMG_UINT32                              ui32FreelistID;
 603 } RGXFWIF_FWCCB_CMD_FREELIST_GS_DATA;
 604
 605 typedef struct _RGXFWIF_FWCCB_CMD_FREELISTS_RECONSTRUCTION_DATA_
 606 {
 607         IMG_UINT32                      ui32FreelistsCount;
 608         IMG_UINT32                      ui32HwrCounter;
 609         IMG_UINT32                      aui32FreelistIDs[MAX_HW_TA3DCONTEXTS * RGXFW_MAX_FREELISTS];
 610 } RGXFWIF_FWCCB_CMD_FREELISTS_RECONSTRUCTION_DATA;
 611
 612 typedef struct _RGXFWIF_FWCCB_CMD_CONTEXT_RESET_DATA_
 613 {
 614         IMG_UINT32                                              ui32ServerCommonContextID;      /*!< Context affected by the reset */
 615         RGXFWIF_CONTEXT_RESET_REASON    eResetReason;                           /*!< Reason for reset */
 616 } RGXFWIF_FWCCB_CMD_CONTEXT_RESET_DATA;
 617
 618
 619 typedef enum _RGXFWIF_FWCCB_CMD_TYPE_
 620 {
 621         RGXFWIF_FWCCB_CMD_ZSBUFFER_BACKING                              = 101,  /*!< Requests ZSBuffer to be backed with physical pages */
 622         RGXFWIF_FWCCB_CMD_ZSBUFFER_UNBACKING                    = 102,  /*!< Requests ZSBuffer to be unbacked */
 623         RGXFWIF_FWCCB_CMD_FREELIST_GROW                                 = 103,  /*!< Requests an on-demand freelist grow/shrink */
 624         RGXFWIF_FWCCB_CMD_FREELISTS_RECONSTRUCTION              = 104,  /*!< Requests freelists reconstruction */
 625         RGXFWIF_FWCCB_CMD_CONTEXT_RESET_NOTIFICATION    = 105,  /*!< Notifies host of a HWR event on a context */
 626         RGXFWIF_FWCCB_CMD_DEBUG_DUMP                                    = 106,  /*!< Requests an on-demand debug dump */
 627         RGXFWIF_FWCCB_CMD_UPDATE_STATS                                  = 107,  /*!< Requests an on-demand update on process stats */
 628 } RGXFWIF_FWCCB_CMD_TYPE;
 629
 630 typedef enum
 631 {
 632     RGXFWIF_FWCCB_CMD_UPDATE_NUM_PARTIAL_RENDERS=1,             /*!< PVRSRVStatsUpdateRenderContextStats should increase the value of the ui32TotalNumPartialRenders stat */
 633     RGXFWIF_FWCCB_CMD_UPDATE_NUM_OUT_OF_MEMORY,                 /*!< PVRSRVStatsUpdateRenderContextStats should increase the value of the ui32TotalNumOutOfMemory stat */
 634     RGXFWIF_FWCCB_CMD_UPDATE_NUM_TA_STORES,                             /*!< PVRSRVStatsUpdateRenderContextStats should increase the value of the ui32NumTAStores stat */
 635     RGXFWIF_FWCCB_CMD_UPDATE_NUM_3D_STORES,                             /*!< PVRSRVStatsUpdateRenderContextStats should increase the value of the ui32Num3DStores stat */
 636     RGXFWIF_FWCCB_CMD_UPDATE_NUM_SH_STORES,                             /*!< PVRSRVStatsUpdateRenderContextStats should increase the value of the ui32NumSHStores stat */
 637     RGXFWIF_FWCCB_CMD_UPDATE_NUM_CDM_STORES                             /*!< PVRSRVStatsUpdateRenderContextStats should increase the value of the ui32NumCDMStores stat */
 638 } RGXFWIF_FWCCB_CMD_UPDATE_STATS_TYPE;
 639
 640
 641 /* Firmware CCB command packet */
 642
 643 typedef struct
 644 {
 645     RGXFWIF_FWCCB_CMD_UPDATE_STATS_TYPE         eElementToUpdate;                       /*!< Element to update */
 646     IMG_PID                                                                     pidOwner;                                       /*!< The pid of the process whose stats are being updated */
 647     IMG_INT32                                                           i32AdjustmentValue;                     /*!< Adjustment to be made to the statistic */
 648 } RGXFWIF_FWCCB_CMD_UPDATE_STATS_DATA;
 649
 650 typedef struct _RGXFWIF_FWCCB_CMD_
 651 {
 652         RGXFWIF_FWCCB_CMD_TYPE                                  eCmdType;       /*!< Command type */
 653         union
 654         {
 655                 RGXFWIF_FWCCB_CMD_ZSBUFFER_BACKING_DATA                         sCmdZSBufferBacking;                    /*!< Data for Z/S-Buffer on-demand (un)backing*/
 656                 RGXFWIF_FWCCB_CMD_FREELIST_GS_DATA                                      sCmdFreeListGS;                                 /*!< Data for on-demand freelist grow/shrink */
 657                 RGXFWIF_FWCCB_CMD_FREELISTS_RECONSTRUCTION_DATA         sCmdFreeListsReconstruction;    /*!< Data for freelists reconstruction */
 658                 RGXFWIF_FWCCB_CMD_CONTEXT_RESET_DATA                            sCmdContextResetNotification;   /*!< Data for context reset notification */
 659         RGXFWIF_FWCCB_CMD_UPDATE_STATS_DATA                 sCmdUpdateStatsData;            /*!< Data for updating process stats */
 660         } RGXFW_ALIGN uCmdData;
 661 } RGXFW_ALIGN RGXFWIF_FWCCB_CMD;
 662
 663 RGX_FW_STRUCT_SIZE_ASSERT(RGXFWIF_FWCCB_CMD);
 664
 665 /*!
 666  ******************************************************************************
 667  * Signature and Checksums Buffer
 668  *****************************************************************************/
 669 typedef struct _RGXFWIF_SIGBUF_CTL_
 670 {
 671         PRGXFWIF_SIGBUFFER              psBuffer;                       /*!< Ptr to Signature Buffer memory */
 672         IMG_UINT32                              ui32LeftSizeInRegs;     /*!< Amount of space left for storing regs in the buffer */
 673 } UNCACHED_ALIGN RGXFWIF_SIGBUF_CTL;
 674
 675 /*!
 676  ******************************************************************************
 677  * Updated configuration post FW data init.
 678  *****************************************************************************/
 679 typedef struct _RGXFWIF_RUNTIME_CFG_
 680 {
 681         IMG_UINT32                              ui32ActivePMLatencyms;          /* APM latency in ms before signalling IDLE to the host */
 682         IMG_BOOL                                bActivePMLatencyPersistant;     /* If set, APM latency does not reset to system default each GPU power transition */
 683         IMG_UINT32                              ui32CoreClockSpeed;             /* Core clock speed, currently only used to calculate timer ticks */
 684 } RGXFWIF_RUNTIME_CFG;
 685
 686 /*!
 687  *****************************************************************************
 688  * Control data for RGX
 689  *****************************************************************************/
 690
 691 #define RGXFWIF_HWR_DEBUG_DUMP_ALL (99999)
 692
 693 #if defined(PDUMP)
 694
 695 #define RGXFWIF_PID_FILTER_MAX_NUM_PIDS 32
 696
 697 typedef enum _RGXFWIF_PID_FILTER_MODE_
 698 {
 699         RGXFW_PID_FILTER_INCLUDE_ALL_EXCEPT,
 700         RGXFW_PID_FILTER_EXCLUDE_ALL_EXCEPT
 701 } RGXFWIF_PID_FILTER_MODE;
 702
 703 typedef struct _RGXFWIF_PID_FILTER_ITEM_
 704 {
 705         IMG_PID uiPID;
 706         IMG_UINT32 ui32OSID;
 707 } RGXFW_ALIGN RGXFWIF_PID_FILTER_ITEM;
 708
 709 typedef struct _RGXFWIF_PID_FILTER_
 710 {
 711         RGXFWIF_PID_FILTER_MODE eMode;
 712         /* each process in the filter list is specified by a PID and OS ID pair.
 713          * each PID and OS pair is an item in the items array (asItems).
 714          * if the array contains less than RGXFWIF_PID_FILTER_MAX_NUM_PIDS entries
 715          * then it must be terminated by an item with pid of zero.
 716          */
 717         RGXFWIF_PID_FILTER_ITEM asItems[RGXFWIF_PID_FILTER_MAX_NUM_PIDS];
 718 } RGXFW_ALIGN RGXFWIF_PID_FILTER;
 719 #endif
 720
 721 typedef struct _RGXFWIF_INIT_
 722 {
 723         IMG_DEV_PHYADDR                 RGXFW_ALIGN sFaultPhysAddr;
 724
 725         IMG_DEV_VIRTADDR                RGXFW_ALIGN sPDSExecBase;
 726         IMG_DEV_VIRTADDR                RGXFW_ALIGN sUSCExecBase;
 727         IMG_DEV_VIRTADDR                RGXFW_ALIGN sResultDumpBase;
 728         IMG_DEV_VIRTADDR                RGXFW_ALIGN sDPXControlStreamBase;
 729         IMG_DEV_VIRTADDR                RGXFW_ALIGN sRTUHeapBase;
 730
 731         IMG_BOOL                                bFirstTA;
 732         IMG_BOOL                                bFirstRender;
 733         IMG_BOOL                                bFrameworkAfterInit;
 734         IMG_BOOL                                bEnableHWPerf;
 735         IMG_BOOL                bDisableFilterHWPerfCustomCounter;
 736         IMG_UINT32                              uiPowerSync;
 737         IMG_UINT32                              ui32FilterFlags;
 738
 739         /* Kernel CCBs */
 740         PRGXFWIF_CCB_CTL                psKernelCCBCtl[RGXFWIF_DM_MAX];
 741         PRGXFWIF_CCB                    psKernelCCB[RGXFWIF_DM_MAX];
 742
 743         /* Firmware CCBs */
 744         PRGXFWIF_CCB_CTL                psFirmwareCCBCtl[RGXFWIF_DM_MAX];
 745         PRGXFWIF_CCB                    psFirmwareCCB[RGXFWIF_DM_MAX];
 746
 747         RGXFWIF_DM                              eDM[RGXFWIF_DM_MAX];
 748
 749         RGXFWIF_SIGBUF_CTL              asSigBufCtl[RGXFWIF_DM_MAX];
 750
 751         IMG_BOOL                                bEnableLogging;
 752         IMG_UINT32                              ui32ConfigFlags;        /*!< Configuration flags from host */
 753         IMG_UINT32                              ui32BreakpointTemps;
 754         IMG_UINT32                              ui32BreakpointShareds;
 755         IMG_UINT32                              ui32HWRDebugDumpLimit;
 756         struct
 757         {
 758                 IMG_UINT64 uiBase;
 759                 IMG_UINT64 uiLen;
 760                 IMG_UINT64 uiXStride;
 761         }                       RGXFW_ALIGN sBifTilingCfg[RGXFWIF_NUM_BIF_TILING_CONFIGS];
 762
 763         PRGXFWIF_RUNTIME_CFG            psRuntimeCfg;
 764
 765         PRGXFWIF_TRACEBUF               psTraceBufCtl;
 766         PRGXFWIF_HWPERFINFO             psHWPerfInfoCtl;
 767         IMG_UINT64      RGXFW_ALIGN ui64HWPerfFilter;
 768
 769         PRGXFWIF_HWRINFOBUF             psRGXFWIfHWRInfoBufCtl;
 770         PRGXFWIF_GPU_UTIL_FWCB  psGpuUtilFWCbCtl;
 771         PRGXFWIF_REG_CFG                psRegCfg;
 772         PRGXFWIF_HWPERF_CTL                     psHWPerfCtl;
 773
 774 #if defined(RGXFW_ALIGNCHECKS)
 775 #if defined(RGX_FIRMWARE)
 776         IMG_UINT32*                             paui32AlignChecks;
 777 #else
 778         RGXFWIF_DEV_VIRTADDR    paui32AlignChecks;
 779 #endif
 780 #endif
 781
 782         /* Core clock speed at FW boot time */
 783         IMG_UINT32              ui32InitialCoreClockSpeed;
 784
 785         /* APM latency in ms before signalling IDLE to the host */
 786         IMG_UINT32                              ui32ActivePMLatencyms;
 787
 788         /* Flag to be set by the Firmware after successful start */
 789         IMG_BOOL                                bFirmwareStarted;
 790
 791         IMG_UINT32                              ui32FirmwareStartedTimeStamp;
 792
 793         IMG_UINT32                              ui32JonesDisableMask;
 794
 795         /* Compatibility checks to be populated by the Firmware */
 796         RGXFWIF_COMPCHECKS              sRGXCompChecks;
 797
 798         RGXFWIF_DMA_ADDR                sCorememDataStore;
 799
 800 #if defined(RGX_FEATURE_SLC_VIVT)
 801         IMG_DEV_VIRTADDR                RGXFW_ALIGN sSLC3FenceDevVAddr;
 802 #endif
 803
 804 #if defined(PDUMP)
 805         RGXFWIF_PID_FILTER sPIDFilter;
 806 #endif
 807
 808 } UNCACHED_ALIGN RGXFWIF_INIT;
 809
 810
 811 /*!
 812  ******************************************************************************
 813  * Client CCB commands which are only required by the kernel
 814  *****************************************************************************/
 815 typedef struct _RGXFWIF_CMD_PRIORITY_
 816 {
 817         IMG_UINT32                              ui32Priority;
 818 } RGXFWIF_CMD_PRIORITY;
 819
 820 /*!
 821  ******************************************************************************
 822  * RGXFW Unittests declarations
 823  *****************************************************************************/
 824 typedef struct _RGXFW_UNITTEST2_
 825 {
 826         /* Irq events */
 827         IMG_UINT32      ui32IrqKicksDM[RGXFWIF_DM_MAX_MTS];
 828         IMG_UINT32      ui32IrqKicksBg;
 829         IMG_UINT32      ui32IrqKicksTimer;
 830
 831         /* Bg events */
 832         IMG_UINT32      ui32BgKicksDM[RGXFWIF_DM_MAX_MTS];
 833         IMG_UINT32      ui32BgKicksCounted;
 834
 835 } RGXFW_UNITTEST2;
 836
 837 /*!
 838  ******************************************************************************
 839  * RGXFW_UNITTESTS declaration
 840  *****************************************************************************/
 841 #define RGXFW_UNITTEST_FWPING           (0x1)
 842 #define RGXFW_UNITTEST_FWPONG           (0x2)
 843
 844 #define RGXFW_UNITTEST_IS_BGKICK(DM)    ((DM) & 0x1)
 845
 846 typedef struct _RGXFW_UNITTESTS_
 847 {
 848         IMG_UINT32      ui32Status;
 849
 850         RGXFW_UNITTEST2 sUnitTest2;
 851
 852 } RGXFW_UNITTESTS;
 853
 854 #endif /*  __RGX_FWIF_KM_H__ */
 855
 856 /******************************************************************************
 857  End of file (rgx_fwif_km.h)
 858 ******************************************************************************/
 859
 860