drivers/gpu/rogue_m/include/system/rgx_tc/tcf_clk_ctrl.h

   1 /*************************************************************************/ /*!
   2 @Title          Test Chip Framework system control register definitions
   3 @Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
   4 @Description    Autogenerated C -- do not edit
   5                 Generated from: tcf_clk_ctrl.def
   6 @License        Dual MIT/GPLv2
   7
   8 The contents of this file are subject to the MIT license as set out below.
   9
  10 Permission is hereby granted, free of charge, to any person obtaining a copy
  11 of this software and associated documentation files (the "Software"), to deal
  12 in the Software without restriction, including without limitation the rights
  13 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  14 copies of the Software, and to permit persons to whom the Software is
  15 furnished to do so, subject to the following conditions:
  16
  17 The above copyright notice and this permission notice shall be included in
  18 all copies or substantial portions of the Software.
  19
  20 Alternatively, the contents of this file may be used under the terms of
  21 the GNU General Public License Version 2 ("GPL") in which case the provisions
  22 of GPL are applicable instead of those above.
  23
  24 If you wish to allow use of your version of this file only under the terms of
  25 GPL, and not to allow others to use your version of this file under the terms
  26 of the MIT license, indicate your decision by deleting the provisions above
  27 and replace them with the notice and other provisions required by GPL as set
  28 out in the file called "GPL-COPYING" included in this distribution. If you do
  29 not delete the provisions above, a recipient may use your version of this file
  30 under the terms of either the MIT license or GPL.
  31
  32 This License is also included in this distribution in the file called
  33 "MIT-COPYING".
  34
  35 EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
  36 PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
  37 BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  38 PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
  39 COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  40 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  41 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  42 */ /**************************************************************************/
  43
  44 #if !defined(_TCF_CLK_CTRL_H_)
  45 #define _TCF_CLK_CTRL_H_
  46
  47 /*
  48         Register FPGA_ID_REG
  49 */
  50 #define TCF_CLK_CTRL_FPGA_ID_REG            0x0000
  51 #define FPGA_ID_REG_CORE_CFG_MASK           0x0000FFFFU
  52 #define FPGA_ID_REG_CORE_CFG_SHIFT          0
  53 #define FPGA_ID_REG_CORE_CFG_SIGNED         0
  54
  55 #define FPGA_ID_REG_CORE_ID_MASK            0xFFFF0000U
  56 #define FPGA_ID_REG_CORE_ID_SHIFT           16
  57 #define FPGA_ID_REG_CORE_ID_SIGNED          0
  58
  59 /*
  60         Register FPGA_REV_REG
  61 */
  62 #define TCF_CLK_CTRL_FPGA_REV_REG           0x0008
  63 #define FPGA_REV_REG_MAINT_MASK             0x000000FFU
  64 #define FPGA_REV_REG_MAINT_SHIFT            0
  65 #define FPGA_REV_REG_MAINT_SIGNED           0
  66
  67 #define FPGA_REV_REG_MINOR_MASK             0x0000FF00U
  68 #define FPGA_REV_REG_MINOR_SHIFT            8
  69 #define FPGA_REV_REG_MINOR_SIGNED           0
  70
  71 #define FPGA_REV_REG_MAJOR_MASK             0x00FF0000U
  72 #define FPGA_REV_REG_MAJOR_SHIFT            16
  73 #define FPGA_REV_REG_MAJOR_SIGNED           0
  74
  75 #define FPGA_REV_REG_DESIGNER_MASK          0xFF000000U
  76 #define FPGA_REV_REG_DESIGNER_SHIFT         24
  77 #define FPGA_REV_REG_DESIGNER_SIGNED        0
  78
  79 /*
  80         Register FPGA_DES_REV_1
  81 */
  82 #define TCF_CLK_CTRL_FPGA_DES_REV_1         0x0010
  83 #define FPGA_DES_REV_1_MASK                 0xFFFFFFFFU
  84 #define FPGA_DES_REV_1_SHIFT                0
  85 #define FPGA_DES_REV_1_SIGNED               0
  86
  87 /*
  88         Register FPGA_DES_REV_2
  89 */
  90 #define TCF_CLK_CTRL_FPGA_DES_REV_2         0x0018
  91 #define FPGA_DES_REV_2_MASK                 0xFFFFFFFFU
  92 #define FPGA_DES_REV_2_SHIFT                0
  93 #define FPGA_DES_REV_2_SIGNED               0
  94
  95 /*
  96         Register TCF_CORE_ID_REG
  97 */
  98 #define TCF_CLK_CTRL_TCF_CORE_ID_REG        0x0020
  99 #define TCF_CORE_ID_REG_CORE_CFG_MASK       0x0000FFFFU
 100 #define TCF_CORE_ID_REG_CORE_CFG_SHIFT      0
 101 #define TCF_CORE_ID_REG_CORE_CFG_SIGNED     0
 102
 103 #define TCF_CORE_ID_REG_CORE_ID_MASK        0xFFFF0000U
 104 #define TCF_CORE_ID_REG_CORE_ID_SHIFT       16
 105 #define TCF_CORE_ID_REG_CORE_ID_SIGNED      0
 106
 107 /*
 108         Register TCF_CORE_REV_REG
 109 */
 110 #define TCF_CLK_CTRL_TCF_CORE_REV_REG       0x0028
 111 #define TCF_CORE_REV_REG_MAINT_MASK         0x000000FFU
 112 #define TCF_CORE_REV_REG_MAINT_SHIFT        0
 113 #define TCF_CORE_REV_REG_MAINT_SIGNED       0
 114
 115 #define TCF_CORE_REV_REG_MINOR_MASK         0x0000FF00U
 116 #define TCF_CORE_REV_REG_MINOR_SHIFT        8
 117 #define TCF_CORE_REV_REG_MINOR_SIGNED       0
 118
 119 #define TCF_CORE_REV_REG_MAJOR_MASK         0x00FF0000U
 120 #define TCF_CORE_REV_REG_MAJOR_SHIFT        16
 121 #define TCF_CORE_REV_REG_MAJOR_SIGNED       0
 122
 123 #define TCF_CORE_REV_REG_DESIGNER_MASK      0xFF000000U
 124 #define TCF_CORE_REV_REG_DESIGNER_SHIFT     24
 125 #define TCF_CORE_REV_REG_DESIGNER_SIGNED    0
 126
 127 /*
 128         Register TCF_CORE_DES_REV_1
 129 */
 130 #define TCF_CLK_CTRL_TCF_CORE_DES_REV_1     0x0030
 131 #define TCF_CORE_DES_REV_1_MASK             0xFFFFFFFFU
 132 #define TCF_CORE_DES_REV_1_SHIFT            0
 133 #define TCF_CORE_DES_REV_1_SIGNED           0
 134
 135 /*
 136         Register TCF_CORE_DES_REV_2
 137 */
 138 #define TCF_CLK_CTRL_TCF_CORE_DES_REV_2     0x0038
 139 #define TCF_CORE_DES_REV_2_MASK             0xFFFFFFFFU
 140 #define TCF_CORE_DES_REV_2_SHIFT            0
 141 #define TCF_CORE_DES_REV_2_SIGNED           0
 142
 143 /*
 144         Register SCB_GENERAL_CONTROL
 145 */
 146 #define TCF_CLK_CTRL_SCB_GENERAL_CONTROL    0x0040
 147 #define SCB_GC_TRANS_HALT_MASK              0x00000200U
 148 #define SCB_GC_TRANS_HALT_SHIFT             9
 149 #define SCB_GC_TRANS_HALT_SIGNED            0
 150
 151 #define SCB_GC_CKD_REGS_MASK                0x00000100U
 152 #define SCB_GC_CKD_REGS_SHIFT               8
 153 #define SCB_GC_CKD_REGS_SIGNED              0
 154
 155 #define SCB_GC_CKD_SLAVE_MASK               0x00000080U
 156 #define SCB_GC_CKD_SLAVE_SHIFT              7
 157 #define SCB_GC_CKD_SLAVE_SIGNED             0
 158
 159 #define SCB_GC_CKD_MASTER_MASK              0x00000040U
 160 #define SCB_GC_CKD_MASTER_SHIFT             6
 161 #define SCB_GC_CKD_MASTER_SIGNED            0
 162
 163 #define SCB_GC_CKD_XDATA_MASK               0x00000020U
 164 #define SCB_GC_CKD_XDATA_SHIFT              5
 165 #define SCB_GC_CKD_XDATA_SIGNED             0
 166
 167 #define SCB_GC_SFR_REG_MASK                 0x00000010U
 168 #define SCB_GC_SFR_REG_SHIFT                4
 169 #define SCB_GC_SFR_REG_SIGNED               0
 170
 171 #define SCB_GC_SFR_SLAVE_MASK               0x00000008U
 172 #define SCB_GC_SFR_SLAVE_SHIFT              3
 173 #define SCB_GC_SFR_SLAVE_SIGNED             0
 174
 175 #define SCB_GC_SFR_MASTER_MASK              0x00000004U
 176 #define SCB_GC_SFR_MASTER_SHIFT             2
 177 #define SCB_GC_SFR_MASTER_SIGNED            0
 178
 179 #define SCB_GC_SFR_DET_DATA_MASK            0x00000002U
 180 #define SCB_GC_SFR_DET_DATA_SHIFT           1
 181 #define SCB_GC_SFR_DET_DATA_SIGNED          0
 182
 183 #define SCB_GC_SFR_GEN_DATA_MASK            0x00000001U
 184 #define SCB_GC_SFR_GEN_DATA_SHIFT           0
 185 #define SCB_GC_SFR_GEN_DATA_SIGNED          0
 186
 187 /*
 188         Register SCB_MASTER_READ_COUNT
 189 */
 190 #define TCF_CLK_CTRL_SCB_MASTER_READ_COUNT  0x0048
 191 #define MASTER_READ_COUNT_MASK              0x0000FFFFU
 192 #define MASTER_READ_COUNT_SHIFT             0
 193 #define MASTER_READ_COUNT_SIGNED            0
 194
 195 /*
 196         Register SCB_MASTER_READ_DATA
 197 */
 198 #define TCF_CLK_CTRL_SCB_MASTER_READ_DATA   0x0050
 199 #define MASTER_READ_DATA_MASK               0x000000FFU
 200 #define MASTER_READ_DATA_SHIFT              0
 201 #define MASTER_READ_DATA_SIGNED             0
 202
 203 /*
 204         Register SCB_MASTER_ADDRESS
 205 */
 206 #define TCF_CLK_CTRL_SCB_MASTER_ADDRESS     0x0058
 207 #define SCB_MASTER_ADDRESS_MASK             0x000003FFU
 208 #define SCB_MASTER_ADDRESS_SHIFT            0
 209 #define SCB_MASTER_ADDRESS_SIGNED           0
 210
 211 /*
 212         Register SCB_MASTER_WRITE_DATA
 213 */
 214 #define TCF_CLK_CTRL_SCB_MASTER_WRITE_DATA  0x0060
 215 #define MASTER_WRITE_DATA_MASK              0x000000FFU
 216 #define MASTER_WRITE_DATA_SHIFT             0
 217 #define MASTER_WRITE_DATA_SIGNED            0
 218
 219 /*
 220         Register SCB_MASTER_WRITE_COUNT
 221 */
 222 #define TCF_CLK_CTRL_SCB_MASTER_WRITE_COUNT 0x0068
 223 #define MASTER_WRITE_COUNT_MASK             0x0000FFFFU
 224 #define MASTER_WRITE_COUNT_SHIFT            0
 225 #define MASTER_WRITE_COUNT_SIGNED           0
 226
 227 /*
 228         Register SCB_BUS_SELECT
 229 */
 230 #define TCF_CLK_CTRL_SCB_BUS_SELECT         0x0070
 231 #define BUS_SELECT_MASK                     0x00000003U
 232 #define BUS_SELECT_SHIFT                    0
 233 #define BUS_SELECT_SIGNED                   0
 234
 235 /*
 236         Register SCB_MASTER_FILL_STATUS
 237 */
 238 #define TCF_CLK_CTRL_SCB_MASTER_FILL_STATUS 0x0078
 239 #define MASTER_WRITE_FIFO_EMPTY_MASK        0x00000008U
 240 #define MASTER_WRITE_FIFO_EMPTY_SHIFT       3
 241 #define MASTER_WRITE_FIFO_EMPTY_SIGNED      0
 242
 243 #define MASTER_WRITE_FIFO_FULL_MASK         0x00000004U
 244 #define MASTER_WRITE_FIFO_FULL_SHIFT        2
 245 #define MASTER_WRITE_FIFO_FULL_SIGNED       0
 246
 247 #define MASTER_READ_FIFO_EMPTY_MASK         0x00000002U
 248 #define MASTER_READ_FIFO_EMPTY_SHIFT        1
 249 #define MASTER_READ_FIFO_EMPTY_SIGNED       0
 250
 251 #define MASTER_READ_FIFO_FULL_MASK          0x00000001U
 252 #define MASTER_READ_FIFO_FULL_SHIFT         0
 253 #define MASTER_READ_FIFO_FULL_SIGNED        0
 254
 255 /*
 256         Register CLK_AND_RST_CTRL
 257 */
 258 #define TCF_CLK_CTRL_CLK_AND_RST_CTRL       0x0080
 259 #define GLB_CLKG_EN_MASK                    0x00020000U
 260 #define GLB_CLKG_EN_SHIFT                   17
 261 #define GLB_CLKG_EN_SIGNED                  0
 262
 263 #define CLK_GATE_CNTL_MASK                  0x00010000U
 264 #define CLK_GATE_CNTL_SHIFT                 16
 265 #define CLK_GATE_CNTL_SIGNED                0
 266
 267 #define DUT_DCM_RESETN_MASK                 0x00000400U
 268 #define DUT_DCM_RESETN_SHIFT                10
 269 #define DUT_DCM_RESETN_SIGNED               0
 270
 271 #define MEM_RESYNC_BYPASS_MASK              0x00000200U
 272 #define MEM_RESYNC_BYPASS_SHIFT             9
 273 #define MEM_RESYNC_BYPASS_SIGNED            0
 274
 275 #define SYS_RESYNC_BYPASS_MASK              0x00000100U
 276 #define SYS_RESYNC_BYPASS_SHIFT             8
 277 #define SYS_RESYNC_BYPASS_SIGNED            0
 278
 279 #define SCB_RESETN_MASK                     0x00000010U
 280 #define SCB_RESETN_SHIFT                    4
 281 #define SCB_RESETN_SIGNED                   0
 282
 283 #define PDP2_RESETN_MASK                    0x00000008U
 284 #define PDP2_RESETN_SHIFT                   3
 285 #define PDP2_RESETN_SIGNED                  0
 286
 287 #define PDP1_RESETN_MASK                    0x00000004U
 288 #define PDP1_RESETN_SHIFT                   2
 289 #define PDP1_RESETN_SIGNED                  0
 290
 291 #define DDR_RESETN_MASK                     0x00000002U
 292 #define DDR_RESETN_SHIFT                    1
 293 #define DDR_RESETN_SIGNED                   0
 294
 295 #define DUT_RESETN_MASK                     0x00000001U
 296 #define DUT_RESETN_SHIFT                    0
 297 #define DUT_RESETN_SIGNED                   0
 298
 299 /*
 300         Register TEST_REG_OUT
 301 */
 302 #define TCF_CLK_CTRL_TEST_REG_OUT           0x0088
 303 #define TEST_REG_OUT_MASK                   0xFFFFFFFFU
 304 #define TEST_REG_OUT_SHIFT                  0
 305 #define TEST_REG_OUT_SIGNED                 0
 306
 307 /*
 308         Register TEST_REG_IN
 309 */
 310 #define TCF_CLK_CTRL_TEST_REG_IN            0x0090
 311 #define TEST_REG_IN_MASK                    0xFFFFFFFFU
 312 #define TEST_REG_IN_SHIFT                   0
 313 #define TEST_REG_IN_SIGNED                  0
 314
 315 /*
 316         Register TEST_CTRL
 317 */
 318 #define TCF_CLK_CTRL_TEST_CTRL              0x0098
 319 #define PCI_TEST_OFFSET_MASK                0xF8000000U
 320 #define PCI_TEST_OFFSET_SHIFT               27
 321 #define PCI_TEST_OFFSET_SIGNED              0
 322
 323 #define HOST_PHY_MODE_MASK                  0x00000100U
 324 #define HOST_PHY_MODE_SHIFT                 8
 325 #define HOST_PHY_MODE_SIGNED                0
 326
 327 #define HOST_ONLY_MODE_MASK                 0x00000080U
 328 #define HOST_ONLY_MODE_SHIFT                7
 329 #define HOST_ONLY_MODE_SIGNED               0
 330
 331 #define PCI_TEST_MODE_MASK                  0x00000040U
 332 #define PCI_TEST_MODE_SHIFT                 6
 333 #define PCI_TEST_MODE_SIGNED                0
 334
 335 #define TURN_OFF_DDR_MASK                   0x00000020U
 336 #define TURN_OFF_DDR_SHIFT                  5
 337 #define TURN_OFF_DDR_SIGNED                 0
 338
 339 #define SYS_RD_CLK_INV_MASK                 0x00000010U
 340 #define SYS_RD_CLK_INV_SHIFT                4
 341 #define SYS_RD_CLK_INV_SIGNED               0
 342
 343 #define MEM_REQ_CLK_INV_MASK                0x00000008U
 344 #define MEM_REQ_CLK_INV_SHIFT               3
 345 #define MEM_REQ_CLK_INV_SIGNED              0
 346
 347 #define BURST_SPLIT_MASK                    0x00000004U
 348 #define BURST_SPLIT_SHIFT                   2
 349 #define BURST_SPLIT_SIGNED                  0
 350
 351 #define CLK_INVERSION_MASK                  0x00000002U
 352 #define CLK_INVERSION_SHIFT                 1
 353 #define CLK_INVERSION_SIGNED                0
 354
 355 #define ADDRESS_FORCE_MASK                  0x00000001U
 356 #define ADDRESS_FORCE_SHIFT                 0
 357 #define ADDRESS_FORCE_SIGNED                0
 358
 359 /*
 360         Register CLEAR_HOST_MEM_SIG
 361 */
 362 #define TCF_CLK_CTRL_CLEAR_HOST_MEM_SIG     0x00A0
 363 #define SIGNATURE_TAG_ID_MASK               0x00000F00U
 364 #define SIGNATURE_TAG_ID_SHIFT              8
 365 #define SIGNATURE_TAG_ID_SIGNED             0
 366
 367 #define CLEAR_HOST_MEM_SIGNATURE_MASK       0x00000001U
 368 #define CLEAR_HOST_MEM_SIGNATURE_SHIFT      0
 369 #define CLEAR_HOST_MEM_SIGNATURE_SIGNED     0
 370
 371 /*
 372         Register HOST_MEM_SIGNATURE
 373 */
 374 #define TCF_CLK_CTRL_HOST_MEM_SIGNATURE     0x00A8
 375 #define HOST_MEM_SIGNATURE_MASK             0xFFFFFFFFU
 376 #define HOST_MEM_SIGNATURE_SHIFT            0
 377 #define HOST_MEM_SIGNATURE_SIGNED           0
 378
 379 /*
 380         Register INTERRUPT_STATUS
 381 */
 382 #define TCF_CLK_CTRL_INTERRUPT_STATUS       0x00C8
 383 #define INTERRUPT_MASTER_STATUS_MASK        0x80000000U
 384 #define INTERRUPT_MASTER_STATUS_SHIFT       31
 385 #define INTERRUPT_MASTER_STATUS_SIGNED      0
 386
 387 #define OTHER_INTS_MASK                     0x7FFE0000U
 388 #define OTHER_INTS_SHIFT                    17
 389 #define OTHER_INTS_SIGNED                   0
 390
 391 #define HOST_MST_NORESPONSE_MASK            0x00010000U
 392 #define HOST_MST_NORESPONSE_SHIFT           16
 393 #define HOST_MST_NORESPONSE_SIGNED          0
 394
 395 #define PDP2_INT_MASK                       0x00008000U
 396 #define PDP2_INT_SHIFT                      15
 397 #define PDP2_INT_SIGNED                     0
 398
 399 #define PDP1_INT_MASK                       0x00004000U
 400 #define PDP1_INT_SHIFT                      14
 401 #define PDP1_INT_SIGNED                     0
 402
 403 #define EXT_INT_MASK                        0x00002000U
 404 #define EXT_INT_SHIFT                       13
 405 #define EXT_INT_SIGNED                      0
 406
 407 #define SCB_MST_HLT_BIT_MASK                0x00001000U
 408 #define SCB_MST_HLT_BIT_SHIFT               12
 409 #define SCB_MST_HLT_BIT_SIGNED              0
 410
 411 #define SCB_SLV_EVENT_MASK                  0x00000800U
 412 #define SCB_SLV_EVENT_SHIFT                 11
 413 #define SCB_SLV_EVENT_SIGNED                0
 414
 415 #define SCB_TDONE_RX_MASK                   0x00000400U
 416 #define SCB_TDONE_RX_SHIFT                  10
 417 #define SCB_TDONE_RX_SIGNED                 0
 418
 419 #define SCB_SLV_WT_RD_DAT_MASK              0x00000200U
 420 #define SCB_SLV_WT_RD_DAT_SHIFT             9
 421 #define SCB_SLV_WT_RD_DAT_SIGNED            0
 422
 423 #define SCB_SLV_WT_PRV_RD_MASK              0x00000100U
 424 #define SCB_SLV_WT_PRV_RD_SHIFT             8
 425 #define SCB_SLV_WT_PRV_RD_SIGNED            0
 426
 427 #define SCB_SLV_WT_WR_DAT_MASK              0x00000080U
 428 #define SCB_SLV_WT_WR_DAT_SHIFT             7
 429 #define SCB_SLV_WT_WR_DAT_SIGNED            0
 430
 431 #define SCB_MST_WT_RD_DAT_MASK              0x00000040U
 432 #define SCB_MST_WT_RD_DAT_SHIFT             6
 433 #define SCB_MST_WT_RD_DAT_SIGNED            0
 434
 435 #define SCB_ADD_ACK_ERR_MASK                0x00000020U
 436 #define SCB_ADD_ACK_ERR_SHIFT               5
 437 #define SCB_ADD_ACK_ERR_SIGNED              0
 438
 439 #define SCB_WR_ACK_ERR_MASK                 0x00000010U
 440 #define SCB_WR_ACK_ERR_SHIFT                4
 441 #define SCB_WR_ACK_ERR_SIGNED               0
 442
 443 #define SCB_SDAT_LO_TIM_MASK                0x00000008U
 444 #define SCB_SDAT_LO_TIM_SHIFT               3
 445 #define SCB_SDAT_LO_TIM_SIGNED              0
 446
 447 #define SCB_SCLK_LO_TIM_MASK                0x00000004U
 448 #define SCB_SCLK_LO_TIM_SHIFT               2
 449 #define SCB_SCLK_LO_TIM_SIGNED              0
 450
 451 #define SCB_UNEX_START_BIT_MASK             0x00000002U
 452 #define SCB_UNEX_START_BIT_SHIFT            1
 453 #define SCB_UNEX_START_BIT_SIGNED           0
 454
 455 #define SCB_BUS_INACTIVE_MASK               0x00000001U
 456 #define SCB_BUS_INACTIVE_SHIFT              0
 457 #define SCB_BUS_INACTIVE_SIGNED             0
 458
 459 /*
 460         Register INTERRUPT_OP_CFG
 461 */
 462 #define TCF_CLK_CTRL_INTERRUPT_OP_CFG       0x00D0
 463 #define PULSE_NLEVEL_MASK                   0x80000000U
 464 #define PULSE_NLEVEL_SHIFT                  31
 465 #define PULSE_NLEVEL_SIGNED                 0
 466
 467 #define INT_SENSE_MASK                      0x40000000U
 468 #define INT_SENSE_SHIFT                     30
 469 #define INT_SENSE_SIGNED                    0
 470
 471 #define INTERRUPT_DEST_MASK                 0x0000000FU
 472 #define INTERRUPT_DEST_SHIFT                0
 473 #define INTERRUPT_DEST_SIGNED               0
 474
 475 /*
 476         Register INTERRUPT_ENABLE
 477 */
 478 #define TCF_CLK_CTRL_INTERRUPT_ENABLE       0x00D8
 479 #define INTERRUPT_MASTER_ENABLE_MASK        0x80000000U
 480 #define INTERRUPT_MASTER_ENABLE_SHIFT       31
 481 #define INTERRUPT_MASTER_ENABLE_SIGNED      0
 482
 483 #define INTERRUPT_ENABLE_MASK               0x7FFFFFFFU
 484 #define INTERRUPT_ENABLE_SHIFT              0
 485 #define INTERRUPT_ENABLE_SIGNED             0
 486
 487 /*
 488         Register INTERRUPT_CLEAR
 489 */
 490 #define TCF_CLK_CTRL_INTERRUPT_CLEAR        0x00E0
 491 #define INTERRUPT_MASTER_CLEAR_MASK         0x80000000U
 492 #define INTERRUPT_MASTER_CLEAR_SHIFT        31
 493 #define INTERRUPT_MASTER_CLEAR_SIGNED       0
 494
 495 #define INTERRUPT_CLEAR_MASK                0x7FFFFFFFU
 496 #define INTERRUPT_CLEAR_SHIFT               0
 497 #define INTERRUPT_CLEAR_SIGNED              0
 498
 499 /*
 500         Register YCC_RGB_CTRL
 501 */
 502 #define TCF_CLK_CTRL_YCC_RGB_CTRL           0x00E8
 503 #define RGB_CTRL1_MASK                      0x000001FFU
 504 #define RGB_CTRL1_SHIFT                     0
 505 #define RGB_CTRL1_SIGNED                    0
 506
 507 #define RGB_CTRL2_MASK                      0x01FF0000U
 508 #define RGB_CTRL2_SHIFT                     16
 509 #define RGB_CTRL2_SIGNED                    0
 510
 511 /*
 512         Register EXP_BRD_CTRL
 513 */
 514 #define TCF_CLK_CTRL_EXP_BRD_CTRL           0x00F8
 515 #define PDP1_DATA_EN_MASK                   0x00000003U
 516 #define PDP1_DATA_EN_SHIFT                  0
 517 #define PDP1_DATA_EN_SIGNED                 0
 518
 519 #define PDP2_DATA_EN_MASK                   0x00000030U
 520 #define PDP2_DATA_EN_SHIFT                  4
 521 #define PDP2_DATA_EN_SIGNED                 0
 522
 523 #define EXP_BRD_OUTPUT_MASK                 0xFFFFFF00U
 524 #define EXP_BRD_OUTPUT_SHIFT                8
 525 #define EXP_BRD_OUTPUT_SIGNED               0
 526
 527 /*
 528         Register HOSTIF_CONTROL
 529 */
 530 #define TCF_CLK_CTRL_HOSTIF_CONTROL         0x0100
 531 #define HOSTIF_CTRL_MASK                    0x000000FFU
 532 #define HOSTIF_CTRL_SHIFT                   0
 533 #define HOSTIF_CTRL_SIGNED                  0
 534
 535 /*
 536         Register DUT_CONTROL_1
 537 */
 538 #define TCF_CLK_CTRL_DUT_CONTROL_1          0x0108
 539 #define DUT_CTRL_1_MASK                     0xFFFFFFFFU
 540 #define DUT_CTRL_1_SHIFT                    0
 541 #define DUT_CTRL_1_SIGNED                   0
 542
 543 /* TC ES2 additional needs those: */
 544 #define DUT_CTRL_TEST_MODE_SHIFT            0
 545 #define DUT_CTRL_TEST_MODE_MASK             0x3
 546
 547 #define DUT_CTRL_VCC_0V9EN                  (1<<12)
 548 #define DUT_CTRL_VCC_1V8EN                  (1<<13)
 549 #define DUT_CTRL_VCC_IO_INH                 (1<<14)
 550 #define DUT_CTRL_VCC_CORE_INH               (1<<15)
 551
 552 /*
 553         Register DUT_STATUS_1
 554 */
 555 #define TCF_CLK_CTRL_DUT_STATUS_1           0x0110
 556 #define DUT_STATUS_1_MASK                   0xFFFFFFFFU
 557 #define DUT_STATUS_1_SHIFT                  0
 558 #define DUT_STATUS_1_SIGNED                 0
 559
 560 /*
 561         Register DUT_CTRL_NOT_STAT_1
 562 */
 563 #define TCF_CLK_CTRL_DUT_CTRL_NOT_STAT_1    0x0118
 564 #define DUT_STAT_NOT_CTRL_1_MASK            0xFFFFFFFFU
 565 #define DUT_STAT_NOT_CTRL_1_SHIFT           0
 566 #define DUT_STAT_NOT_CTRL_1_SIGNED          0
 567
 568 /*
 569         Register DUT_CONTROL_2
 570 */
 571 #define TCF_CLK_CTRL_DUT_CONTROL_2          0x0120
 572 #define DUT_CTRL_2_MASK                     0xFFFFFFFFU
 573 #define DUT_CTRL_2_SHIFT                    0
 574 #define DUT_CTRL_2_SIGNED                   0
 575
 576 /*
 577         Register DUT_STATUS_2
 578 */
 579 #define TCF_CLK_CTRL_DUT_STATUS_2           0x0128
 580 #define DUT_STATUS_2_MASK                   0xFFFFFFFFU
 581 #define DUT_STATUS_2_SHIFT                  0
 582 #define DUT_STATUS_2_SIGNED                 0
 583
 584 /*
 585         Register DUT_CTRL_NOT_STAT_2
 586 */
 587 #define TCF_CLK_CTRL_DUT_CTRL_NOT_STAT_2    0x0130
 588 #define DUT_CTRL_NOT_STAT_2_MASK            0xFFFFFFFFU
 589 #define DUT_CTRL_NOT_STAT_2_SHIFT           0
 590 #define DUT_CTRL_NOT_STAT_2_SIGNED          0
 591
 592 /*
 593         Register BUS_CAP_BASE_ADDR
 594 */
 595 #define TCF_CLK_CTRL_BUS_CAP_BASE_ADDR      0x0138
 596 #define BUS_CAP_BASE_ADDR_MASK              0xFFFFFFFFU
 597 #define BUS_CAP_BASE_ADDR_SHIFT             0
 598 #define BUS_CAP_BASE_ADDR_SIGNED            0
 599
 600 /*
 601         Register BUS_CAP_ENABLE
 602 */
 603 #define TCF_CLK_CTRL_BUS_CAP_ENABLE         0x0140
 604 #define BUS_CAP_ENABLE_MASK                 0x00000001U
 605 #define BUS_CAP_ENABLE_SHIFT                0
 606 #define BUS_CAP_ENABLE_SIGNED               0
 607
 608 /*
 609         Register BUS_CAP_COUNT
 610 */
 611 #define TCF_CLK_CTRL_BUS_CAP_COUNT          0x0148
 612 #define BUS_CAP_COUNT_MASK                  0xFFFFFFFFU
 613 #define BUS_CAP_COUNT_SHIFT                 0
 614 #define BUS_CAP_COUNT_SIGNED                0
 615
 616 /*
 617         Register DCM_LOCK_STATUS
 618 */
 619 #define TCF_CLK_CTRL_DCM_LOCK_STATUS        0x0150
 620 #define DCM_LOCK_STATUS_MASK                0x00000007U
 621 #define DCM_LOCK_STATUS_SHIFT               0
 622 #define DCM_LOCK_STATUS_SIGNED              0
 623
 624 /*
 625         Register AUX_DUT_RESETNS
 626 */
 627 #define TCF_CLK_CTRL_AUX_DUT_RESETNS        0x0158
 628 #define AUX_DUT_RESETNS_MASK                0x0000000FU
 629 #define AUX_DUT_RESETNS_SHIFT               0
 630 #define AUX_DUT_RESETNS_SIGNED              0
 631
 632 /*
 633         Register TCF_SPI_MST_ADDR_RDNWR
 634 */
 635 #define TCF_CLK_CTRL_TCF_SPI_MST_ADDR_RDNWR 0x0160
 636 #define TCF_SPI_MST_ADDR_MASK               0x00000FFFU
 637 #define TCF_SPI_MST_ADDR_SHIFT              0
 638 #define TCF_SPI_MST_ADDR_SIGNED             0
 639
 640 #define TCF_SPI_MST_RDNWR_MASK              0x00001000U
 641 #define TCF_SPI_MST_RDNWR_SHIFT             12
 642 #define TCF_SPI_MST_RDNWR_SIGNED            0
 643
 644 #define TCF_SPI_MST_SLAVE_ID_MASK           0x00010000U
 645 #define TCF_SPI_MST_SLAVE_ID_SHIFT          16
 646 #define TCF_SPI_MST_SLAVE_ID_SIGNED         0
 647
 648 /*
 649         Register TCF_SPI_MST_WDATA
 650 */
 651 #define TCF_CLK_CTRL_TCF_SPI_MST_WDATA      0x0168
 652 #define TCF_SPI_MST_WDATA_MASK              0xFFFFFFFFU
 653 #define TCF_SPI_MST_WDATA_SHIFT             0
 654 #define TCF_SPI_MST_WDATA_SIGNED            0
 655
 656 /*
 657         Register TCF_SPI_MST_RDATA
 658 */
 659 #define TCF_CLK_CTRL_TCF_SPI_MST_RDATA      0x0170
 660 #define TCF_SPI_MST_RDATA_MASK              0xFFFFFFFFU
 661 #define TCF_SPI_MST_RDATA_SHIFT             0
 662 #define TCF_SPI_MST_RDATA_SIGNED            0
 663
 664 /*
 665         Register TCF_SPI_MST_STATUS
 666 */
 667 #define TCF_CLK_CTRL_TCF_SPI_MST_STATUS     0x0178
 668 #define TCF_SPI_MST_STATUS_MASK             0x0000000FU
 669 #define TCF_SPI_MST_STATUS_SHIFT            0
 670 #define TCF_SPI_MST_STATUS_SIGNED           0
 671
 672 /*
 673         Register TCF_SPI_MST_GO
 674 */
 675 #define TCF_CLK_CTRL_TCF_SPI_MST_GO         0x0180
 676 #define TCF_SPI_MST_GO_MASK                 0x00000001U
 677 #define TCF_SPI_MST_GO_SHIFT                0
 678 #define TCF_SPI_MST_GO_SIGNED               0
 679
 680 /*
 681         Register EXT_SIG_CTRL
 682 */
 683 #define TCF_CLK_CTRL_EXT_SIG_CTRL           0x0188
 684 #define EXT_SYS_REQ_SIG_START_MASK          0x00000001U
 685 #define EXT_SYS_REQ_SIG_START_SHIFT         0
 686 #define EXT_SYS_REQ_SIG_START_SIGNED        0
 687
 688 #define EXT_SYS_RD_SIG_START_MASK           0x00000002U
 689 #define EXT_SYS_RD_SIG_START_SHIFT          1
 690 #define EXT_SYS_RD_SIG_START_SIGNED         0
 691
 692 #define EXT_MEM_REQ_SIG_START_MASK          0x00000004U
 693 #define EXT_MEM_REQ_SIG_START_SHIFT         2
 694 #define EXT_MEM_REQ_SIG_START_SIGNED        0
 695
 696 #define EXT_MEM_RD_SIG_START_MASK           0x00000008U
 697 #define EXT_MEM_RD_SIG_START_SHIFT          3
 698 #define EXT_MEM_RD_SIG_START_SIGNED         0
 699
 700 /*
 701         Register EXT_SYS_REQ_SIG
 702 */
 703 #define TCF_CLK_CTRL_EXT_SYS_REQ_SIG        0x0190
 704 #define EXT_SYS_REQ_SIG_MASK                0xFFFFFFFFU
 705 #define EXT_SYS_REQ_SIG_SHIFT               0
 706 #define EXT_SYS_REQ_SIG_SIGNED              0
 707
 708 /*
 709         Register EXT_SYS_RD_SIG
 710 */
 711 #define TCF_CLK_CTRL_EXT_SYS_RD_SIG         0x0198
 712 #define EXT_SYS_RD_SIG_MASK                 0xFFFFFFFFU
 713 #define EXT_SYS_RD_SIG_SHIFT                0
 714 #define EXT_SYS_RD_SIG_SIGNED               0
 715
 716 /*
 717         Register EXT_MEM_REQ_SIG
 718 */
 719 #define TCF_CLK_CTRL_EXT_MEM_REQ_SIG        0x01A0
 720 #define EXT_MEM_REQ_SIG_MASK                0xFFFFFFFFU
 721 #define EXT_MEM_REQ_SIG_SHIFT               0
 722 #define EXT_MEM_REQ_SIG_SIGNED              0
 723
 724 /*
 725         Register EXT_MEM_RD_SIG
 726 */
 727 #define TCF_CLK_CTRL_EXT_MEM_RD_SIG         0x01A8
 728 #define EXT_MEM_RD_SIG_MASK                 0xFFFFFFFFU
 729 #define EXT_MEM_RD_SIG_SHIFT                0
 730 #define EXT_MEM_RD_SIG_SIGNED               0
 731
 732 /*
 733         Register EXT_SYS_REQ_WR_CNT
 734 */
 735 #define TCF_CLK_CTRL_EXT_SYS_REQ_WR_CNT     0x01B0
 736 #define EXT_SYS_REQ_WR_CNT_MASK             0xFFFFFFFFU
 737 #define EXT_SYS_REQ_WR_CNT_SHIFT            0
 738 #define EXT_SYS_REQ_WR_CNT_SIGNED           0
 739
 740 /*
 741         Register EXT_SYS_REQ_RD_CNT
 742 */
 743 #define TCF_CLK_CTRL_EXT_SYS_REQ_RD_CNT     0x01B8
 744 #define EXT_SYS_REQ_RD_CNT_MASK             0xFFFFFFFFU
 745 #define EXT_SYS_REQ_RD_CNT_SHIFT            0
 746 #define EXT_SYS_REQ_RD_CNT_SIGNED           0
 747
 748 /*
 749         Register EXT_SYS_RD_CNT
 750 */
 751 #define TCF_CLK_CTRL_EXT_SYS_RD_CNT         0x01C0
 752 #define EXT_SYS_RD_CNT_MASK                 0xFFFFFFFFU
 753 #define EXT_SYS_RD_CNT_SHIFT                0
 754 #define EXT_SYS_RD_CNT_SIGNED               0
 755
 756 /*
 757         Register EXT_MEM_REQ_WR_CNT
 758 */
 759 #define TCF_CLK_CTRL_EXT_MEM_REQ_WR_CNT     0x01C8
 760 #define EXT_MEM_REQ_WR_CNT_MASK             0xFFFFFFFFU
 761 #define EXT_MEM_REQ_WR_CNT_SHIFT            0
 762 #define EXT_MEM_REQ_WR_CNT_SIGNED           0
 763
 764 /*
 765         Register EXT_MEM_REQ_RD_CNT
 766 */
 767 #define TCF_CLK_CTRL_EXT_MEM_REQ_RD_CNT     0x01D0
 768 #define EXT_MEM_REQ_RD_CNT_MASK             0xFFFFFFFFU
 769 #define EXT_MEM_REQ_RD_CNT_SHIFT            0
 770 #define EXT_MEM_REQ_RD_CNT_SIGNED           0
 771
 772 /*
 773         Register EXT_MEM_RD_CNT
 774 */
 775 #define TCF_CLK_CTRL_EXT_MEM_RD_CNT         0x01D8
 776 #define EXT_MEM_RD_CNT_MASK                 0xFFFFFFFFU
 777 #define EXT_MEM_RD_CNT_SHIFT                0
 778 #define EXT_MEM_RD_CNT_SIGNED               0
 779
 780 /*
 781         Register TCF_CORE_TARGET_BUILD_CFG
 782 */
 783 #define TCF_CLK_CTRL_TCF_CORE_TARGET_BUILD_CFG 0x01E0
 784 #define TCF_CORE_TARGET_BUILD_ID_MASK       0x000000FFU
 785 #define TCF_CORE_TARGET_BUILD_ID_SHIFT      0
 786 #define TCF_CORE_TARGET_BUILD_ID_SIGNED     0
 787
 788 /*
 789         Register MEM_THROUGH_SYS
 790 */
 791 #define TCF_CLK_CTRL_MEM_THROUGH_SYS        0x01E8
 792 #define MEM_THROUGH_SYS_MASK                0x00000001U
 793 #define MEM_THROUGH_SYS_SHIFT               0
 794 #define MEM_THROUGH_SYS_SIGNED              0
 795
 796 /*
 797         Register HOST_PHY_OFFSET
 798 */
 799 #define TCF_CLK_CTRL_HOST_PHY_OFFSET        0x01F0
 800 #define HOST_PHY_OFFSET_MASK                0xFFFFFFFFU
 801 #define HOST_PHY_OFFSET_SHIFT               0
 802 #define HOST_PHY_OFFSET_SIGNED              0
 803
 804 #endif /* !defined(_TCF_CLK_CTRL_H_) */
 805
 806 /*****************************************************************************
 807  End of file (tcf_clk_ctrl.h)
 808 *****************************************************************************/