1 /*************************************************************************/ /*!
3 @Title RGX HWPerf Types and Defines Header
4 @Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
5 @Description Common data types definitions for hardware performance API
6 @License Dual MIT/GPLv2
8 The contents of this file are subject to the MIT license as set out below.
10 Permission is hereby granted, free of charge, to any person obtaining a copy
11 of this software and associated documentation files (the "Software"), to deal
12 in the Software without restriction, including without limitation the rights
13 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
14 copies of the Software, and to permit persons to whom the Software is
15 furnished to do so, subject to the following conditions:
17 The above copyright notice and this permission notice shall be included in
18 all copies or substantial portions of the Software.
20 Alternatively, the contents of this file may be used under the terms of
21 the GNU General Public License Version 2 ("GPL") in which case the provisions
22 of GPL are applicable instead of those above.
24 If you wish to allow use of your version of this file only under the terms of
25 GPL, and not to allow others to use your version of this file under the terms
26 of the MIT license, indicate your decision by deleting the provisions above
27 and replace them with the notice and other provisions required by GPL as set
28 out in the file called "GPL-COPYING" included in this distribution. If you do
29 not delete the provisions above, a recipient may use your version of this file
30 under the terms of either the MIT license or GPL.
32 This License is also included in this distribution in the file called
35 EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
36 PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
37 BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
38 PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
39 COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
40 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
41 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
42 */ /**************************************************************************/
43 #ifndef RGX_HWPERF_KM_H_
44 #define RGX_HWPERF_KM_H_
47 * This header file holds the HWPerf related macros and types needed by the
48 * code in the Kernel Mode (KM) server/driver module and its content is
49 * intended to be suitable for distribution under a public software license.
50 * The definitions within are common and may be used in user-mode, kernel-mode
51 * and firmware compilation units.
54 #if defined (__cplusplus)
58 #define RGX_HWPERF_V2_FORMAT 2
60 #include "rgx_common.h"
63 /******************************************************************************
64 * Data Stream Common Types
65 *****************************************************************************/
67 /* These structures are used on both GPU and CPU and must be a size that is a
68 * multiple of 64 bits, 8 bytes to allow the FW to write 8 byte quantities
69 * at 8 byte aligned addresses. BLD_ASSERT() is used to check this.
72 /*! Type used to encode the event that generated the HW performance packet.
73 * NOTE: When this type is updated the corresponding hwperfbin2json tool source
74 * needs to be updated as well. Also need to update the table in rgxhwperf.c.
75 * The RGX_HWPERF_EVENT_MASK_* macros will also need updating when adding new
80 RGX_HWPERF_INVALID = 0x00,
81 /* FW types 0x01..0x07 */
82 RGX_HWPERF_FW_BGSTART = 0x01,
83 RGX_HWPERF_FW_BGEND = 0x02,
84 RGX_HWPERF_FW_IRQSTART = 0x03,
86 RGX_HWPERF_FW_IRQEND = 0x04,
87 RGX_HWPERF_FW_DBGSTART = 0x05,
88 RGX_HWPERF_FW_DBGEND = 0x06,
90 /* HW types 0x08..0x18 */
91 RGX_HWPERF_HW_TAKICK = 0x08,
92 RGX_HWPERF_HW_TAFINISHED = 0x09,
93 RGX_HWPERF_HW_3DTQKICK = 0x0A,
94 /* RGX_HWPERF_HW_3DTQFINISHED = 0x17, */
95 /* RGX_HWPERF_HW_3DSPMKICK = 0x11, */
96 /* RGX_HWPERF_HW_3DSPMFINISHED = 0x18, */
97 RGX_HWPERF_HW_3DKICK = 0x0B,
99 RGX_HWPERF_HW_3DFINISHED = 0x0C,
100 RGX_HWPERF_HW_CDMKICK = 0x0D,
101 RGX_HWPERF_HW_CDMFINISHED = 0x0E,
102 RGX_HWPERF_HW_TLAKICK = 0x0F,
104 RGX_HWPERF_HW_TLAFINISHED = 0x10,
105 RGX_HWPERF_HW_3DSPMKICK = 0x11,
106 RGX_HWPERF_HW_PERIODIC = 0x12,
107 RGX_HWPERF_HW_RTUKICK = 0x13,
109 RGX_HWPERF_HW_RTUFINISHED = 0x14,
110 RGX_HWPERF_HW_SHGKICK = 0x15,
111 RGX_HWPERF_HW_SHGFINISHED = 0x16,
112 RGX_HWPERF_HW_3DTQFINISHED = 0x17,
114 RGX_HWPERF_HW_3DSPMFINISHED = 0x18,
116 /* other types 0x1A..0x1F */
117 RGX_HWPERF_CLKS_CHG = 0x1A,
118 RGX_HWPERF_GPU_STATE_CHG = 0x1B,
120 /* power types 0x20..0x27 */
121 RGX_HWPERF_PWR_EST_REQUEST = 0x20,
122 RGX_HWPERF_PWR_EST_READY = 0x21,
123 RGX_HWPERF_PWR_EST_RESULT = 0x22,
124 RGX_HWPERF_PWR_CHG = 0x23,
126 /* context switch types 0x30..0x31 */
127 RGX_HWPERF_CSW_START = 0x30,
128 RGX_HWPERF_CSW_FINISHED = 0x31,
131 RGX_HWPERF_LAST_TYPE,
133 /* This enumeration must have a value that is a power of two as it is
134 * used in masks and a filter bit field (currently 64 bits long).
136 RGX_HWPERF_MAX_TYPE = 0x40
137 } RGX_HWPERF_EVENT_TYPE;
139 /* The event type values are incrementing integers for use as a shift ordinal
140 * in the event filtering process at the point events are generated.
141 * This scheme thus implies a limit of 63 event types.
143 BLD_ASSERT((RGX_HWPERF_LAST_TYPE<RGX_HWPERF_MAX_TYPE), rgx_hwperf_h)
145 /*! Type obsolete and will be removed in a later release, use RGXFWIF_DM */
146 typedef RGXFWIF_DM RGX_HWPERF_DM;
147 #define RGX_HWPERF_DM_GP RGXFWIF_DM_GP
148 #define RGX_HWPERF_DM_2D RGXFWIF_DM_2D
149 #define RGX_HWPERF_DM_TA RGXFWIF_DM_TA
150 #define RGX_HWPERF_DM_3D RGXFWIF_DM_3D
151 #define RGX_HWPERF_DM_CDM RGXFWIF_DM_CDM
152 #define RGX_HWPERF_DM_RTU RGXFWIF_DM_RTU
153 #define RGX_HWPERF_DM_SHG RGXFWIF_DM_SHG
154 #define RGX_HWPERF_DM_LAST RGXFWIF_DM_LAST
157 /******************************************************************************
158 * Packet Format Version 2 Types
159 *****************************************************************************/
161 /*! Signature ASCII pattern 'HWP2' found in the first word of a HWPerfV2 packet
163 #define HWPERF_PACKET_V2_SIG 0x48575032
164 /*! Signature ASCII pattern 'HWPA' found in the first word of a HWPerfV2a packet
166 #define HWPERF_PACKET_V2A_SIG 0x48575041
168 /*! Signature ASCII pattern 'HWPB' found in the first word of a HWPerfV2b packet
170 #define HWPERF_PACKET_V2B_SIG 0x48575042
172 #define HWPERF_PACKET_ISVALID(_ptr) (((_ptr) == HWPERF_PACKET_V2_SIG) || ((_ptr) == HWPERF_PACKET_V2A_SIG)|| ((_ptr) == HWPERF_PACKET_V2B_SIG))
174 /*! This structure defines version 2 of the packet format which is
175 * based around a header and a variable length data payload structure.
176 * The address of the next packet can be found by adding the ui16Size field
177 * in the header to the current packet address.
178 * Producers of packets must always ensure the size field is a multiple of 8
179 * as packets must start on an 8-byte granular address.
183 /* HEADER - packet header fields common to all packet types */
184 IMG_UINT32 ui32Sig; /*!< Always the value HWPERF_PACKET_SIG */
186 IMG_UINT32 ui32Size; /*!< Overall packet size in bytes, includes
187 * header and payload. Size is a 16-bit field
188 * stored in the 16 LSb. 16 MSb reserved.
189 * Use RGX_HWPERF_MAKE_SIZE_* and RGX_HWPERF_GET_SIZE
190 * macros to set/get, never write directly. */
192 IMG_UINT32 eTypeId; /*!< Includes event type and META thread ID in
193 * the 16 LSb. 16 MSb reserved.
194 * Use RGX_HWPERF_MAKE_TYPEID and RGX_HWPERF_GET_*
195 * macros to set/get, never write directly. */
197 IMG_UINT32 ui32Ordinal; /*!< Sequential number of the packet */
198 IMG_UINT64 ui64RGXTimer; /*!< Value of RGX_CR_TIMER at event */
200 /* PAYLOAD - bytes from this point on in the buffer are from the
201 * RGX_HWPERF_V2_PACKET_DATA union which encodes the payload data specific
202 * to the event type set in the header. When the structure in the union
203 * has a variable length member e.g. HW packets the payload length
206 } RGX_HWPERF_V2_PACKET_HDR, *RGX_PHWPERF_V2_PACKET_HDR;
208 RGX_FW_STRUCT_OFFSET_ASSERT(RGX_HWPERF_V2_PACKET_HDR, ui64RGXTimer)
210 RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_V2_PACKET_HDR)
213 /*! Mask for use with the IMG_UINT32 ui32Size header field */
214 #define RGX_HWPERF_SIZE_MASK 0xFFFFU
216 /*! Macro which takes a structure name and provides the packet size for
217 * a fixed size payload packet for assignment to the ui16Size field. */
218 #define RGX_HWPERF_MAKE_SIZE_FIXED(_struct) ((IMG_UINT32)(RGX_HWPERF_SIZE_MASK&(sizeof(RGX_HWPERF_V2_PACKET_HDR)+sizeof(_struct))))
220 /*! Macro which takes the number of bytes written in the data payload of a
221 * packet for a variable size payload packet, rounds it up to 8 bytes where
222 * it may be assigned to the ui16Size field. */
223 #define RGX_HWPERF_MAKE_SIZE_VARIABLE(_size) ((IMG_UINT32)(RGX_HWPERF_SIZE_MASK&(sizeof(RGX_HWPERF_V2_PACKET_HDR)+PVR_ALIGN(_size, 8))))
225 /*! Macro to obtain the size of the packet */
226 #define RGX_HWPERF_GET_SIZE(_packet_addr) ((IMG_UINT16)(((_packet_addr)->ui32Size) & RGX_HWPERF_SIZE_MASK))
228 /*! Macro to obtain the size of the packet data */
229 #define RGX_HWPERF_GET_DATA_SIZE(_packet_addr) (RGX_HWPERF_GET_SIZE(_packet_addr) - sizeof(RGX_HWPERF_V2_PACKET_HDR))
232 /*! Masks for use with the IMG_UINT32 eTypeId header field */
233 #define RGX_HWPERF_TYPEID_MASK 0xFFFFU
234 #define RGX_HWPERF_TYPEID_THREAD_MASK 0x8000U
235 #define RGX_HWPERF_TYPEID_EVENT_MASK (RGX_HWPERF_MAX_TYPE-1)
237 /*! Meta thread macros for encoding the ID into the type field of a packet */
238 #define RGX_HWPERF_META_THREAD_SHIFT 15U
239 #define RGX_HWPERF_META_THREAD_ID0 0x0U
240 #define RGX_HWPERF_META_THREAD_ID1 0x1U
241 /*! Obsolete, kept for source compatibility */
242 #define RGX_HWPERF_META_THREAD_MASK 0x1U
244 /*! Macros used to set the packet type and encode meta thread ID (0|1) within */
245 #define RGX_HWPERF_MAKE_TYPEID(_type,_thread) ((IMG_UINT32) ((RGX_HWPERF_TYPEID_THREAD_MASK&((_thread)<<RGX_HWPERF_META_THREAD_SHIFT)) | (RGX_HWPERF_TYPEID_EVENT_MASK&(_type))))
247 /*! Obtains the event type that generated the packet */
248 #define RGX_HWPERF_GET_TYPE(_packet_addr) (((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_EVENT_MASK)
250 /*! Obtains the META Thread number that generated the packet */
251 #define RGX_HWPERF_GET_THREAD_ID(_packet_addr) (((((_packet_addr)->eTypeId)&RGX_HWPERF_TYPEID_THREAD_MASK) >> RGX_HWPERF_META_THREAD_SHIFT))
253 /*! Macros to obtain a typed pointer to a packet or data structure given a packet address */
254 #define RGX_HWPERF_GET_PACKET(_buffer_addr) ((RGX_HWPERF_V2_PACKET_HDR*) (_buffer_addr))
255 #define RGX_HWPERF_GET_PACKET_DATA_BYTES(_packet_addr) ((IMG_BYTE*) ( ((IMG_BYTE*)(_packet_addr)) +sizeof(RGX_HWPERF_V2_PACKET_HDR) ) )
256 #define RGX_HWPERF_GET_NEXT_PACKET(_packet_addr) ((RGX_HWPERF_V2_PACKET_HDR*) ( ((IMG_BYTE*)(_packet_addr))+(RGX_HWPERF_SIZE_MASK&(_packet_addr)->ui32Size)) )
258 /*! Obtains a typed pointer to a packet header given the packed data address */
259 #define RGX_HWPERF_GET_PACKET_HEADER(_packet_addr) ((RGX_HWPERF_V2_PACKET_HDR*) ( ((IMG_BYTE*)(_packet_addr)) - sizeof(RGX_HWPERF_V2_PACKET_HDR) ))
262 /*! Masks for use with the IMG_UINT32 ui32BlkInfo field */
263 #define RGX_HWPERF_BLKINFO_BLKCOUNT_MASK 0xFFFF0000U
264 #define RGX_HWPERF_BLKINFO_BLKOFFSET_MASK 0x0000FFFFU
266 /*! Shift for the NumBlocks and counter block offset field in ui32BlkInfo */
267 #define RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT 16U
268 #define RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT 0U
270 /*! Macro used to set the block info word as a combination of two 16-bit integers */
271 #define RGX_HWPERF_MAKE_BLKINFO(_numblks,_blkoffset) ((IMG_UINT32) ((RGX_HWPERF_BLKINFO_BLKCOUNT_MASK&((_numblks) << RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT)) | (RGX_HWPERF_BLKINFO_BLKOFFSET_MASK&((_blkoffset) << RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT))))
273 /*! Macro used to obtain get the number of counter blocks present in the packet */
274 #define RGX_HWPERF_GET_BLKCOUNT(_blkinfo) ((_blkinfo & RGX_HWPERF_BLKINFO_BLKCOUNT_MASK) >> RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT)
276 /*! Obtains the offset of the counter block stream in the packet */
277 #define RGX_HWPERF_GET_BLKOFFSET(_blkinfo) ((_blkinfo & RGX_HWPERF_BLKINFO_BLKOFFSET_MASK) >> RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT)
279 /* This is the maximum frame contexts that are supported in the driver at the moment */
280 #define RGX_HWPERF_HW_MAX_WORK_CONTEXT 2
281 /*! This structure holds the field data of a Hardware packet.
283 #define RGX_HWPERF_HW_DATA_FIELDS_LIST \
284 IMG_UINT32 ui32DMCyc; /*!< DataMaster cycle count register, 0 if none */\
285 IMG_UINT32 ui32FrameNum; /*!< Frame number */\
286 IMG_UINT32 ui32PID; /*!< Process identifier */\
287 IMG_UINT32 ui32DMContext; /*!< RenderContext for a TA,3D, Compute context for CDM, etc. */\
288 IMG_UINT32 ui32RenderTarget; /*!< RenderTarget for a TA,3D, 0x0 otherwise */\
289 IMG_UINT32 ui32ExtJobRef; /*!< Externally provided job reference used to track work for debugging purposes */\
290 IMG_UINT32 ui32IntJobRef; /*!< Internally provided job reference used to track work for debugging purposes */\
291 IMG_UINT32 ui32TimeCorrIndex; /*!< Index to the time correlation at the time the packet was generated */\
292 IMG_UINT32 ui32BlkInfo; /*!< <31..16> NumBlocks <15..0> Counterblock stream offset */\
293 IMG_UINT32 ui32WorkContext; /*!< Work context number. Frame number for RTU DM, 0x0 otherwise */
297 RGX_HWPERF_HW_DATA_FIELDS_LIST
298 } RGX_HWPERF_HW_DATA_FIELDS;
300 RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_HW_DATA_FIELDS)
303 /******************************************************************************
305 *****************************************************************************/
308 /*! Mask macros for use with RGXCtrlHWPerf() API.
309 * RGX_HWPERF_EVENT_ALL is obsolete, use RGX_HWPERF_EVENT_MASK_ALL
311 #define RGX_HWPERF_EVENT_MASK_NONE (IMG_UINT64_C(0x0000000000000000))
312 #define RGX_HWPERF_EVENT_MASK_ALL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
313 #define RGX_HWPERF_EVENT_MASK_ALL_FW (IMG_UINT64_C(0x000000000000007E))
314 #define RGX_HWPERF_EVENT_MASK_HW_KICKFINISH (IMG_UINT64_C(0x0000000001FBFF00))
315 #define RGX_HWPERF_EVENT_MASK_HW_PERIODIC (IMG_UINT64_C(0x0000000000040000))
316 #define RGX_HWPERF_EVENT_MASK_ALL_HW (RGX_HWPERF_EVENT_MASK_HW_KICKFINISH \
317 | RGX_HWPERF_EVENT_MASK_HW_PERIODIC)
318 #define RGX_HWPERF_EVENT_MASK_ALL_PWR_EST (IMG_UINT64_C(0X0000000700000000))
319 #define RGX_HWPERF_EVENT_MASK_ALL_PWR (IMG_UINT64_C(0X0000000800000000))
320 #define RGX_HWPERF_EVENT_MASK_VALUE(e) (((IMG_UINT64)1)<<(e))
322 /*! Type used in the RGX API RGXConfigureAndEnableHWPerfCounters()
323 * It is used to configure the performance counter module in a layout
324 * block and allows one or more counters in the block to be
325 * configured in one operation based on the counter select mask. The bit
326 * shifts for this are the values in RGX_HWPERF_CNTBLK_COUNTER_ID. This mask
327 * also encodes which values in the arrays are valid, for example, if bit 1 set
328 * then aui8Mode[1], aui16GroupSelect[1], aui16BitSelect[1], aui32BatchMax[1],
329 * and aui32BatchMin[1] must be set. If these array elements are all set to
330 * 0 then the counter will not count and will not be in the HW event,
331 * effectively disabling the counter from the callers point of view.
332 * If any are non zero then the counter will be included in the HW event.
334 * Each layout block has 4 or 6 counters that can be programmed independently to
335 * profile the performance of a HW block. Each counter can be configured to
336 * accumulate statistics from 1 of 32 counter groups defined for that block.
337 * Each counter group can have up to 16 signals/bits defined that can be
338 * selected. Each counter may accumulate in one of two modes.
339 * See hwdefs/regapiperf.h for block/group/signal definitions.
341 typedef struct _RGX_HWPERF_CONFIG_CNTBLK_
343 /*! Counter block ID, see RGX_HWPERF_CNTBLK_ID */
344 IMG_UINT16 ui16BlockID;
346 /*! 4 or 6 LSBs are a mask of which counters to configure. Bit 0 is counter 0,
347 * bit 1 is counter 1 on so on. */
348 IMG_UINT8 ui8CounterSelect;
350 /*! 4 or 6 LSBs 0 for counting 1's in the group, 1 for treating the group
351 * signals as a number for unsigned addition. Bit 0 is counter 0, bit 1 is
352 * counter 1 on so on. This member relates to the MODE field
353 * in the RGX_CR_<N>_PERF_SELECTm register for each counter */
356 /*! 5 or 6 LSBs used as the GROUP_SELECT field in the RGX_CR_<N>_PERF_SELECTm
357 * register. Array index 0 is counter 0, index 1 is counter 1 and so on. */
358 IMG_UINT8 aui8GroupSelect[RGX_HWPERF_CNTRS_IN_BLK];
360 /*! 16 LSBs used as the BIT_SELECT field in the RGX_CR_<N>_PERF_SELECTm
361 * register. Array indexes relate to counters as above. */
362 IMG_UINT16 aui16BitSelect[RGX_HWPERF_CNTRS_IN_BLK];
364 /*! 14 LSBs used as the BATCH_MAX field in the RGX_CR_<N>_PERF_SELECTm
365 * register. Array indexes relate to counters as above. */
366 IMG_UINT32 aui32BatchMax[RGX_HWPERF_CNTRS_IN_BLK];
368 /*! 14 LSBs used as the BATCH_MIN field in the RGX_CR_<N>_PERF_SELECTm
369 * register. Array indexes relate to counters as above. */
370 IMG_UINT32 aui32BatchMin[RGX_HWPERF_CNTRS_IN_BLK];
371 } UNCACHED_ALIGN RGX_HWPERF_CONFIG_CNTBLK;
373 RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_CONFIG_CNTBLK)
376 #if defined (__cplusplus)
380 #endif /* RGX_HWPERF_KM_H_ */
382 /******************************************************************************
384 ******************************************************************************/