drivers/gpu/rogue/services/server/devices/rgx/rgxdevice.h

   1 /*************************************************************************/ /*!
   2 @File
   3 @Title          RGX device node header file
   4 @Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
   5 @Description    Header for the RGX device node
   6 @License        Dual MIT/GPLv2
   7
   8 The contents of this file are subject to the MIT license as set out below.
   9
  10 Permission is hereby granted, free of charge, to any person obtaining a copy
  11 of this software and associated documentation files (the "Software"), to deal
  12 in the Software without restriction, including without limitation the rights
  13 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  14 copies of the Software, and to permit persons to whom the Software is
  15 furnished to do so, subject to the following conditions:
  16
  17 The above copyright notice and this permission notice shall be included in
  18 all copies or substantial portions of the Software.
  19
  20 Alternatively, the contents of this file may be used under the terms of
  21 the GNU General Public License Version 2 ("GPL") in which case the provisions
  22 of GPL are applicable instead of those above.
  23
  24 If you wish to allow use of your version of this file only under the terms of
  25 GPL, and not to allow others to use your version of this file under the terms
  26 of the MIT license, indicate your decision by deleting the provisions above
  27 and replace them with the notice and other provisions required by GPL as set
  28 out in the file called "GPL-COPYING" included in this distribution. If you do
  29 not delete the provisions above, a recipient may use your version of this file
  30 under the terms of either the MIT license or GPL.
  31
  32 This License is also included in this distribution in the file called
  33 "MIT-COPYING".
  34
  35 EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
  36 PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
  37 BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  38 PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
  39 COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  40 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  41 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  42 */ /**************************************************************************/
  43
  44 #if !defined(__RGXDEVICE_H__)
  45 #define __RGXDEVICE_H__
  46
  47 #include "img_types.h"
  48 #include "pvrsrv_device_types.h"
  49 #include "mmu_common.h"
  50 #include "rgx_fwif_km.h"
  51 #include "rgx_fwif.h"
  52 #include "rgxscript.h"
  53 #include "cache_external.h"
  54 #include "device.h"
  55 #include "osfunc.h"
  56
  57 typedef struct _RGX_SERVER_COMMON_CONTEXT_ RGX_SERVER_COMMON_CONTEXT;
  58
  59 typedef struct {
  60         DEVMEM_MEMDESC          *psFWFrameworkMemDesc;
  61         IMG_DEV_VIRTADDR        *psMCUFenceAddr;
  62 } RGX_COMMON_CONTEXT_INFO;
  63
  64
  65 /*!
  66  ******************************************************************************
  67  * Device state flags
  68  *****************************************************************************/
  69 #define RGXKM_DEVICE_STATE_ZERO_FREELIST                        (0x1 << 0)              /*!< Zeroing the physical pages of reconstructed free lists */
  70 #define RGXKM_DEVICE_STATE_FTRACE_EN                            (0x1 << 1)              /*!< Used to enable device FTrace thread to consume HWPerf data */
  71 #define RGXKM_DEVICE_STATE_DISABLE_DW_LOGGING_EN        (0x1 << 2)              /*!< Used to disable the Devices Watchdog logging */
  72
  73 /*!
  74  ******************************************************************************
  75  * GPU DVFS History CB
  76  *****************************************************************************/
  77
  78 #define RGX_GPU_DVFS_HIST_SIZE 200  /* History size must NOT be greater than 4096 (2^12) */
  79
  80 typedef struct _RGX_GPU_DVFS_HIST_
  81 {
  82         IMG_UINT32               ui32CurrentDVFSId;              /*!< Current history entry index */
  83         IMG_UINT32                               aui32DVFSClockCB[RGX_GPU_DVFS_HIST_SIZE];   /*!< Circular buffer of DVFS clock history in Hz */
  84 } RGX_GPU_DVFS_HIST;
  85
  86 typedef struct _RGXFWIF_GPU_UTIL_STATS_
  87 {
  88         IMG_BOOL                bValid;                                 /* If TRUE, statistics are valid.
  89                                                                                            It might be FALSE if DVFS frequency is not provided by system layer (see RGX_TIMING_INFORMATION::ui32CoreClockSpeed)
  90                                                                                            or if the driver couldn't acquire the PowerLock */
  91         IMG_BOOL                bIncompleteData;                /* TRUE when the host couldn't find enough data to cover the whole time window, so the returned values could be wrong */
  92         IMG_UINT32              ui32GpuStatActiveHigh;  /* GPU active high ratio expressed in 0,01% units */
  93         IMG_UINT32              ui32GpuStatActiveLow;   /* GPU active low (i.e. TLA active only) ratio expressed in 0,01% units */
  94         IMG_UINT32              ui32GpuStatBlocked;             /* GPU blocked ratio expressed in 0,01% units */
  95         IMG_UINT32              ui32GpuStatIdle;                /* GPU idle ratio expressed in 0,01% units */
  96 } RGXFWIF_GPU_UTIL_STATS;
  97
  98 typedef struct _RGX_REG_CONFIG_
  99 {
 100         IMG_BOOL                        bEnabled;
 101         RGXFWIF_PWR_EVT         ePowerIslandToPush;
 102         IMG_UINT32              ui32NumRegRecords;
 103 } RGX_REG_CONFIG;
 104
 105 typedef struct _PVRSRV_STUB_PBDESC_ PVRSRV_STUB_PBDESC;
 106
 107 /* there is a corresponding define in rgxapi.h */
 108 #define RGX_MAX_TIMER_QUERIES 16
 109
 110 /*!
 111  ******************************************************************************
 112  * RGX Device info
 113  *****************************************************************************/
 114
 115 typedef struct _PVRSRV_RGXDEV_INFO_
 116 {
 117         PVRSRV_DEVICE_TYPE              eDeviceType;
 118         PVRSRV_DEVICE_CLASS             eDeviceClass;
 119         PVRSRV_DEVICE_NODE              *psDeviceNode;
 120
 121         IMG_UINT8                               ui8VersionMajor;
 122         IMG_UINT8                               ui8VersionMinor;
 123         IMG_UINT32                              ui32CoreConfig;
 124         IMG_UINT32                              ui32CoreFlags;
 125
 126         IMG_BOOL                bFirmwareInitialised;
 127         IMG_BOOL                                bPDPEnabled;
 128
 129         /* Kernel mode linear address of device registers */
 130         IMG_PVOID                               pvRegsBaseKM;
 131
 132
 133         IMG_HANDLE                              hRegMapping;
 134
 135         /* System physical address of device registers*/
 136         IMG_CPU_PHYADDR                 sRegsPhysBase;
 137         /*  Register region size in bytes */
 138         IMG_UINT32                              ui32RegSize;
 139
 140         PVRSRV_STUB_PBDESC              *psStubPBDescListKM;
 141
 142     IMG_BOOL                            bEnableProcessStats;
 143
 144         /* Firmware memory context info */
 145         DEVMEM_CONTEXT                  *psKernelDevmemCtx;
 146         DEVMEM_HEAP                             *psFirmwareHeap;
 147         MMU_CONTEXT                             *psKernelMMUCtx;
 148         IMG_UINT32                              ui32KernelCatBaseIdReg;
 149         IMG_UINT32                              ui32KernelCatBaseId;
 150         IMG_UINT32                              ui32KernelCatBaseReg;
 151         IMG_UINT32                              ui32KernelCatBaseWordSize;
 152         IMG_UINT32                              ui32KernelCatBaseAlignShift;
 153         IMG_UINT32                              ui32KernelCatBaseShift;
 154         IMG_UINT64                              ui64KernelCatBaseMask;
 155
 156         IMG_VOID                                *pvDeviceMemoryHeap;
 157
 158         /* Kernel CCBs */
 159         DEVMEM_MEMDESC                  *apsKernelCCBCtlMemDesc[RGXFWIF_DM_MAX];        /*!< memdesc for kernel CCB control */
 160         RGXFWIF_CCB_CTL                 *apsKernelCCBCtl[RGXFWIF_DM_MAX];                       /*!< kernel CCB control kernel mapping */
 161         DEVMEM_MEMDESC                  *apsKernelCCBMemDesc[RGXFWIF_DM_MAX];           /*!< memdesc for kernel CCB */
 162         IMG_UINT8                               *apsKernelCCB[RGXFWIF_DM_MAX];                          /*!< kernel CCB kernel mapping */
 163
 164         /* Firmware CCBs */
 165         DEVMEM_MEMDESC                  *apsFirmwareCCBCtlMemDesc[RGXFWIF_DM_MAX];      /*!< memdesc for Firmware CCB control */
 166         RGXFWIF_CCB_CTL                 *apsFirmwareCCBCtl[RGXFWIF_DM_MAX];                     /*!< kernel CCB control Firmware mapping */
 167         DEVMEM_MEMDESC                  *apsFirmwareCCBMemDesc[RGXFWIF_DM_MAX];         /*!< memdesc for Firmware CCB */
 168         IMG_UINT8                               *apsFirmwareCCB[RGXFWIF_DM_MAX];                                /*!< kernel CCB Firmware mapping */
 169
 170         /*
 171                 if we don't preallocate the pagetables we must
 172                 insert newly allocated page tables dynamically
 173         */
 174         IMG_VOID                                *pvMMUContextList;
 175
 176         IMG_UINT32                              ui32ClkGateStatusReg;
 177         IMG_UINT32                              ui32ClkGateStatusMask;
 178         RGX_SCRIPTS                             *psScripts;
 179
 180         DEVMEM_MEMDESC                  *psRGXFWCodeMemDesc;
 181         DEVMEM_EXPORTCOOKIE             sRGXFWCodeExportCookie;
 182
 183         DEVMEM_MEMDESC                  *psRGXFWDataMemDesc;
 184         DEVMEM_EXPORTCOOKIE             sRGXFWDataExportCookie;
 185
 186         DEVMEM_MEMDESC                  *psRGXFWCorememMemDesc;
 187         DEVMEM_EXPORTCOOKIE             sRGXFWCorememExportCookie;
 188
 189         DEVMEM_MEMDESC                  *psRGXFWIfTraceBufCtlMemDesc;
 190         RGXFWIF_TRACEBUF                *psRGXFWIfTraceBuf;
 191
 192         DEVMEM_MEMDESC                  *psRGXFWIfHWRInfoBufCtlMemDesc;
 193         RGXFWIF_HWRINFOBUF              *psRGXFWIfHWRInfoBuf;
 194
 195         DEVMEM_MEMDESC                  *psRGXFWIfGpuUtilFWCbCtlMemDesc;
 196         RGXFWIF_GPU_UTIL_FWCB   *psRGXFWIfGpuUtilFWCb;
 197
 198         DEVMEM_MEMDESC                  *psRGXFWIfHWPerfBufMemDesc;
 199         IMG_BYTE                                *psRGXFWIfHWPerfBuf;
 200         IMG_UINT32                              ui32RGXFWIfHWPerfBufSize; /* in bytes */
 201
 202         DEVMEM_MEMDESC                  *psRGXFWIfCorememDataStoreMemDesc;
 203
 204         DEVMEM_MEMDESC                  *psRGXFWIfRegCfgMemDesc;
 205
 206         DEVMEM_MEMDESC                  *psRGXFWIfInitMemDesc;
 207
 208         DEVMEM_MEMDESC                  *psRGXFWIfRuntimeCfgMemDesc;
 209         RGXFWIF_RUNTIME_CFG             *psRGXFWIfRuntimeCfg;
 210
 211 #if defined(RGXFW_ALIGNCHECKS)
 212         DEVMEM_MEMDESC                  *psRGXFWAlignChecksMemDesc;
 213 #endif
 214
 215         DEVMEM_MEMDESC                  *psRGXFWSigTAChecksMemDesc;
 216         IMG_UINT32                              ui32SigTAChecksSize;
 217
 218         DEVMEM_MEMDESC                  *psRGXFWSig3DChecksMemDesc;
 219         IMG_UINT32                              ui32Sig3DChecksSize;
 220
 221 #if defined(RGX_FEATURE_RAY_TRACING)
 222         DEVMEM_MEMDESC                  *psRGXFWSigRTChecksMemDesc;
 223         IMG_UINT32                              ui32SigRTChecksSize;
 224
 225         DEVMEM_MEMDESC                  *psRGXFWSigSHChecksMemDesc;
 226         IMG_UINT32                              ui32SigSHChecksSize;
 227 #endif
 228
 229         IMG_VOID                                *pvLISRData;
 230         IMG_VOID                                *pvMISRData;
 231         IMG_VOID                                *pvAPMISRData;
 232
 233         DEVMEM_MEMDESC                  *psRGXFaultAddressMemDesc;
 234
 235 #if defined(FIX_HW_BRN_37200)
 236         DEVMEM_MEMDESC                  *psRGXFWHWBRN37200MemDesc;
 237 #endif
 238
 239 #if defined(RGX_FEATURE_SLC_VIVT)
 240         DEVMEM_MEMDESC                  *psSLC3FenceMemDesc;
 241 #endif
 242
 243 #if defined (PDUMP)
 244         IMG_BOOL                                abDumpedKCCBCtlAlready[RGXFWIF_DM_MAX];
 245
 246 #endif
 247
 248         /*! Handles to the lock and stream objects used to transport
 249          * HWPerf data to user side clients. See RGXHWPerfInit() RGXHWPerfDeinit().
 250          * Set during initialisation if the application hint turns bit 7
 251          * 'Enable HWPerf' on in the ConfigFlags sent to the FW. FW stores this
 252          * bit in the RGXFW_CTL.ui32StateFlags member. They may also get
 253          * set by the API RGXCtrlHWPerf(). Thus these members may be 0 if HWPerf is
 254          * not enabled as these members are created on demand and destroyed at
 255          * driver unload.
 256          */
 257         POS_LOCK                                hLockHWPerfStream;
 258         IMG_HANDLE                              hHWPerfStream;
 259 #if defined(SUPPORT_GPUTRACE_EVENTS)
 260         IMG_HANDLE                              hGPUTraceCmdCompleteHandle;
 261         IMG_BOOL                                bFTraceGPUEventsEnabled;
 262         IMG_HANDLE                              hGPUTraceTLConnection;
 263         IMG_HANDLE                              hGPUTraceTLStream;
 264         IMG_UINT64                              ui64LastSampledTimeCorrOSTimeStamp;
 265 #endif
 266
 267         /* If we do 10 deferred memory allocations per second, then the ID would warp around after 13 years */
 268         IMG_UINT32                              ui32ZSBufferCurrID;     /*!< ID assigned to the next deferred devmem allocation */
 269         IMG_UINT32                              ui32FreelistCurrID;     /*!< ID assigned to the next freelist */
 270
 271         POS_LOCK                                hLockZSBuffer;          /*!< Lock to protect simultaneous access to ZSBuffers */
 272         DLLIST_NODE                             sZSBufferHead;          /*!< List of on-demand ZSBuffers */
 273         POS_LOCK                                hLockFreeList;          /*!< Lock to protect simultaneous access to Freelists */
 274         DLLIST_NODE                             sFreeListHead;          /*!< List of growable Freelists */
 275         PSYNC_PRIM_CONTEXT              hSyncPrimContext;
 276         PVRSRV_CLIENT_SYNC_PRIM *psPowSyncPrim;
 277
 278         IMG_UINT32                              ui32ActivePMReqOk;
 279         IMG_UINT32                              ui32ActivePMReqDenied;
 280         IMG_UINT32                              ui32ActivePMReqTotal;
 281
 282         IMG_HANDLE                              hProcessQueuesMISR;
 283
 284         IMG_UINT32                              ui32DeviceFlags;        /*!< Flags to track general device state  */
 285
 286         /* Poll data for detecting firmware fatal errors */
 287         IMG_UINT32  aui32CrLastPollAddr[RGXFW_THREAD_NUM];
 288         IMG_UINT32  ui32KCCBCmdsExecutedLastTime;
 289         IMG_BOOL    bKCCBCmdsWaitingLastTime;
 290         IMG_UINT32  ui32GEOTimeoutsLastTime;
 291
 292         /* Client stall detection */
 293         IMG_BOOL        bStalledClient;
 294
 295         /* Timer Queries */
 296         IMG_UINT32     ui32ActiveQueryId;       /*!< id of the active line */
 297         IMG_BOOL       bSaveStart;              /*!< save the start time of the next kick on the device*/
 298         IMG_BOOL       bSaveEnd;                /*!< save the end time of the next kick on the device*/
 299
 300         DEVMEM_MEMDESC * psStartTimeMemDesc;    /*!< memdesc for Start Times */
 301         IMG_UINT64     * pui64StartTimeById;    /*!< CPU mapping of the above */
 302
 303         DEVMEM_MEMDESC * psEndTimeMemDesc;      /*!< memdesc for End Timer */
 304         IMG_UINT64     * pui64EndTimeById;      /*!< CPU mapping of the above */
 305
 306         IMG_UINT32     aui32ScheduledOnId[RGX_MAX_TIMER_QUERIES];      /*!< kicks Scheduled on QueryId */
 307         DEVMEM_MEMDESC * psCompletedMemDesc;    /*!< kicks Completed on QueryId */
 308         IMG_UINT32     * pui32CompletedById;    /*!< CPU mapping of the above */
 309
 310
 311         /* GPU DVFS History and GPU Utilization stats */
 312         RGX_GPU_DVFS_HIST*      psGpuDVFSHistory;
 313         RGXFWIF_GPU_UTIL_STATS  (*pfnGetGpuUtilStats) (PVRSRV_DEVICE_NODE *psDeviceNode);
 314
 315         /* Register configuration */
 316         RGX_REG_CONFIG          sRegCongfig;
 317
 318         IMG_BOOL                                bIgnoreFurtherIRQs;
 319         DLLIST_NODE                             sMemoryContextList;
 320
 321         POSWR_LOCK              hRenderCtxListLock;
 322         POSWR_LOCK              hComputeCtxListLock;
 323         POSWR_LOCK              hTransferCtxListLock;
 324         POSWR_LOCK              hRaytraceCtxListLock;
 325         POSWR_LOCK              hMemoryCtxListLock;
 326
 327         /* Linked lists of contexts on this device */
 328         DLLIST_NODE             sRenderCtxtListHead;
 329         DLLIST_NODE             sComputeCtxtListHead;
 330         DLLIST_NODE             sTransferCtxtListHead;
 331         DLLIST_NODE             sRaytraceCtxtListHead;
 332
 333         DLLIST_NODE             sCommonCtxtListHead;
 334         IMG_UINT32                      ui32CommonCtxtCurrentID;                        /*!< ID assigned to the next common context */
 335 } PVRSRV_RGXDEV_INFO;
 336
 337
 338
 339 typedef struct _RGX_TIMING_INFORMATION_
 340 {
 341         /*! GPU default core clock speed in Hz */
 342         IMG_UINT32                      ui32CoreClockSpeed;
 343
 344         /*! Active Power Management: GPU actively requests the host driver to be powered off */
 345         IMG_BOOL                        bEnableActivePM;
 346
 347         /*! Enable the GPU to power off internal Power Islands independently from the host driver */
 348         IMG_BOOL                        bEnableRDPowIsland;
 349
 350         /*! Active Power Management: Delay between the GPU idle and the request to the host */
 351         IMG_UINT32                      ui32ActivePMLatencyms;
 352
 353 } RGX_TIMING_INFORMATION;
 354
 355 typedef struct _RGX_DATA_
 356 {
 357         /*! Timing information */
 358         RGX_TIMING_INFORMATION  *psRGXTimingInfo;
 359         IMG_BOOL bHasTDMetaCodePhysHeap;
 360         IMG_UINT32 uiTDMetaCodePhysHeapID;
 361         IMG_BOOL bHasTDSecureBufPhysHeap;
 362         IMG_UINT32 uiTDSecureBufPhysHeapID;
 363 } RGX_DATA;
 364
 365
 366 /*
 367         RGX PDUMP register bank name (prefix)
 368 */
 369 #define RGX_PDUMPREG_NAME               "RGXREG"
 370
 371 #endif /* __RGXDEVICE_H__ */