drivers/gpu/rogue/services/include/rgx_fwif_km.h

   1 /*************************************************************************/ /*!
   2 @File
   3 @Title          RGX firmware interface structures used by pvrsrvkm
   4 @Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
   5 @Description    RGX firmware interface structures used by pvrsrvkm
   6 @License        Dual MIT/GPLv2
   7
   8 The contents of this file are subject to the MIT license as set out below.
   9
  10 Permission is hereby granted, free of charge, to any person obtaining a copy
  11 of this software and associated documentation files (the "Software"), to deal
  12 in the Software without restriction, including without limitation the rights
  13 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  14 copies of the Software, and to permit persons to whom the Software is
  15 furnished to do so, subject to the following conditions:
  16
  17 The above copyright notice and this permission notice shall be included in
  18 all copies or substantial portions of the Software.
  19
  20 Alternatively, the contents of this file may be used under the terms of
  21 the GNU General Public License Version 2 ("GPL") in which case the provisions
  22 of GPL are applicable instead of those above.
  23
  24 If you wish to allow use of your version of this file only under the terms of
  25 GPL, and not to allow others to use your version of this file under the terms
  26 of the MIT license, indicate your decision by deleting the provisions above
  27 and replace them with the notice and other provisions required by GPL as set
  28 out in the file called "GPL-COPYING" included in this distribution. If you do
  29 not delete the provisions above, a recipient may use your version of this file
  30 under the terms of either the MIT license or GPL.
  31
  32 This License is also included in this distribution in the file called
  33 "MIT-COPYING".
  34
  35 EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
  36 PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
  37 BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  38 PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
  39 COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  40 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  41 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  42 */ /**************************************************************************/
  43
  44 #if !defined (__RGX_FWIF_KM_H__)
  45 #define __RGX_FWIF_KM_H__
  46
  47 #include "img_types.h"
  48 #include "rgx_fwif_shared.h"
  49 #include "rgxdefs_km.h"
  50 #include "pvr_debug.h"
  51 #include "dllist.h"
  52
  53
  54 #if defined(RGX_FIRMWARE)
  55 /* Compiling the actual firmware - use a fully typed pointer */
  56 typedef struct _RGXFWIF_HOST_CTL_                       *PRGXFWIF_HOST_CTL;
  57 typedef struct _RGXFWIF_CCB_CTL_                        *PRGXFWIF_CCB_CTL;
  58 typedef IMG_UINT8                                                       *PRGXFWIF_CCB;
  59 typedef struct _RGXFWIF_FWMEMCONTEXT_           *PRGXFWIF_FWMEMCONTEXT;
  60 typedef struct _RGXFWIF_FWRENDERCONTEXT_        *PRGXFWIF_FWRENDERCONTEXT;
  61 typedef struct _RGXFWIF_FWTQ2DCONTEXT_          *PRGXFWIF_FWTQ2DCONTEXT;
  62 typedef struct _RGXFWIF_FWTQ3DCONTEXT_          *PRGXFWIF_FWTQ3DCONTEXT;
  63 typedef struct _RGXFWIF_FWCOMPUTECONTEXT_       *PRGXFWIF_FWCOMPUTECONTEXT;
  64 typedef struct _RGXFWIF_FWCOMMONCONTEXT_        *PRGXFWIF_FWCOMMONCONTEXT;
  65 typedef struct _RGXFWIF_ZSBUFFER_                       *PRGXFWIF_ZSBUFFER;
  66 typedef IMG_UINT32                                                      *PRGXFWIF_SIGBUFFER;
  67 typedef struct _RGXFWIF_INIT_                           *PRGXFWIF_INIT;
  68 typedef struct _RGXFWIF_RUNTIME_CFG                     *PRGXFWIF_RUNTIME_CFG;
  69 typedef struct _RGXFW_UNITTESTS_                        *PRGXFW_UNITTESTS;
  70 typedef struct _RGXFWIF_TRACEBUF_                       *PRGXFWIF_TRACEBUF;
  71 typedef IMG_UINT8                                                       *PRGXFWIF_HWPERFINFO;
  72 typedef struct _RGXFWIF_HWRINFOBUF_                     *PRGXFWIF_HWRINFOBUF;
  73 typedef struct _RGXFWIF_GPU_UTIL_FWCB_          *PRGXFWIF_GPU_UTIL_FWCB;
  74 typedef struct _RGXFWIF_REG_CFG_                *PRGXFWIF_REG_CFG;
  75 typedef IMG_UINT8                                                       *PRGXFWIF_COMMONCTX_STATE;
  76 typedef struct _RGXFWIF_TACTX_STATE_            *PRGXFWIF_TACTX_STATE;
  77 typedef struct _RGXFWIF_3DCTX_STATE_            *PRGXFWIF_3DCTX_STATE;
  78 typedef struct _RGXFWIF_COMPUTECTX_STATE_       *PRGXFWIF_COMPUTECTX_STATE;
  79 typedef struct _RGXFWIF_VRDMCTX_STATE_          *PRGXFWIF_VRDMCTX_STATE;
  80 typedef IMG_UINT8                                                       *PRGXFWIF_RF_CMD;
  81 typedef struct _RGXFWIF_COMPCHECKS_                     *PRGXFWIF_COMPCHECKS;
  82 typedef struct _RGX_HWPERF_CONFIG_CNTBLK_       *PRGX_HWPERF_CONFIG_CNTBLK;
  83 typedef IMG_UINT32                          *PRGX_HWPERF_SELECT_CUSTOM_CNTRS;
  84 typedef DLLIST_NODE                                                     RGXFWIF_DLLIST_NODE;
  85 #else
  86 /* Compiling the host driver - use a firmware device virtual pointer */
  87 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_HOST_CTL;
  88 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_CCB_CTL;
  89 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_CCB;
  90 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_FWMEMCONTEXT;
  91 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_FWRENDERCONTEXT;
  92 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_FWTQ2DCONTEXT;
  93 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_FWTQ3DCONTEXT;
  94 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_FWCOMPUTECONTEXT;
  95 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_FWCOMMONCONTEXT;
  96 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_ZSBUFFER;
  97 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_SIGBUFFER;
  98 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_INIT;
  99 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_RUNTIME_CFG;
 100 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFW_UNITTESTS;
 101 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_TRACEBUF;
 102 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_HWPERFINFO;
 103 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_HWRINFOBUF;
 104 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_GPU_UTIL_FWCB;
 105 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_REG_CFG;
 106 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_COMMONCTX_STATE;
 107 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_RF_CMD;
 108 typedef RGXFWIF_DEV_VIRTADDR                            PRGXFWIF_COMPCHECKS;
 109 typedef RGXFWIF_DEV_VIRTADDR                            PRGX_HWPERF_CONFIG_CNTBLK;
 110 typedef RGXFWIF_DEV_VIRTADDR                PRGX_HWPERF_SELECT_CUSTOM_CNTRS;
 111 typedef struct {RGXFWIF_DEV_VIRTADDR p;
 112                                   RGXFWIF_DEV_VIRTADDR n;}      RGXFWIF_DLLIST_NODE;
 113 #endif /* RGX_FIRMWARE */
 114
 115 /*!
 116  * This number is used to represent an invalid page catalogue physical address
 117  */
 118 #define RGXFWIF_INVALID_PC_PHYADDR 0xFFFFFFFFFFFFFFFFLLU
 119
 120 /*!
 121         Firmware memory context.
 122 */
 123 typedef struct _RGXFWIF_FWMEMCONTEXT_
 124 {
 125         IMG_DEV_PHYADDR                 RGXFW_ALIGN sPCDevPAddr;        /*!< device physical address of context's page catalogue */
 126         IMG_INT32                               uiPageCatBaseRegID;     /*!< associated page catalog base register (-1 == unallocated) */
 127         IMG_UINT32                              uiBreakpointAddr; /*!< breakpoint address */
 128         IMG_UINT32                              uiBPHandlerAddr;  /*!< breakpoint handler address */
 129         IMG_UINT32                              uiBreakpointCtl; /*!< DM and enable control for BP */
 130 } RGXFWIF_FWMEMCONTEXT;
 131
 132
 133 /*!
 134  *      FW context state flags
 135  */
 136 #define RGXFWIF_CONTEXT_TAFLAGS_NEED_RESUME                     (0x00000001)
 137 #define RGXFWIF_CONTEXT_RENDERFLAGS_NEED_RESUME         (0x00000002)
 138 #define RGXFWIF_CONTEXT_CDMFLAGS_NEED_RESUME            (0x00000004)
 139 #define RGXFWIF_CONTEXT_SHGFLAGS_NEED_RESUME            (0x00000008)
 140 #define RGXFWIF_CONTEXT_ALLFLAGS_NEED_RESUME            (0x0000000F)
 141
 142
 143 typedef struct _RGXFWIF_TACTX_STATE_
 144 {
 145         /* FW-accessible TA state which must be written out to memory on context store */
 146         IMG_UINT64      RGXFW_ALIGN uTAReg_VDM_CALL_STACK_POINTER;               /* To store in mid-TA */
 147         IMG_UINT64      RGXFW_ALIGN uTAReg_VDM_CALL_STACK_POINTER_Init;  /* Initial value (in case is 'lost' due to a lock-up */
 148         IMG_UINT64      RGXFW_ALIGN uTAReg_VDM_BATCH;
 149         IMG_UINT64      RGXFW_ALIGN uTAReg_VBS_SO_PRIM0;
 150         IMG_UINT64      RGXFW_ALIGN uTAReg_VBS_SO_PRIM1;
 151         IMG_UINT64      RGXFW_ALIGN uTAReg_VBS_SO_PRIM2;
 152         IMG_UINT64      RGXFW_ALIGN uTAReg_VBS_SO_PRIM3;
 153
 154         /* Number of stores on this context */
 155         IMG_UINT32  ui32NumStores;
 156 } RGXFWIF_TACTX_STATE;
 157
 158
 159 typedef struct _RGXFWIF_3DCTX_STATE_
 160 {
 161         /* FW-accessible ISP state which must be written out to memory on context store */
 162 #if !defined(RGX_FEATURE_S7_TOP_INFRASTRUCTURE)
 163         IMG_UINT32      RGXFW_ALIGN au3DReg_ISP_STORE[8];
 164 #else
 165         IMG_UINT32      RGXFW_ALIGN au3DReg_ISP_STORE[32];
 166 #endif
 167         IMG_UINT64      RGXFW_ALIGN u3DReg_PM_DEALLOCATED_MASK_STATUS;
 168         IMG_UINT64      RGXFW_ALIGN u3DReg_PM_PDS_MTILEFREE_STATUS;
 169
 170         /* Number of stores on this context */
 171         IMG_UINT32  ui32NumStores;
 172 } RGXFWIF_3DCTX_STATE;
 173
 174
 175
 176 typedef struct _RGXFWIF_COMPUTECTX_STATE_
 177 {
 178         IMG_UINT64      RGXFW_ALIGN     ui64Padding;
 179
 180         /* Number of stores on this context */
 181         IMG_UINT32  ui32NumStores;
 182 } RGXFWIF_COMPUTECTX_STATE;
 183
 184
 185 typedef struct _RGXFWIF_VRDMCTX_STATE_
 186 {
 187         /* FW-accessible TA state which must be written out to memory on context store */
 188         IMG_UINT64      RGXFW_ALIGN uVRDMReg_VRM_CALL_STACK_POINTER;
 189         IMG_UINT64      RGXFW_ALIGN uVRDMReg_VRM_BATCH;
 190
 191         /* Number of stores on this context */
 192         IMG_UINT32  ui32NumStores;
 193 } RGXFWIF_VRDMCTX_STATE;
 194
 195
 196 typedef struct _RGXFWIF_FWCOMMONCONTEXT_
 197 {
 198         /*
 199                 Used by bg and irq context
 200         */
 201         /* CCB details for this firmware context */
 202         PRGXFWIF_CCCB_CTL               psCCBCtl;                               /*!< CCB control */
 203         PRGXFWIF_CCCB                   psCCB;                                  /*!< CCB base */
 204
 205         /*
 206                 Used by the bg context only
 207         */
 208         RGXFWIF_DLLIST_NODE             RGXFW_ALIGN sWaitingNode;                       /*!< List entry for the waiting list */
 209
 210         /*
 211                 Used by the irq context only
 212         */
 213         RGXFWIF_DLLIST_NODE             sRunNode;                               /*!< List entry for the run list */
 214
 215         PRGXFWIF_FWMEMCONTEXT   psFWMemContext;                 /*!< Memory context */
 216
 217         /* Context suspend state */
 218         PRGXFWIF_COMMONCTX_STATE        RGXFW_ALIGN psContextState;             /*!< TA/3D context suspend state, read/written by FW */
 219
 220         /* Framework state
 221          */
 222         PRGXFWIF_RF_CMD         RGXFW_ALIGN psRFCmd;            /*!< Register updates for Framework */
 223
 224         /*
 225          *      Flags e.g. for context switching
 226          */
 227         IMG_UINT32                              ui32Flags;
 228         IMG_UINT32                              ui32Priority;
 229         IMG_UINT64              RGXFW_ALIGN     ui64MCUFenceAddr;
 230
 231         /* Reference back to the Server Common Context */
 232         IMG_UINT32                              ui32ServerCommonContextID;
 233
 234 } RGXFWIF_FWCOMMONCONTEXT;
 235
 236
 237 /*!
 238         Firmware render context.
 239 */
 240 typedef struct _RGXFWIF_FWRENDERCONTEXT_
 241 {
 242         RGXFWIF_FWCOMMONCONTEXT sTAContext;                             /*!< Firmware context for the TA */
 243         RGXFWIF_FWCOMMONCONTEXT s3DContext;                             /*!< Firmware context for the 3D */
 244
 245         /*
 246          * Note: The following fields keep track of OOM and partial render statistics.
 247          * Because these data structures are allocated cache-incoherent,
 248          * and because these fields are updated by the firmware,
 249          * the host will read valid values only after an SLC flush/inval.
 250          * This is only guaranteed to happen while destroying the render-context.
 251          */
 252         IMG_UINT32                      ui32TotalNumPartialRenders; /*!< Total number of partial renders */
 253         IMG_UINT32                      ui32TotalNumOutOfMemory;        /*!< Total number of OOMs */
 254
 255 } RGXFWIF_FWRENDERCONTEXT;
 256
 257 /*!
 258         Firmware render context.
 259 */
 260 typedef struct _RGXFWIF_FWRAYCONTEXT_
 261 {
 262         RGXFWIF_FWCOMMONCONTEXT sSHGContext;                            /*!< Firmware context for the SHG */
 263         RGXFWIF_FWCOMMONCONTEXT sRTUContext;                            /*!< Firmware context for the RTU */
 264         PRGXFWIF_CCCB_CTL               psCCBCtl[DPX_MAX_RAY_CONTEXTS];
 265         PRGXFWIF_CCCB                   psCCB[DPX_MAX_RAY_CONTEXTS];
 266         IMG_UINT32                              ui32NextFC;
 267         IMG_UINT32                              ui32ActiveFCMask;
 268 } RGXFWIF_FWRAYCONTEXT;
 269
 270 #define RGXFWIF_INVALID_FRAME_CONTEXT (0xFFFFFFFF)
 271
 272 /*!
 273     BIF requester selection
 274 */
 275 typedef enum _RGXFWIF_BIFREQ_
 276 {
 277         RGXFWIF_BIFREQ_TA               = 0,
 278         RGXFWIF_BIFREQ_3D               = 1,
 279         RGXFWIF_BIFREQ_CDM              = 2,
 280         RGXFWIF_BIFREQ_2D               = 3,
 281         RGXFWIF_BIFREQ_HOST             = 4,
 282         RGXFWIF_BIFREQ_RTU              = 5,
 283         RGXFWIF_BIFREQ_SHG              = 6,
 284         RGXFWIF_BIFREQ_MAX              = 7
 285 } RGXFWIF_BIFREQ;
 286
 287 typedef enum _RGXFWIF_PM_DM_
 288 {
 289         RGXFWIF_PM_DM_TA        = 0,
 290         RGXFWIF_PM_DM_3D        = 1,
 291 } RGXFWIF_PM_DM;
 292
 293 /*!
 294  ******************************************************************************
 295  * Kernel CCB control for RGX
 296  *****************************************************************************/
 297 typedef struct _RGXFWIF_CCB_CTL_
 298 {
 299         volatile IMG_UINT32             ui32WriteOffset;                /*!< write offset into array of commands (MUST be aligned to 16 bytes!) */
 300         volatile IMG_UINT32             ui32ReadOffset;                 /*!< read offset into array of commands */
 301         IMG_UINT32                              ui32WrapMask;                   /*!< Offset wrapping mask (Total capacity of the CCB - 1) */
 302         IMG_UINT32                              ui32CmdSize;                    /*!< size of each command in bytes */
 303 } RGXFWIF_CCB_CTL;
 304
 305 /*!
 306  ******************************************************************************
 307  * Kernel CCB command structure for RGX
 308  *****************************************************************************/
 309 #if !defined(RGX_FEATURE_SLC_VIVT)
 310
 311 #define RGXFWIF_MMUCACHEDATA_FLAGS_PT      (0x1) /* BIF_CTRL_INVAL_PT_EN */
 312 #define RGXFWIF_MMUCACHEDATA_FLAGS_PD      (0x2) /* BIF_CTRL_INVAL_PD_EN */
 313 #define RGXFWIF_MMUCACHEDATA_FLAGS_PC      (0x4) /* BIF_CTRL_INVAL_PC_EN */
 314 #define RGXFWIF_MMUCACHEDATA_FLAGS_PMTLB   (0x10) /* can't use PM_TLB0 bit from BIFPM_CTRL reg because it collides with PT bit from BIF_CTRL reg */
 315 #define RGXFWIF_MMUCACHEDATA_FLAGS_TLB     (RGXFWIF_MMUCACHEDATA_FLAGS_PMTLB | 0x8) /* BIF_CTRL_INVAL_TLB1_EN */
 316 #define RGXFWIF_MMUCACHEDATA_FLAGS_CTX(C)  (0x0) /* not used */
 317 #define RGXFWIF_MMUCACHEDATA_FLAGS_CTX_ALL (0x0) /* not used */
 318
 319 #define RGXFWIF_PMMMUCACHEDATA_FLAGS_INVAL       (0x0) /* not used */
 320 #define RGXFWIF_PMMMUCACHEDATA_FLAGS_FLUSH       (0x0) /* not used */
 321 #define RGXFWIF_PMMMUCACHEDATA_FLAGS_FLUSHINVAL  (0x0) /* not used */
 322
 323 #else /* RGX_FEATURE_SLC_VIVT */
 324 #define RGXFWIF_MMUCACHEDATA_FLAGS_PT      (0x1) /* MMU_CTRL_INVAL_PT_EN */
 325 #define RGXFWIF_MMUCACHEDATA_FLAGS_PD      (0x2) /* MMU_CTRL_INVAL_PD_EN */
 326 #define RGXFWIF_MMUCACHEDATA_FLAGS_PC      (0x4) /* MMU_CTRL_INVAL_PC_EN */
 327 #define RGXFWIF_MMUCACHEDATA_FLAGS_PMTLB   (0x0) /* not used */
 328 #define RGXFWIF_MMUCACHEDATA_FLAGS_TLB     (0x0) /* not used */
 329 #define RGXFWIF_MMUCACHEDATA_FLAGS_CTX(C)  (C << 0x3) /* MMU_CTRL_INVAL_CONTEXT_SHIFT */
 330 #define RGXFWIF_MMUCACHEDATA_FLAGS_CTX_ALL (0x800) /* MMU_CTRL_INVAL_ALL_CONTEXTS_EN */
 331
 332 #define RGXFWIF_PMMMUCACHEDATA_FLAGS_INVAL       (0x1) /* RGX_CR_SLC3_CFI_INVALIDATE_EN */
 333 #define RGXFWIF_PMMMUCACHEDATA_FLAGS_FLUSH       (0x2) /* RGX_CR_SLC3_CFI_FLUSH_EN */
 334 #define RGXFWIF_PMMMUCACHEDATA_FLAGS_FLUSHINVAL  (0x3) /* RGX_CR_SLC3_CFI_FLUSH_EN|RGX_CR_SLC3_CFI_INVALIDATE_EN */
 335 #endif
 336
 337 typedef struct _RGXFWIF_MMUCACHEDATA_
 338 {
 339         PRGXFWIF_FWMEMCONTEXT           psMemoryContext;
 340         IMG_UINT32                                      ui32Flags;
 341         IMG_UINT32                                      ui32CacheSequenceNum;
 342 } RGXFWIF_MMUCACHEDATA;
 343
 344 typedef struct _RGXFWIF_SLCBPCTLDATA_
 345 {
 346         IMG_BOOL               bSetBypassed;        /*!< Should SLC be/not be bypassed for indicated units? */
 347         IMG_UINT32             uiFlags;             /*!< Units to enable/disable */
 348 } RGXFWIF_SLCBPCTLDATA;
 349
 350 #define RGXFWIF_BPDATA_FLAGS_WRITE      (1 << 0)
 351 #define RGXFWIF_BPDATA_FLAGS_CTL        (1 << 1)
 352 #define RGXFWIF_BPDATA_FLAGS_REGS       (1 << 2)
 353
 354 typedef struct _RGXFWIF_FWBPDATA_
 355 {
 356         PRGXFWIF_FWMEMCONTEXT   psFWMemContext;                 /*!< Memory context */
 357         IMG_UINT32              ui32BPAddr;                     /*!< Breakpoint address */
 358         IMG_UINT32              ui32HandlerAddr;                /*!< Breakpoint handler */
 359         IMG_UINT32              ui32BPDM;                       /*!< Breakpoint control */
 360         IMG_BOOL                bEnable;
 361         IMG_UINT32              ui32Flags;
 362         IMG_UINT32              ui32TempRegs;           /*!< Number of temporary registers to overallocate */
 363         IMG_UINT32              ui32SharedRegs;         /*!< Number of shared registers to overallocate */
 364 } RGXFWIF_BPDATA;
 365
 366 #define RGXFWIF_KCCB_CMD_KICK_DATA_MAX_NUM_CLEANUP_CTLS 4
 367
 368 typedef struct _RGXFWIF_KCCB_CMD_KICK_DATA_
 369 {
 370         PRGXFWIF_FWCOMMONCONTEXT        psContext;                      /*!< address of the firmware context */
 371         IMG_UINT32                                      ui32CWoffUpdate;        /*!< Client CCB woff update */
 372         IMG_UINT32              ui32NumCleanupCtl;              /*!< number of CleanupCtl pointers attached */
 373         PRGXFWIF_CLEANUP_CTL    apsCleanupCtl[RGXFWIF_KCCB_CMD_KICK_DATA_MAX_NUM_CLEANUP_CTLS]; /*!< CleanupCtl structures associated with command */
 374 } RGXFWIF_KCCB_CMD_KICK_DATA;
 375
 376 typedef struct _RGXFWIF_KCCB_CMD_FENCE_DATA_
 377 {
 378         IMG_UINT32 uiSyncObjDevVAddr;
 379         IMG_UINT32 uiUpdateVal;
 380 } RGXFWIF_KCCB_CMD_SYNC_DATA;
 381
 382 typedef enum _RGXFWIF_CLEANUP_TYPE_
 383 {
 384         RGXFWIF_CLEANUP_FWCOMMONCONTEXT,                /*!< FW common context cleanup */
 385         RGXFWIF_CLEANUP_HWRTDATA,                               /*!< FW HW RT data cleanup */
 386         RGXFWIF_CLEANUP_FREELIST,                               /*!< FW freelist cleanup */
 387         RGXFWIF_CLEANUP_ZSBUFFER,                               /*!< FW ZS Buffer cleanup */
 388 } RGXFWIF_CLEANUP_TYPE;
 389
 390 #define RGXFWIF_CLEANUP_RUN             (1 << 0)        /*!< The requested cleanup command has run on the FW */
 391 #define RGXFWIF_CLEANUP_BUSY    (1 << 1)        /*!< The requested resource is busy */
 392
 393 typedef struct _RGXFWIF_CLEANUP_REQUEST_
 394 {
 395         RGXFWIF_CLEANUP_TYPE                    eCleanupType;                   /*!< Cleanup type */
 396         union {
 397                 PRGXFWIF_FWCOMMONCONTEXT        psContext;                              /*!< FW common context to cleanup */
 398                 PRGXFWIF_HWRTDATA                       psHWRTData;                             /*!< HW RT to cleanup */
 399                 PRGXFWIF_FREELIST                       psFreelist;                             /*!< Freelist to cleanup */
 400                 PRGXFWIF_ZSBUFFER                       psZSBuffer;                             /*!< ZS Buffer to cleanup */
 401         } uCleanupData;
 402         IMG_UINT32                                              uiSyncObjDevVAddr;              /*!< sync primitive used to indicate state of the request */
 403 } RGXFWIF_CLEANUP_REQUEST;
 404
 405 typedef enum _RGXFWIF_POWER_TYPE_
 406 {
 407         RGXFWIF_POW_OFF_REQ = 1,
 408         RGXFWIF_POW_FORCED_IDLE_REQ,
 409         RGXFWIF_POW_NUMDUST_CHANGE,
 410         RGXFWIF_POW_APM_LATENCY_CHANGE
 411 } RGXFWIF_POWER_TYPE;
 412
 413 typedef struct _RGXFWIF_POWER_REQUEST_
 414 {
 415         RGXFWIF_POWER_TYPE                              ePowType;                               /*!< Type of power request */
 416         union
 417         {
 418                 IMG_UINT32                                      ui32NumOfDusts;                 /*!< Number of active Dusts */
 419                 IMG_BOOL                                        bForced;                                /*!< If the operation is mandatory */
 420                 IMG_BOOL                                        bCancelForcedIdle;              /*!< If the operation is to cancel previously forced idle */
 421                 IMG_UINT32                                      ui32ActivePMLatencyms;          /* Number of milliseconds to set APM latency */
 422         } uPoweReqData;
 423 } RGXFWIF_POWER_REQUEST;
 424
 425 typedef struct _RGXFWIF_SLCFLUSHINVALDATA_
 426 {
 427     PRGXFWIF_FWCOMMONCONTEXT psContext; /*!< Context to fence on */
 428     IMG_BOOL    bInval;                 /*!< invalidate the cache as well as flushing */
 429     IMG_UINT32  eDM;                    /*!< DM to flush entries for */
 430 } RGXFWIF_SLCFLUSHINVALDATA;
 431
 432 typedef struct _RGXFWIF_HWPERF_CTRL_
 433 {
 434         IMG_BOOL                                bToggle;        /*!< Toggle masked bits or apply full mask? */
 435         IMG_UINT64      RGXFW_ALIGN     ui64Mask;   /*!< Mask of events to toggle */
 436 } RGXFWIF_HWPERF_CTRL;
 437
 438 typedef struct _RGXFWIF_HWPERF_CONFIG_ENABLE_BLKS_
 439 {
 440         IMG_UINT32                              ui32NumBlocks;  /*!< Number of RGX_HWPERF_CONFIG_CNTBLK in the array */
 441         PRGX_HWPERF_CONFIG_CNTBLK pasBlockConfigs;      /*!< Address of the RGX_HWPERF_CONFIG_CNTBLK array */
 442 } RGXFWIF_HWPERF_CONFIG_ENABLE_BLKS;
 443
 444 typedef struct _RGXFWIF_CORECLKSPEEDCHANGE_DATA_
 445 {
 446         IMG_UINT32      ui32NewClockSpeed;                      /*!< New clock speed */
 447 } RGXFWIF_CORECLKSPEEDCHANGE_DATA;
 448
 449 /* This macro value must always be greater than or equal to
 450  * RGX_HWPERF_MAX_BLKS for all valid BVNCs. This is asserted in
 451  * rgxsrvinit.c. This macro is defined with a constant to avoid a KM
 452  * dependency */
 453  #define RGXFWIF_HWPERF_CTRL_BLKS_MAX   32
 454
 455 typedef struct _RGXFWIF_HWPERF_CTRL_BLKS_
 456 {
 457         IMG_BOOL        bEnable;
 458         IMG_UINT32      ui32NumBlocks;                              /*!< Number of block IDs in the array */
 459         IMG_UINT8       aeBlockIDs[RGXFWIF_HWPERF_CTRL_BLKS_MAX];   /*!< Array of RGX_HWPERF_CNTBLK_ID values */
 460 } RGXFWIF_HWPERF_CTRL_BLKS;
 461
 462
 463 typedef struct _RGXFWIF_HWPERF_SELECT_CUSTOM_CNTRS_
 464 {
 465         IMG_UINT16 ui16CustomBlock;
 466         IMG_UINT16 ui16NumCounters;
 467         PRGX_HWPERF_SELECT_CUSTOM_CNTRS pui32CustomCounterIDs;
 468 } RGXFWIF_HWPERF_SELECT_CUSTOM_CNTRS;
 469
 470 typedef struct _RGXFWIF_ZSBUFFER_BACKING_DATA_
 471 {
 472         IMG_UINT32                              psZSBufferFWDevVAddr;                           /*!< ZS-Buffer FW address */
 473         IMG_UINT32                              bDone;                                                          /*!< action backing/unbacking succeeded */
 474 } RGXFWIF_ZSBUFFER_BACKING_DATA;
 475
 476 typedef struct _RGXFWIF_FREELIST_GS_DATA_
 477 {
 478         IMG_UINT32                              psFreeListFWDevVAddr;                           /*!< Freelist FW address */
 479         IMG_UINT32                              ui32DeltaSize;                                          /*!< Amount of the Freelist change */
 480         IMG_UINT32                              ui32NewSize;                                                    /*!< New amount of pages on the freelist */
 481 } RGXFWIF_FREELIST_GS_DATA;
 482
 483 #define RGXFWIF_FREELISTS_RECONSTRUCTION_FAILED_FLAG 0x80000000
 484
 485 typedef struct _RGXFWIF_FREELISTS_RECONSTRUCTION_DATA_
 486 {
 487         IMG_UINT32                      ui32FreelistsCount;
 488         IMG_UINT32                      aui32FreelistIDs[MAX_HW_TA3DCONTEXTS * RGXFW_MAX_FREELISTS];
 489 } RGXFWIF_FREELISTS_RECONSTRUCTION_DATA;
 490
 491 /*!
 492  ******************************************************************************
 493  * Register configuration structures
 494  *****************************************************************************/
 495
 496 #define RGXFWIF_REG_CFG_MAX_SIZE 512
 497
 498 typedef enum _RGXFWIF_REGDATA_CMD_TYPE_
 499 {
 500         RGXFWIF_REGCFG_CMD_ADD                          = 101,
 501         RGXFWIF_REGCFG_CMD_CLEAR                        = 102,
 502         RGXFWIF_REGCFG_CMD_ENABLE                       = 103,
 503         RGXFWIF_REGCFG_CMD_DISABLE                      = 104
 504 } RGXFWIF_REGDATA_CMD_TYPE;
 505
 506 typedef struct _RGXFWIF_REGCONFIG_DATA_
 507 {
 508         RGXFWIF_REGDATA_CMD_TYPE        eCmdType;
 509         RGXFWIF_REG_CFG_REC             sRegConfig;
 510         RGXFWIF_PWR_EVT                 eRegConfigPI;
 511 } RGXFWIF_REGCONFIG_DATA;
 512
 513 typedef struct _RGXFWIF_REG_CFG_
 514 {
 515         IMG_UINT32                      ui32NumRegsSidekick;
 516         IMG_UINT32                      ui32NumRegsRascalDust;
 517         RGXFWIF_REG_CFG_REC     RGXFW_ALIGN     asRegConfigs[RGXFWIF_REG_CFG_MAX_SIZE];
 518 } RGXFWIF_REG_CFG;
 519
 520 typedef enum _RGXFWIF_KCCB_CMD_TYPE_
 521 {
 522         RGXFWIF_KCCB_CMD_KICK                                           = 101,
 523         RGXFWIF_KCCB_CMD_MMUCACHE                                       = 102,
 524         RGXFWIF_KCCB_CMD_BP                                                     = 104,
 525         RGXFWIF_KCCB_CMD_SLCBPCTL                               = 106, /*!< slc bypass control. Requires sSLCBPCtlData. For validation */
 526         RGXFWIF_KCCB_CMD_SYNC                                   = 107, /*!< host sync command. Requires sSyncData. */
 527         RGXFWIF_KCCB_CMD_SLCFLUSHINVAL                          = 108, /*!< slc flush and invalidation request */
 528         RGXFWIF_KCCB_CMD_CLEANUP                                        = 109, /*!< Requests cleanup of a FW resource (type specified in the command data) */
 529         RGXFWIF_KCCB_CMD_POW                                            = 110, /*!< Power request */
 530         RGXFWIF_KCCB_CMD_HWPERF_CTRL_EVENTS                     = 111, /*!< Control the HWPerf event generation behaviour */
 531         RGXFWIF_KCCB_CMD_HWPERF_CONFIG_ENABLE_BLKS      = 112, /*!< Configure, clear and enable multiple HWPerf blocks */
 532         RGXFWIF_KCCB_CMD_HWPERF_CTRL_BLKS                       = 113, /*!< Enable or disable multiple HWPerf blocks (reusing existing configuration) */
 533         RGXFWIF_KCCB_CMD_CORECLKSPEEDCHANGE                     = 114, /*!< CORE clock speed change event */
 534         RGXFWIF_KCCB_CMD_ZSBUFFER_BACKING_UPDATE        = 115, /*!< Backing for on-demand ZS-Buffer done */
 535         RGXFWIF_KCCB_CMD_ZSBUFFER_UNBACKING_UPDATE      = 116, /*!< Unbacking for on-demand ZS-Buffer done */
 536         RGXFWIF_KCCB_CMD_FREELIST_GROW_UPDATE           = 117, /*!< Freelist Grow done */
 537         RGXFWIF_KCCB_CMD_FREELIST_SHRINK_UPDATE         = 118, /*!< Freelist Shrink done */
 538         RGXFWIF_KCCB_CMD_FREELISTS_RECONSTRUCTION_UPDATE        = 119, /*!< Freelists Reconstruction done */
 539         RGXFWIF_KCCB_CMD_HEALTH_CHECK               = 120, /*!< Health check request */
 540         RGXFWIF_KCCB_CMD_REGCONFIG                  = 121,
 541         RGXFWIF_KCCB_CMD_HWPERF_SELECT_CUSTOM_CNTRS = 122, /*!< Configure the custom counters for HWPerf */
 542 } RGXFWIF_KCCB_CMD_TYPE;
 543
 544 /* Kernel CCB command packet */
 545 typedef struct _RGXFWIF_KCCB_CMD_
 546 {
 547         RGXFWIF_KCCB_CMD_TYPE                                   eCmdType;                       /*!< Command type */
 548         union
 549         {
 550                 RGXFWIF_KCCB_CMD_KICK_DATA                      sCmdKickData;                   /*!< Data for Kick command */
 551                 RGXFWIF_MMUCACHEDATA                            sMMUCacheData;                  /*!< Data for MMUCACHE command */
 552                 RGXFWIF_BPDATA                                          sBPData;                                /*!< Data for Breakpoint Commands */
 553                 RGXFWIF_SLCBPCTLDATA                            sSLCBPCtlData;                  /*!< Data for SLC Bypass Control */
 554                 RGXFWIF_KCCB_CMD_SYNC_DATA                      sSyncData;              /*!< Data for host sync commands */
 555                 RGXFWIF_SLCFLUSHINVALDATA                       sSLCFlushInvalData;             /*!< Data for SLC Flush/Inval commands */
 556                 RGXFWIF_CLEANUP_REQUEST                         sCleanupData;                   /*!< Data for cleanup commands */
 557                 RGXFWIF_POWER_REQUEST                           sPowData;                               /*!< Data for power request commands */
 558                 RGXFWIF_HWPERF_CTRL                                     sHWPerfCtrl;                    /*!< Data for HWPerf control command */
 559                 RGXFWIF_HWPERF_CONFIG_ENABLE_BLKS       sHWPerfCfgEnableBlks;   /*!< Data for HWPerf configure, clear and enable performance counter block command */
 560                 RGXFWIF_HWPERF_CTRL_BLKS                        sHWPerfCtrlBlks;                /*!< Data for HWPerf enable or disable performance counter block commands */
 561                 RGXFWIF_HWPERF_SELECT_CUSTOM_CNTRS  sHWPerfSelectCstmCntrs; /*!< Data for HWPerf configure the custom counters to read */
 562                 RGXFWIF_CORECLKSPEEDCHANGE_DATA         sCORECLKSPEEDCHANGEData;/*!< Data for CORE clock speed change */
 563                 RGXFWIF_ZSBUFFER_BACKING_DATA           sZSBufferBackingData;   /*!< Feedback for Z/S Buffer backing/unbacking */
 564                 RGXFWIF_FREELIST_GS_DATA                        sFreeListGSData;                /*!< Feedback for Freelist grow/shrink */
 565                 RGXFWIF_FREELISTS_RECONSTRUCTION_DATA   sFreeListsReconstructionData;   /*!< Feedback for Freelists reconstruction */
 566                 RGXFWIF_REGCONFIG_DATA                          sRegConfigData;                 /*!< Data for custom register configuration */
 567         } uCmdData;
 568 } RGXFWIF_KCCB_CMD;
 569
 570 RGX_FW_STRUCT_SIZE_ASSERT(RGXFWIF_KCCB_CMD);
 571
 572 /*!
 573  ******************************************************************************
 574  * Firmware CCB command structure for RGX
 575  *****************************************************************************/
 576
 577 typedef struct _RGXFWIF_FWCCB_CMD_ZSBUFFER_BACKING_DATA_
 578 {
 579         IMG_UINT32                              ui32ZSBufferID;
 580         IMG_BOOL                                bPopulate;
 581 } RGXFWIF_FWCCB_CMD_ZSBUFFER_BACKING_DATA;
 582
 583 typedef struct _RGXFWIF_FWCCB_CMD_FREELIST_GS_DATA_
 584 {
 585         IMG_UINT32                              ui32FreelistID;
 586 } RGXFWIF_FWCCB_CMD_FREELIST_GS_DATA;
 587
 588 typedef struct _RGXFWIF_FWCCB_CMD_FREELISTS_RECONSTRUCTION_DATA_
 589 {
 590         IMG_UINT32                      ui32FreelistsCount;
 591         IMG_UINT32                      aui32FreelistIDs[MAX_HW_TA3DCONTEXTS * RGXFW_MAX_FREELISTS];
 592 } RGXFWIF_FWCCB_CMD_FREELISTS_RECONSTRUCTION_DATA;
 593
 594 typedef struct _RGXFWIF_FWCCB_CMD_CONTEXT_RESET_DATA_
 595 {
 596         IMG_UINT32                                              ui32ServerCommonContextID;      /*!< Context affected by the reset */
 597         RGXFWIF_CONTEXT_RESET_REASON    eResetReason;                           /*!< Reason for reset */
 598 } RGXFWIF_FWCCB_CMD_CONTEXT_RESET_DATA;
 599
 600
 601 typedef enum _RGXFWIF_FWCCB_CMD_TYPE_
 602 {
 603         RGXFWIF_FWCCB_CMD_ZSBUFFER_BACKING                              = 101,  /*!< Requests ZSBuffer to be backed with physical pages */
 604         RGXFWIF_FWCCB_CMD_ZSBUFFER_UNBACKING                    = 102,  /*!< Requests ZSBuffer to be unbacked */
 605         RGXFWIF_FWCCB_CMD_FREELIST_GROW                                 = 103,  /*!< Requests an on-demand freelist grow/shrink */
 606         RGXFWIF_FWCCB_CMD_FREELISTS_RECONSTRUCTION              = 104,  /*!< Requests freelists reconstruction */
 607         RGXFWIF_FWCCB_CMD_CONTEXT_RESET_NOTIFICATION    = 105,  /*!< Notifies host of a HWR event on a context */
 608         RGXFWIF_FWCCB_CMD_DEBUG_DUMP                                    = 106,  /*!< Requests an on-demand debug dump */
 609         RGXFWIF_FWCCB_CMD_UPDATE_STATS                                  = 107,  /*!< Requests an on-demand update on process stats */
 610 } RGXFWIF_FWCCB_CMD_TYPE;
 611
 612 typedef enum
 613 {
 614     RGXFWIF_INCREASE_TOTAL_NUM_PARTIAL_RENDERS=1,               /*!< PVRSRVStatsUpdateRenderContextStats should increase the value of the ui32TotalNumPartialRenders stat */
 615     RGXFWIF_INCREASE_TOTAL_NUM_OUT_OF_MEMORY,                   /*!< PVRSRVStatsUpdateRenderContextStats should increase the value of the ui32TotalNumOutOfMemory stat */
 616     RGXFWIF_INCREASE_NUM_TA_STORES,                                     /*!< PVRSRVStatsUpdateRenderContextStats should increase the value of the ui32NumTAStores stat */
 617     RGXFWIF_INCREASE_NUM_3D_STORES,                                     /*!< PVRSRVStatsUpdateRenderContextStats should increase the value of the ui32Num3DStores stat */
 618     RGXFWIF_INCREASE_NUM_SH_STORES,                                     /*!< PVRSRVStatsUpdateRenderContextStats should increase the value of the ui32NumSHStores stat */
 619     RGXFWIF_INCREASE_NUM_CDM_STORES                                     /*!< PVRSRVStatsUpdateRenderContextStats should increase the value of the ui32NumCDMStores stat */
 620 } RGXFWIF_FWCCB_CMD_UPDATE_STATS_TYPE;
 621
 622
 623 /* Firmware CCB command packet */
 624
 625 typedef struct
 626 {
 627     IMG_UINT32                                                          ui32ElementToUpdate;            /*!< Element to update */
 628     IMG_PID                                                                     pidOwner;                                       /*!< The pid of the process whose stats are being updated */
 629 } RGXFWIF_FWCCB_CMD_UPDATE_STATS_DATA;
 630
 631 typedef struct _RGXFWIF_FWCCB_CMD_
 632 {
 633         RGXFWIF_FWCCB_CMD_TYPE                                  eCmdType;       /*!< Command type */
 634         union
 635         {
 636                 RGXFWIF_FWCCB_CMD_ZSBUFFER_BACKING_DATA                         sCmdZSBufferBacking;                    /*!< Data for Z/S-Buffer on-demand (un)backing*/
 637                 RGXFWIF_FWCCB_CMD_FREELIST_GS_DATA                                      sCmdFreeListGS;                                 /*!< Data for on-demand freelist grow/shrink */
 638                 RGXFWIF_FWCCB_CMD_FREELISTS_RECONSTRUCTION_DATA         sCmdFreeListsReconstruction;    /*!< Data for freelists reconstruction */
 639                 RGXFWIF_FWCCB_CMD_CONTEXT_RESET_DATA                            sCmdContextResetNotification;   /*!< Data for context reset notification */
 640         RGXFWIF_FWCCB_CMD_UPDATE_STATS_DATA                 sCmdUpdateStatsData;            /*!< Data for updating process stats */
 641                 IMG_UINT32                                                                                      ui32Padding[7];                                 /*!< Force structure to be 8 words */
 642         } uCmdData;
 643 } RGXFWIF_FWCCB_CMD;
 644
 645 BLD_ASSERT(sizeof(RGXFWIF_FWCCB_CMD)==32, rgx_fwif_km_h);
 646
 647 /*!
 648  ******************************************************************************
 649  * Signature and Checksums Buffer
 650  *****************************************************************************/
 651 typedef struct _RGXFWIF_SIGBUF_CTL_
 652 {
 653         PRGXFWIF_SIGBUFFER              psBuffer;                       /*!< Ptr to Signature Buffer memory */
 654         IMG_UINT32                              ui32LeftSizeInRegs;     /*!< Amount of space left for storing regs in the buffer */
 655 } RGXFWIF_SIGBUF_CTL;
 656
 657 /*!
 658  ******************************************************************************
 659  * Updated configuration post FW data init.
 660  *****************************************************************************/
 661 typedef struct _RGXFWIF_RUNTIME_CFG_
 662 {
 663         IMG_UINT32                              ui32ActivePMLatencyms;          /* APM latency in ms before signalling IDLE to the host */
 664         IMG_BOOL                                bActivePMLatencyPersistant;     /* If set, APM latency does not reset to system default each GPU power transition */
 665         IMG_UINT32                              ui32CoreClockSpeed;             /* Core clock speed, currently only used to calculate timer ticks */
 666 } RGXFWIF_RUNTIME_CFG;
 667
 668 /*!
 669  *****************************************************************************
 670  * Control data for RGX
 671  *****************************************************************************/
 672
 673 typedef struct _RGXFWIF_INIT_
 674 {
 675         IMG_DEV_PHYADDR                 RGXFW_ALIGN sFaultPhysAddr;
 676
 677         IMG_DEV_VIRTADDR                RGXFW_ALIGN sPDSExecBase;
 678         IMG_DEV_VIRTADDR                RGXFW_ALIGN sUSCExecBase;
 679         IMG_DEV_VIRTADDR                RGXFW_ALIGN sResultDumpBase;
 680         IMG_DEV_VIRTADDR                RGXFW_ALIGN sDPXControlStreamBase;
 681         IMG_DEV_VIRTADDR                RGXFW_ALIGN sRTUHeapBase;
 682
 683         IMG_BOOL                                bFirstTA;
 684         IMG_BOOL                                bFirstRender;
 685         IMG_BOOL                                bFrameworkAfterInit;
 686         IMG_BOOL                                bEnableHWPerf;
 687         IMG_BOOL                bDisableFilterHWPerfCustomCounter;
 688         IMG_UINT32                              uiPowerSync;
 689         IMG_UINT32                              ui32FilterFlags;
 690
 691         /* Kernel CCBs */
 692         PRGXFWIF_CCB_CTL                psKernelCCBCtl[RGXFWIF_DM_MAX];
 693         PRGXFWIF_CCB                    psKernelCCB[RGXFWIF_DM_MAX];
 694
 695         /* Firmware CCBs */
 696         PRGXFWIF_CCB_CTL                psFirmwareCCBCtl[RGXFWIF_DM_MAX];
 697         PRGXFWIF_CCB                    psFirmwareCCB[RGXFWIF_DM_MAX];
 698
 699         RGXFWIF_DM                              eDM[RGXFWIF_DM_MAX];
 700
 701         RGXFWIF_SIGBUF_CTL              asSigBufCtl[RGXFWIF_DM_MAX];
 702
 703         IMG_BOOL                                bEnableLogging;
 704         IMG_UINT32                              ui32ConfigFlags;        /*!< Configuration flags from host */
 705         IMG_UINT32                              ui32BreakpointTemps;
 706         IMG_UINT32                              ui32BreakpointShareds;
 707         struct
 708         {
 709                 IMG_UINT64 uiBase;
 710                 IMG_UINT64 uiLen;
 711                 IMG_UINT64 uiXStride;
 712         }                       RGXFW_ALIGN sBifTilingCfg[RGXFWIF_NUM_BIF_TILING_CONFIGS];
 713
 714         PRGXFWIF_RUNTIME_CFG            psRuntimeCfg;
 715
 716         PRGXFWIF_TRACEBUF               psTraceBufCtl;
 717         PRGXFWIF_HWPERFINFO             psHWPerfInfoCtl;
 718         IMG_UINT64      RGXFW_ALIGN ui64HWPerfFilter;
 719
 720         PRGXFWIF_HWRINFOBUF             psRGXFWIfHWRInfoBufCtl;
 721         PRGXFWIF_GPU_UTIL_FWCB  psGpuUtilFWCbCtl;
 722         PRGXFWIF_REG_CFG        psRegCfg;
 723
 724
 725 #if defined(RGXFW_ALIGNCHECKS)
 726 #if defined(RGX_FIRMWARE)
 727         IMG_UINT32*                             paui32AlignChecks;
 728 #else
 729         RGXFWIF_DEV_VIRTADDR    paui32AlignChecks;
 730 #endif
 731 #endif
 732
 733         /* Core clock speed at FW boot time */
 734         IMG_UINT32              ui32InitialCoreClockSpeed;
 735
 736         /* APM latency in ms before signalling IDLE to the host */
 737         IMG_UINT32                              ui32ActivePMLatencyms;
 738
 739         /* Flag to be set by the Firmware after successful start */
 740         IMG_BOOL                                bFirmwareStarted;
 741
 742         IMG_UINT32                              ui32FirmwareStartedTimeStamp;
 743
 744         /* Compatibility checks to be populated by the Firmware */
 745         RGXFWIF_COMPCHECKS              sRGXCompChecks;
 746
 747         RGXFWIF_DMA_ADDR                sCorememDataStore;
 748
 749 #if defined(RGX_FEATURE_SLC_VIVT)
 750         IMG_DEV_VIRTADDR                RGXFW_ALIGN sSLC3FenceDevVAddr;
 751 #endif
 752
 753 } RGXFWIF_INIT;
 754
 755
 756 /*!
 757  ******************************************************************************
 758  * Client CCB commands which are only required by the kernel
 759  *****************************************************************************/
 760 typedef struct _RGXFWIF_CMD_PRIORITY_
 761 {
 762         IMG_UINT32                              ui32Priority;
 763 } RGXFWIF_CMD_PRIORITY;
 764
 765 /*!
 766  ******************************************************************************
 767  * RGXFW Unittests declarations
 768  *****************************************************************************/
 769 typedef struct _RGXFW_UNITTEST2_
 770 {
 771         /* Irq events */
 772         IMG_UINT32      ui32IrqKicksDM[RGXFWIF_DM_MAX_MTS];
 773         IMG_UINT32      ui32IrqKicksBg;
 774         IMG_UINT32      ui32IrqKicksTimer;
 775
 776         /* Bg events */
 777         IMG_UINT32      ui32BgKicksDM[RGXFWIF_DM_MAX_MTS];
 778         IMG_UINT32      ui32BgKicksCounted;
 779
 780 } RGXFW_UNITTEST2;
 781
 782 /*!
 783  ******************************************************************************
 784  * RGXFW_UNITTESTS declaration
 785  *****************************************************************************/
 786 #define RGXFW_UNITTEST_FWPING           (0x1)
 787 #define RGXFW_UNITTEST_FWPONG           (0x2)
 788
 789 #define RGXFW_UNITTEST_IS_BGKICK(DM)    ((DM) & 0x1)
 790
 791 typedef struct _RGXFW_UNITTESTS_
 792 {
 793         IMG_UINT32      ui32Status;
 794
 795         RGXFW_UNITTEST2 sUnitTest2;
 796
 797 } RGXFW_UNITTESTS;
 798
 799 #endif /*  __RGX_FWIF_KM_H__ */
 800
 801 /******************************************************************************
 802  End of file (rgx_fwif_km.h)
 803 ******************************************************************************/
 804
 805