drivers/gpu/rogue/services/include/rgx_fwif.h

   1 /*************************************************************************/ /*!
   2 @File                   rgx_fwif.h
   3 @Title          RGX firmware interface structures
   4 @Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
   5 @Description    RGX firmware interface structures used by srvinit and server
   6 @License        Dual MIT/GPLv2
   7
   8 The contents of this file are subject to the MIT license as set out below.
   9
  10 Permission is hereby granted, free of charge, to any person obtaining a copy
  11 of this software and associated documentation files (the "Software"), to deal
  12 in the Software without restriction, including without limitation the rights
  13 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  14 copies of the Software, and to permit persons to whom the Software is
  15 furnished to do so, subject to the following conditions:
  16
  17 The above copyright notice and this permission notice shall be included in
  18 all copies or substantial portions of the Software.
  19
  20 Alternatively, the contents of this file may be used under the terms of
  21 the GNU General Public License Version 2 ("GPL") in which case the provisions
  22 of GPL are applicable instead of those above.
  23
  24 If you wish to allow use of your version of this file only under the terms of
  25 GPL, and not to allow others to use your version of this file under the terms
  26 of the MIT license, indicate your decision by deleting the provisions above
  27 and replace them with the notice and other provisions required by GPL as set
  28 out in the file called "GPL-COPYING" included in this distribution. If you do
  29 not delete the provisions above, a recipient may use your version of this file
  30 under the terms of either the MIT license or GPL.
  31
  32 This License is also included in this distribution in the file called
  33 "MIT-COPYING".
  34
  35 EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
  36 PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
  37 BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  38 PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
  39 COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  40 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  41 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  42 */ /**************************************************************************/
  43
  44 #if !defined (__RGX_FWIF_H__)
  45 #define __RGX_FWIF_H__
  46
  47 #include "rgx_meta.h"
  48 #include "rgx_fwif_shared.h"
  49
  50 #include "pvr_tlcommon.h"
  51
  52 /*************************************************************************/ /*!
  53  Logging type
  54 */ /**************************************************************************/
  55 #define RGXFWIF_LOG_TYPE_NONE                   0x00000000
  56 #define RGXFWIF_LOG_TYPE_TRACE                  0x00000001
  57 #define RGXFWIF_LOG_TYPE_GROUP_MAIN             0x00000002
  58 #define RGXFWIF_LOG_TYPE_GROUP_MTS              0x00000004
  59 #define RGXFWIF_LOG_TYPE_GROUP_CLEANUP  0x00000008
  60 #define RGXFWIF_LOG_TYPE_GROUP_CSW              0x00000010
  61 #define RGXFWIF_LOG_TYPE_GROUP_BIF              0x00000020
  62 #define RGXFWIF_LOG_TYPE_GROUP_PM               0x00000040
  63 #define RGXFWIF_LOG_TYPE_GROUP_RTD              0x00000080
  64 #define RGXFWIF_LOG_TYPE_GROUP_SPM              0x00000100
  65 #define RGXFWIF_LOG_TYPE_GROUP_POW              0x00000200
  66 #define RGXFWIF_LOG_TYPE_GROUP_HWR              0x00000400
  67 #define RGXFWIF_LOG_TYPE_GROUP_HWP              0x00000800
  68 #define RGXFWIF_LOG_TYPE_GROUP_DEBUG    0x80000000
  69 #define RGXFWIF_LOG_TYPE_GROUP_MASK             0x80000FFE
  70 #define RGXFWIF_LOG_TYPE_MASK                   0x80000FFF
  71
  72 /* String used in pvrdebug -h output */
  73 #define RGXFWIF_LOG_GROUPS_STRING_LIST   "main,mts,cleanup,csw,bif,pm,rtd,spm,pow,hwr,hwp"
  74
  75 /* Table entry to map log group strings to log type value */
  76 typedef struct {
  77         const IMG_CHAR* pszLogGroupName;
  78         IMG_UINT32      ui32LogGroupType;
  79 } RGXFWIF_LOG_GROUP_MAP_ENTRY;
  80
  81 /*
  82   Macro for use with the RGXFWIF_LOG_GROUP_MAP_ENTRY type to create a lookup
  83   table where needed. Keep log group names short, no more than 20 chars.
  84 */
  85 #define RGXFWIF_LOG_GROUP_NAME_VALUE_MAP { "main",    RGXFWIF_LOG_TYPE_GROUP_MAIN }, \
  86                                          { "mts",     RGXFWIF_LOG_TYPE_GROUP_MTS }, \
  87                                          { "cleanup", RGXFWIF_LOG_TYPE_GROUP_CLEANUP }, \
  88                                          { "csw",     RGXFWIF_LOG_TYPE_GROUP_CSW }, \
  89                                          { "bif",     RGXFWIF_LOG_TYPE_GROUP_BIF }, \
  90                                          { "pm",      RGXFWIF_LOG_TYPE_GROUP_PM }, \
  91                                          { "rtd",     RGXFWIF_LOG_TYPE_GROUP_RTD }, \
  92                                          { "spm",     RGXFWIF_LOG_TYPE_GROUP_SPM }, \
  93                                          { "pow",     RGXFWIF_LOG_TYPE_GROUP_POW }, \
  94                                          { "hwr",     RGXFWIF_LOG_TYPE_GROUP_HWR }, \
  95                                          { "hwp",     RGXFWIF_LOG_TYPE_GROUP_HWP }, \
  96                                          { "debug",   RGXFWIF_LOG_TYPE_GROUP_DEBUG }
  97
  98
  99 /* Used in print statements to display log group state, one %s per group defined */
 100 #define RGXFWIF_LOG_ENABLED_GROUPS_LIST_PFSPEC  "%s%s%s%s%s%s%s%s%s%s%s%s"
 101
 102 /* Used in a print statement to display log group state, one per group */
 103 #define RGXFWIF_LOG_ENABLED_GROUPS_LIST(types)  (((types) & RGXFWIF_LOG_TYPE_GROUP_MAIN)        ?("main ")              :("")),         \
 104                                                 (((types) & RGXFWIF_LOG_TYPE_GROUP_MTS)         ?("mts ")               :("")),         \
 105                                                 (((types) & RGXFWIF_LOG_TYPE_GROUP_CLEANUP)     ?("cleanup ")   :("")),         \
 106                                                 (((types) & RGXFWIF_LOG_TYPE_GROUP_CSW)         ?("csw ")               :("")),         \
 107                                                 (((types) & RGXFWIF_LOG_TYPE_GROUP_BIF)         ?("bif ")               :("")),         \
 108                                                 (((types) & RGXFWIF_LOG_TYPE_GROUP_PM)          ?("pm ")                :("")),         \
 109                                                 (((types) & RGXFWIF_LOG_TYPE_GROUP_RTD)         ?("rtd ")               :("")),         \
 110                                                 (((types) & RGXFWIF_LOG_TYPE_GROUP_SPM)         ?("spm ")               :("")),         \
 111                                                 (((types) & RGXFWIF_LOG_TYPE_GROUP_POW)         ?("pow ")               :("")),         \
 112                                                 (((types) & RGXFWIF_LOG_TYPE_GROUP_HWR)         ?("hwr ")               :("")),         \
 113                                                 (((types) & RGXFWIF_LOG_TYPE_GROUP_HWP)         ?("hwp ")               :("")),         \
 114                                                 (((types) & RGXFWIF_LOG_TYPE_GROUP_DEBUG)       ?("debug ")             :(""))
 115
 116
 117 /*! Logging function */
 118 typedef IMG_VOID (*PFN_RGXFW_LOG) (const IMG_CHAR* pszFmt, ...);
 119
 120 /*!
 121  ******************************************************************************
 122  * HWPERF
 123  *****************************************************************************/
 124 /* Size of the Firmware L1 HWPERF buffer in bytes (256KB). Accessed by the
 125  * Firmware and host driver. */
 126 #define RGXFW_HWPERF_L1_SIZE_MIN                (0x004000)
 127 #define RGXFW_HWPERF_L1_SIZE_DEFAULT    (0x040000)
 128 #define RGXFW_HWPERF_L1_SIZE_MAX        (0xC00000)
 129 /* This padding value must always be greater than or equal to
 130  * RGX_HWPERF_V2_MAX_PACKET_SIZE for all valid BVNCs. This is asserted in
 131  * rgxsrvinit.c. This macro is defined with a constant to avoid a KM
 132  * dependency */
 133 #define RGXFW_HWPERF_L1_PADDING_DEFAULT (0x800)
 134
 135 /*!
 136  ******************************************************************************
 137  * Trace Buffer
 138  *****************************************************************************/
 139
 140 /*! Number of elements on each line when dumping the trace buffer */
 141 #define RGXFW_TRACE_BUFFER_LINESIZE     (30)
 142
 143 /*! Total size of RGXFWIF_TRACEBUF dword (needs to be a multiple of RGXFW_TRACE_BUFFER_LINESIZE) */
 144 #define RGXFW_TRACE_BUFFER_SIZE         (400*RGXFW_TRACE_BUFFER_LINESIZE)
 145 #define RGXFW_TRACE_BUFFER_ASSERT_SIZE 200
 146 #define RGXFW_THREAD_NUM 1
 147
 148 #define RGXFW_POLL_TYPE_SET 0x80000000
 149
 150 typedef struct _RGXFWIF_ASSERTBUF_
 151 {
 152         IMG_CHAR        szPath[RGXFW_TRACE_BUFFER_ASSERT_SIZE];
 153         IMG_CHAR        szInfo[RGXFW_TRACE_BUFFER_ASSERT_SIZE];
 154         IMG_UINT32      ui32LineNum;
 155 }RGXFWIF_ASSERTBUF;
 156
 157 typedef struct _RGXFWIF_TRACEBUF_SPACE_
 158 {
 159         IMG_UINT32                      ui32TracePointer;
 160         IMG_UINT32                      aui32TraceBuffer[RGXFW_TRACE_BUFFER_SIZE];
 161         RGXFWIF_ASSERTBUF       sAssertBuf;
 162 } RGXFWIF_TRACEBUF_SPACE;
 163
 164 #define RGXFWIF_POW_STATES \
 165   X(RGXFWIF_POW_OFF)                    /* idle and handshaked with the host (ready to full power down) */ \
 166   X(RGXFWIF_POW_ON)                             /* running HW mds */ \
 167   X(RGXFWIF_POW_FORCED_IDLE)    /* forced idle */ \
 168   X(RGXFWIF_POW_IDLE)                   /* idle waiting for host handshake */
 169
 170 typedef enum _RGXFWIF_POW_STATE_
 171 {
 172 #define X(NAME) NAME,
 173         RGXFWIF_POW_STATES
 174 #undef X
 175 } RGXFWIF_POW_STATE;
 176
 177 /* Firmware HWR states */
 178 #define RGXFWIF_HWR_HARDWARE_OK         (0x1 << 0)      /*!< Tells if the HW state is ok or locked up */
 179 #define RGXFWIF_HWR_FREELIST_OK         (0x1 << 1)      /*!< Tells if the freelists are ok or being reconstructed */
 180 #define RGXFWIF_HWR_ANALYSIS_DONE       (0x1 << 2)      /*!< Tells if the analysis of a GPU lockup has already been performed */
 181 #define RGXFWIF_HWR_GENERAL_LOCKUP      (0x1 << 3)      /*!< Tells if a DM unrelated lockup has been detected */
 182 typedef IMG_UINT32 RGXFWIF_HWR_STATEFLAGS;
 183
 184 /* Firmware per-DM HWR states */
 185 #define RGXFWIF_DM_STATE_WORKING                                        (0x00)          /*!< DM is working if all flags are cleared */
 186 #define RGXFWIF_DM_STATE_READY_FOR_HWR                          (0x1 << 0)      /*!< DM is idle and ready for HWR */
 187 #define RGXFWIF_DM_STATE_NEEDS_FL_RECONSTRUCTION        (0x1 << 1)      /*!< DM need FL reconstruction before resuming processing */
 188 #define RGXFWIF_DM_STATE_NEEDS_SKIP                                     (0x1 << 2)      /*!< DM need to skip to next cmd before resuming processing */
 189 #define RGXFWIF_DM_STATE_NEEDS_PR_CLEANUP                       (0x1 << 3)      /*!< DM need partial render cleanup before resuming processing */
 190 #define RGXFWIF_DM_STATE_NEEDS_TRACE_CLEAR                      (0x1 << 4)      /*!< DM need to increment Recovery Count once fully recovered */
 191 #define RGXFWIF_DM_STATE_GUILTY_LOCKUP                          (0x1 << 5)      /*!< DM was identified as locking up and causing HWR */
 192 #define RGXFWIF_DM_STATE_INNOCENT_LOCKUP                        (0x1 << 6)      /*!< DM was innocently affected by another lockup which caused HWR */
 193 #define RGXFWIF_DM_STATE_GUILTY_OVERRUNING                      (0x1 << 7)      /*!< DM was identified as over-running and causing HWR */
 194 #define RGXFWIF_DM_STATE_INNOCENT_OVERRUNING            (0x1 << 8)      /*!< DM was innocently affected by another DM over-running which caused HWR */
 195 typedef IMG_UINT32 RGXFWIF_HWR_RECOVERYFLAGS;
 196
 197 typedef struct _RGXFWIF_TRACEBUF_
 198 {
 199     IMG_UINT32                          ui32LogType;
 200         RGXFWIF_POW_STATE               ePowState;
 201         RGXFWIF_TRACEBUF_SPACE  sTraceBuf[RGXFW_THREAD_NUM];
 202
 203         IMG_UINT16                              aui16HwrDmLockedUpCount[RGXFWIF_DM_MAX];
 204         IMG_UINT16                              aui16HwrDmOverranCount[RGXFWIF_DM_MAX];
 205         IMG_UINT16                              aui16HwrDmRecoveredCount[RGXFWIF_DM_MAX];
 206         IMG_UINT16                              aui16HwrDmFalseDetectCount[RGXFWIF_DM_MAX];
 207         IMG_UINT32                              ui32HwrCounter;
 208         RGXFWIF_DEV_VIRTADDR    apsHwrDmFWCommonContext[RGXFWIF_DM_MAX];
 209
 210         IMG_UINT32                              aui32CrPollAddr[RGXFW_THREAD_NUM];
 211         IMG_UINT32                              aui32CrPollMask[RGXFW_THREAD_NUM];
 212
 213         RGXFWIF_HWR_STATEFLAGS          ui32HWRStateFlags;
 214         RGXFWIF_HWR_RECOVERYFLAGS       aui32HWRRecoveryFlags[RGXFWIF_HWDM_MAX];
 215
 216         volatile IMG_UINT32             ui32HWPerfRIdx;
 217         volatile IMG_UINT32             ui32HWPerfWIdx;
 218         volatile IMG_UINT32             ui32HWPerfWrapCount;
 219         IMG_UINT32                              ui32HWPerfSize;      /* Constant after setup, needed in FW */
 220         IMG_UINT32                              ui32HWPerfDropCount; /* The number of times the FW drops a packet due to buffer full */
 221
 222         /* These next three items are only valid at runtime when the FW is built
 223          * with RGX_HWPERF_UTILIZATION defined in rgxfw_hwperf.c */
 224         IMG_UINT32                              ui32HWPerfUt;        /* Buffer utilisation, high watermark of bytes in use */
 225         IMG_UINT32                              ui32FirstDropOrdinal;/* The ordinal of the first packet the FW dropped */
 226         IMG_UINT32              ui32LastDropOrdinal; /* The ordinal of the last packet the FW dropped */
 227
 228         IMG_UINT32                              ui32InterruptCount;
 229         IMG_UINT32                              ui32KCCBCmdsExecuted;
 230     IMG_UINT64 RGXFW_ALIGN      ui64StartIdleTime;
 231 } RGXFWIF_TRACEBUF;
 232
 233 /*!
 234  ******************************************************************************
 235  * GPU Utilization FW CB
 236  *****************************************************************************/
 237 #define RGXFWIF_GPU_STATS_WINDOW_SIZE_US                        500000                  /*!< Time window considered for active/idle/blocked statistics */
 238 #define RGXFWIF_GPU_STATS_STATE_CHG_PER_SEC                     1000                    /*!< Expected number of maximum GPU state changes per second */
 239 #define RGXFWIF_GPU_STATS_MAX_VALUE_OF_STATE            10000
 240
 241 #define RGXFWIF_GPU_UTIL_FWCB_SIZE      ((RGXFWIF_GPU_STATS_WINDOW_SIZE_US * RGXFWIF_GPU_STATS_STATE_CHG_PER_SEC) / 1000000)
 242
 243 #define RGXFWIF_GPU_UTIL_FWCB_TYPE_CRTIME               IMG_UINT64_C(0x0)
 244 #define RGXFWIF_GPU_UTIL_FWCB_TYPE_POWER_ON             IMG_UINT64_C(0x1)
 245 #define RGXFWIF_GPU_UTIL_FWCB_TYPE_POWER_OFF    IMG_UINT64_C(0x2)
 246 #define RGXFWIF_GPU_UTIL_FWCB_TYPE_END_CRTIME   IMG_UINT64_C(0x3)
 247 #define RGXFWIF_GPU_UTIL_FWCB_TYPE_MASK                 IMG_UINT64_C(0xC000000000000000)
 248 #define RGXFWIF_GPU_UTIL_FWCB_TYPE_SHIFT                (62)
 249
 250 #define RGXFWIF_GPU_UTIL_FWCB_STATE_ACTIVE_LOW  IMG_UINT64_C(0x0)
 251 #define RGXFWIF_GPU_UTIL_FWCB_STATE_IDLE                IMG_UINT64_C(0x1)
 252 #define RGXFWIF_GPU_UTIL_FWCB_STATE_ACTIVE_HIGH IMG_UINT64_C(0x2)
 253 #define RGXFWIF_GPU_UTIL_FWCB_STATE_BLOCKED             IMG_UINT64_C(0x3)
 254 #define RGXFWIF_GPU_UTIL_FWCB_STATE_MASK                IMG_UINT64_C(0x3000000000000000)
 255 #define RGXFWIF_GPU_UTIL_FWCB_STATE_SHIFT               (60)
 256
 257 #define RGXFWIF_GPU_UTIL_FWCB_ID_MASK                   IMG_UINT64_C(0x0FFF000000000000)
 258 #define RGXFWIF_GPU_UTIL_FWCB_ID_SHIFT                  (48)
 259
 260 #define RGXFWIF_GPU_UTIL_FWCB_CR_TIMER_MASK             IMG_UINT64_C(0x0000FFFFFFFFFFFF)
 261 #define RGXFWIF_GPU_UTIL_FWCB_OS_TIMER_MASK             IMG_UINT64_C(0x0FFFFFFFFFFFFFFF)
 262 #define RGXFWIF_GPU_UTIL_FWCB_TIMER_SHIFT               (0)
 263
 264 #define RGXFWIF_GPU_UTIL_FWCB_ENTRY_TYPE(entry)         (((entry)&RGXFWIF_GPU_UTIL_FWCB_TYPE_MASK)>>RGXFWIF_GPU_UTIL_FWCB_TYPE_SHIFT)
 265 #define RGXFWIF_GPU_UTIL_FWCB_ENTRY_STATE(entry)        (((entry)&RGXFWIF_GPU_UTIL_FWCB_STATE_MASK)>>RGXFWIF_GPU_UTIL_FWCB_STATE_SHIFT)
 266 #define RGXFWIF_GPU_UTIL_FWCB_ENTRY_ID(entry)           (((entry)&RGXFWIF_GPU_UTIL_FWCB_ID_MASK)>>RGXFWIF_GPU_UTIL_FWCB_ID_SHIFT)
 267 #define RGXFWIF_GPU_UTIL_FWCB_ENTRY_CR_TIMER(entry)     (((entry)&RGXFWIF_GPU_UTIL_FWCB_CR_TIMER_MASK)>>RGXFWIF_GPU_UTIL_FWCB_TIMER_SHIFT)
 268 #define RGXFWIF_GPU_UTIL_FWCB_ENTRY_OS_TIMER(entry)     (((entry)&RGXFWIF_GPU_UTIL_FWCB_OS_TIMER_MASK)>>RGXFWIF_GPU_UTIL_FWCB_TIMER_SHIFT)
 269
 270 /* It can never happen that the GPU is reported as powered off and active at the same time,
 271  * use this combination to mark the entry as reserved */
 272 #define RGXFWIF_GPU_UTIL_FWCB_RESERVED  \
 273         ( (RGXFWIF_GPU_UTIL_FWCB_TYPE_POWER_OFF <<  RGXFWIF_GPU_UTIL_FWCB_TYPE_SHIFT) | \
 274           (RGXFWIF_GPU_UTIL_FWCB_STATE_ACTIVE_LOW << RGXFWIF_GPU_UTIL_FWCB_STATE_SHIFT) )
 275
 276 #define RGXFWIF_GPU_UTIL_FWCB_ENTRY_ADD(cb, crtimer, state) do {                                                                                                                \
 277                 /* Combine all the information about current state transition into a single 64-bit word */                                              \
 278                 (cb)->aui64CB[(cb)->ui32WriteOffset] =                                                                                          \
 279                         (((IMG_UINT64)(crtimer) << RGXFWIF_GPU_UTIL_FWCB_TIMER_SHIFT) & RGXFWIF_GPU_UTIL_FWCB_CR_TIMER_MASK) |          \
 280                         (((IMG_UINT64)(state) << RGXFWIF_GPU_UTIL_FWCB_STATE_SHIFT) & RGXFWIF_GPU_UTIL_FWCB_STATE_MASK) |                       \
 281                         (((IMG_UINT64)(cb)->ui32CurrentDVFSId << RGXFWIF_GPU_UTIL_FWCB_ID_SHIFT) & RGXFWIF_GPU_UTIL_FWCB_ID_MASK);      \
 282                 /* Make sure the value is written to the memory before advancing write offset */                                                                \
 283                 RGXFW_MEM_FENCE();                                                                                                                                                                                              \
 284                 /* Advance the CB write offset */                                                                                                                                                               \
 285                 (cb)->ui32WriteOffset++;                                                                                                                                                                                \
 286                 if((cb)->ui32WriteOffset >= RGXFWIF_GPU_UTIL_FWCB_SIZE)                                                                                                                 \
 287                 {                                                                                                                                                                                                                               \
 288                         (cb)->ui32WriteOffset = 0;                                                                                                                                                                      \
 289                 }                                                                                                                                                                                                                               \
 290                 /* Cache current transition in cached memory */                                                                                                                                 \
 291                 (cb)->ui32LastGpuUtilState = (state);                                                                                                                                                   \
 292         } while (0)
 293
 294
 295 /* The timer correlation array must be big enough to ensure old entries won't be
 296  * overwritten before all the HWPerf events linked to those entries are processed
 297  * by the MISR. The update frequency of this array depends on how fast the system
 298  * can change state (basically how small the APM latency is) and perform DVFS transitions.
 299  *
 300  * The minimum size is 2 (not 1) to avoid race conditions between the FW reading
 301  * an entry while the Host is updating it. With 2 entries in the worst case the FW
 302  * will read old data, which is still quite ok if the Host is updating the timer
 303  * correlation at that time.
 304  */
 305 #define RGXFWIF_TIME_CORR_ARRAY_SIZE    256
 306
 307 typedef IMG_UINT64 RGXFWIF_GPU_UTIL_FWCB_ENTRY;
 308
 309 typedef struct _RGXFWIF_GPU_UTIL_FWCB_
 310 {
 311         RGXFWIF_TIME_CORR       sTimeCorr[RGXFWIF_TIME_CORR_ARRAY_SIZE];
 312         IMG_UINT32                      ui32TimeCorrCurrent;
 313         IMG_UINT32                      ui32WriteOffset;
 314         IMG_UINT32                      ui32LastGpuUtilState;
 315         IMG_UINT32                      ui32CurrentDVFSId;
 316         RGXFWIF_GPU_UTIL_FWCB_ENTRY     RGXFW_ALIGN aui64CB[RGXFWIF_GPU_UTIL_FWCB_SIZE];
 317 } RGXFWIF_GPU_UTIL_FWCB;
 318
 319 /* HWR Data */
 320 typedef enum _RGX_HWRTYPE_
 321 {
 322         RGX_HWRTYPE_UNKNOWNFAILURE      = 0,
 323         RGX_HWRTYPE_OVERRUN             = 1,
 324         RGX_HWRTYPE_POLLFAILURE         = 2,
 325 #if !defined(RGX_FEATURE_S7_TOP_INFRASTRUCTURE)
 326         RGX_HWRTYPE_BIF0FAULT           = 3,
 327         RGX_HWRTYPE_BIF1FAULT           = 4,
 328 #if defined(RGX_FEATURE_CLUSTER_GROUPING)
 329         RGX_HWRTYPE_TEXASBIF0FAULT      = 5,
 330 #endif
 331 #else
 332         RGX_HWRTYPE_MMUFAULT            = 6,
 333         RGX_HWRTYPE_MMUMETAFAULT        = 7,
 334 #endif
 335 } RGX_HWRTYPE;
 336
 337 #define RGXFWIF_BIFFAULTBIT_GET(ui32BIFMMUStatus) \
 338                 ((ui32BIFMMUStatus & ~RGX_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_CLRMSK) >> RGX_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_SHIFT)
 339 #define RGXFWIF_MMUFAULTBIT_GET(ui32BIFMMUStatus) \
 340                 ((ui32BIFMMUStatus & ~RGX_CR_MMU_FAULT_STATUS_FAULT_CLRMSK) >> RGX_CR_MMU_FAULT_STATUS_FAULT_SHIFT)
 341
 342 #define RGXFWIF_HWRTYPE_BIF_BANK_GET(eHWRType) ((eHWRType == RGX_HWRTYPE_BIF0FAULT) ? 0 : 1 )
 343
 344 typedef struct _RGX_BIFINFO_
 345 {
 346         IMG_UINT64      RGXFW_ALIGN             ui64BIFReqStatus;
 347         IMG_UINT64      RGXFW_ALIGN             ui64BIFMMUStatus;
 348         IMG_UINT64      RGXFW_ALIGN             ui64PCAddress; /*!< phys address of the page catalogue */
 349 } RGX_BIFINFO;
 350
 351 typedef struct _RGX_MMUINFO_
 352 {
 353         IMG_UINT64      RGXFW_ALIGN             ui64MMUStatus;
 354 } RGX_MMUINFO;
 355
 356 typedef struct _RGX_POLLINFO_
 357 {
 358         IMG_UINT32      ui32ThreadNum;
 359         IMG_UINT32      ui32CrPollAddr;
 360         IMG_UINT32      ui32CrPollMask;
 361 } RGX_POLLINFO;
 362
 363 typedef struct _RGX_HWRINFO_
 364 {
 365         union
 366         {
 367                 RGX_BIFINFO             sBIFInfo;
 368                 RGX_MMUINFO             sMMUInfo;
 369                 RGX_POLLINFO    sPollInfo;
 370         } uHWRData;
 371
 372         IMG_UINT64      RGXFW_ALIGN             ui64CRTimer;
 373         IMG_UINT32                                      ui32FrameNum;
 374         IMG_UINT32                                      ui32PID;
 375         IMG_UINT32                                      ui32ActiveHWRTData;
 376         IMG_UINT32                                      ui32HWRNumber;
 377         IMG_UINT32                                      ui32EventStatus;
 378         IMG_UINT32                                      ui32HWRRecoveryFlags;
 379         RGX_HWRTYPE                             eHWRType;
 380
 381         RGXFWIF_DM                                      eDM;
 382 } RGX_HWRINFO;
 383
 384 #define RGXFWIF_HWINFO_MAX_FIRST 8                                                      /* Number of first HWR logs recorded (never overwritten by newer logs) */
 385 #define RGXFWIF_HWINFO_MAX_LAST 8                                                       /* Number of latest HWR logs (older logs are overwritten by newer logs) */
 386 #define RGXFWIF_HWINFO_MAX (RGXFWIF_HWINFO_MAX_FIRST + RGXFWIF_HWINFO_MAX_LAST) /* Total number of HWR logs stored in a buffer */
 387 #define RGXFWIF_HWINFO_LAST_INDEX (RGXFWIF_HWINFO_MAX - 1)      /* Index of the last log in the HWR log buffer */
 388 typedef struct _RGXFWIF_HWRINFOBUF_
 389 {
 390         RGX_HWRINFO sHWRInfo[RGXFWIF_HWINFO_MAX];
 391
 392         IMG_UINT32      ui32FirstCrPollAddr[RGXFW_THREAD_NUM];
 393         IMG_UINT32      ui32FirstCrPollMask[RGXFW_THREAD_NUM];
 394         IMG_UINT32      ui32WriteIndex;
 395         IMG_BOOL        bDDReqIssued;
 396 } RGXFWIF_HWRINFOBUF;
 397
 398 /*! RGX firmware Init Config Data */
 399 #define RGXFWIF_INICFG_CTXSWITCH_TA_EN          (0x1 << 0)
 400 #define RGXFWIF_INICFG_CTXSWITCH_3D_EN          (0x1 << 1)
 401 #define RGXFWIF_INICFG_CTXSWITCH_CDM_EN         (0x1 << 2)
 402 #define RGXFWIF_INICFG_CTXSWITCH_MODE_RAND      (0x1 << 3)
 403 #define RGXFWIF_INICFG_CTXSWITCH_SRESET_EN      (0x1 << 4)
 404 #define RGXFWIF_INICFG_RSVD                                     (0x1 << 5)
 405 #define RGXFWIF_INICFG_POW_RASCALDUST           (0x1 << 6)
 406 #define RGXFWIF_INICFG_HWPERF_EN                        (0x1 << 7)
 407 #define RGXFWIF_INICFG_HWR_EN                           (0x1 << 8)
 408 #define RGXFWIF_INICFG_CHECK_MLIST_EN           (0x1 << 9)
 409 #define RGXFWIF_INICFG_DISABLE_CLKGATING_EN (0x1 << 10)
 410 #define RGXFWIF_INICFG_POLL_COUNTERS_EN         (0x1 << 11)
 411 #define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INDEX         (RGX_CR_VDM_CONTEXT_STORE_MODE_MODE_INDEX << 12)
 412 #define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INSTANCE      (RGX_CR_VDM_CONTEXT_STORE_MODE_MODE_INSTANCE << 12)
 413 #define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_LIST          (RGX_CR_VDM_CONTEXT_STORE_MODE_MODE_LIST << 12)
 414 #define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_CLRMSK        (0xFFFFCFFFU)
 415 #define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_SHIFT         (12)
 416 #define RGXFWIF_INICFG_SHG_BYPASS_EN            (0x1 << 14)
 417 #define RGXFWIF_INICFG_RTU_BYPASS_EN            (0x1 << 15)
 418 #define RGXFWIF_INICFG_REGCONFIG_EN             (0x1 << 16)
 419 #define RGXFWIF_INICFG_ASSERT_ON_OUTOFMEMORY    (0x1 << 17)
 420 #define RGXFWIF_INICFG_HWP_DISABLE_FILTER  (0x1 << 18)
 421 #define RGXFWIF_INICFG_ALL                                      (0x0007FFDFU)
 422 #define RGXFWIF_SRVCFG_DISABLE_PDP_EN           (0x1 << 31)
 423 #define RGXFWIF_SRVCFG_ALL                                      (0x80000000U)
 424 #define RGXFWIF_FILTCFG_TRUNCATE_HALF           (0x1 << 3)
 425 #define RGXFWIF_FILTCFG_TRUNCATE_INT            (0x1 << 2)
 426 #define RGXFWIF_FILTCFG_NEW_FILTER_MODE         (0x1 << 1)
 427
 428 #define RGXFWIF_INICFG_CTXSWITCH_DM_ALL         (RGXFWIF_INICFG_CTXSWITCH_TA_EN | \
 429                                                                                          RGXFWIF_INICFG_CTXSWITCH_3D_EN | \
 430                                                                                          RGXFWIF_INICFG_CTXSWITCH_CDM_EN)
 431
 432 #define RGXFWIF_INICFG_CTXSWITCH_CLRMSK         ~(RGXFWIF_INICFG_CTXSWITCH_DM_ALL | \
 433                                                                                          RGXFWIF_INICFG_CTXSWITCH_MODE_RAND | \
 434                                                                                          RGXFWIF_INICFG_CTXSWITCH_SRESET_EN)
 435
 436 typedef enum
 437 {
 438         RGX_ACTIVEPM_FORCE_OFF = 0,
 439         RGX_ACTIVEPM_FORCE_ON = 1,
 440         RGX_ACTIVEPM_DEFAULT = 3
 441 } RGX_ACTIVEPM_CONF;
 442
 443 /*!
 444  ******************************************************************************
 445  * Querying DM state
 446  *****************************************************************************/
 447
 448 typedef enum _RGXFWIF_DM_STATE_
 449 {
 450         RGXFWIF_DM_STATE_NORMAL                 = 0,
 451         RGXFWIF_DM_STATE_LOCKEDUP               = 1,
 452
 453 } RGXFWIF_DM_STATE;
 454
 455 typedef struct
 456 {
 457         IMG_UINT16  ui16RegNum;                         /*!< Register number */
 458         IMG_UINT16  ui16IndirectRegNum;         /*!< Indirect register number (or 0 if not used) */
 459         IMG_UINT16  ui16IndirectStartVal;       /*!< Start value for indirect register */
 460         IMG_UINT16  ui16IndirectEndVal;         /*!< End value for indirect register */
 461 } RGXFW_REGISTER_LIST;
 462
 463 #endif /*  __RGX_FWIF_H__ */
 464
 465 /******************************************************************************
 466  End of file (rgx_fwif.h)
 467 ******************************************************************************/
 468