2 * Copyright (C) 2013 NVIDIA Corporation
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
23 #include <linux/clk.h>
24 #include <linux/delay.h>
25 #include <linux/host1x.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
33 #define MIPI_CAL_CTRL 0x00
34 #define MIPI_CAL_CTRL_NOISE_FILTER(x) (((x) & 0xf) << 26)
35 #define MIPI_CAL_CTRL_PRESCALE(x) (((x) & 0x3) << 24)
36 #define MIPI_CAL_CTRL_CLKEN_OVR (1 << 4)
37 #define MIPI_CAL_CTRL_START (1 << 0)
39 #define MIPI_CAL_AUTOCAL_CTRL 0x01
41 #define MIPI_CAL_STATUS 0x02
42 #define MIPI_CAL_STATUS_DONE (1 << 16)
43 #define MIPI_CAL_STATUS_ACTIVE (1 << 0)
45 #define MIPI_CAL_CONFIG_CSIA 0x05
46 #define MIPI_CAL_CONFIG_CSIB 0x06
47 #define MIPI_CAL_CONFIG_CSIC 0x07
48 #define MIPI_CAL_CONFIG_CSID 0x08
49 #define MIPI_CAL_CONFIG_CSIE 0x09
50 #define MIPI_CAL_CONFIG_DSIA 0x0e
51 #define MIPI_CAL_CONFIG_DSIB 0x0f
52 #define MIPI_CAL_CONFIG_DSIC 0x10
53 #define MIPI_CAL_CONFIG_DSID 0x11
55 #define MIPI_CAL_CONFIG_DSIA_CLK 0x19
56 #define MIPI_CAL_CONFIG_DSIB_CLK 0x1a
57 #define MIPI_CAL_CONFIG_CSIAB_CLK 0x1b
58 #define MIPI_CAL_CONFIG_CSICD_CLK 0x1c
59 #define MIPI_CAL_CONFIG_CSIE_CLK 0x1d
61 /* for data and clock lanes */
62 #define MIPI_CAL_CONFIG_SELECT (1 << 21)
65 #define MIPI_CAL_CONFIG_HSPDOS(x) (((x) & 0x1f) << 16)
66 #define MIPI_CAL_CONFIG_HSPUOS(x) (((x) & 0x1f) << 8)
67 #define MIPI_CAL_CONFIG_TERMOS(x) (((x) & 0x1f) << 0)
70 #define MIPI_CAL_CONFIG_HSCLKPDOSD(x) (((x) & 0x1f) << 8)
71 #define MIPI_CAL_CONFIG_HSCLKPUOSD(x) (((x) & 0x1f) << 0)
73 #define MIPI_CAL_BIAS_PAD_CFG0 0x16
74 #define MIPI_CAL_BIAS_PAD_PDVCLAMP (1 << 1)
75 #define MIPI_CAL_BIAS_PAD_E_VCLAMP_REF (1 << 0)
77 #define MIPI_CAL_BIAS_PAD_CFG1 0x17
78 #define MIPI_CAL_BIAS_PAD_DRV_DN_REF(x) (((x) & 0x7) << 16)
79 #define MIPI_CAL_BIAS_PAD_DRV_UP_REF(x) (((x) & 0x7) << 8)
81 #define MIPI_CAL_BIAS_PAD_CFG2 0x18
82 #define MIPI_CAL_BIAS_PAD_VCLAMP(x) (((x) & 0x7) << 16)
83 #define MIPI_CAL_BIAS_PAD_VAUXP(x) (((x) & 0x7) << 4)
84 #define MIPI_CAL_BIAS_PAD_PDVREG (1 << 1)
86 struct tegra_mipi_pad {
91 struct tegra_mipi_soc {
93 const struct tegra_mipi_pad *pads;
94 unsigned int num_pads;
96 bool clock_enable_override;
97 bool needs_vclamp_ref;
99 /* bias pad configuration settings */
100 u8 pad_drive_down_ref;
106 /* calibration settings for data lanes */
111 /* calibration settings for clock lanes */
117 const struct tegra_mipi_soc *soc;
123 struct tegra_mipi_device {
124 struct platform_device *pdev;
125 struct tegra_mipi *mipi;
126 struct device *device;
130 static inline u32 tegra_mipi_readl(struct tegra_mipi *mipi,
131 unsigned long offset)
133 return readl(mipi->regs + (offset << 2));
136 static inline void tegra_mipi_writel(struct tegra_mipi *mipi, u32 value,
137 unsigned long offset)
139 writel(value, mipi->regs + (offset << 2));
142 struct tegra_mipi_device *tegra_mipi_request(struct device *device)
144 struct device_node *np = device->of_node;
145 struct tegra_mipi_device *dev;
146 struct of_phandle_args args;
149 err = of_parse_phandle_with_args(np, "nvidia,mipi-calibrate",
150 "#nvidia,mipi-calibrate-cells", 0,
155 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
161 dev->pdev = of_find_device_by_node(args.np);
167 dev->mipi = platform_get_drvdata(dev->pdev);
173 of_node_put(args.np);
175 dev->pads = args.args[0];
176 dev->device = device;
181 platform_device_put(dev->pdev);
185 of_node_put(args.np);
188 EXPORT_SYMBOL(tegra_mipi_request);
190 void tegra_mipi_free(struct tegra_mipi_device *device)
192 platform_device_put(device->pdev);
195 EXPORT_SYMBOL(tegra_mipi_free);
197 static int tegra_mipi_wait(struct tegra_mipi *mipi)
199 unsigned long timeout = jiffies + msecs_to_jiffies(250);
202 while (time_before(jiffies, timeout)) {
203 value = tegra_mipi_readl(mipi, MIPI_CAL_STATUS);
204 if ((value & MIPI_CAL_STATUS_ACTIVE) == 0 &&
205 (value & MIPI_CAL_STATUS_DONE) != 0)
208 usleep_range(10, 50);
214 int tegra_mipi_calibrate(struct tegra_mipi_device *device)
216 const struct tegra_mipi_soc *soc = device->mipi->soc;
221 err = clk_enable(device->mipi->clk);
225 mutex_lock(&device->mipi->lock);
227 value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG0);
228 value &= ~MIPI_CAL_BIAS_PAD_PDVCLAMP;
230 if (soc->needs_vclamp_ref)
231 value |= MIPI_CAL_BIAS_PAD_E_VCLAMP_REF;
233 tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG0);
235 value = MIPI_CAL_BIAS_PAD_DRV_DN_REF(soc->pad_drive_down_ref) |
236 MIPI_CAL_BIAS_PAD_DRV_UP_REF(soc->pad_drive_up_ref);
237 tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG1);
239 value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG2);
240 value &= ~MIPI_CAL_BIAS_PAD_PDVREG;
241 tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG2);
243 value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG2);
244 value &= ~MIPI_CAL_BIAS_PAD_VCLAMP(0x7);
245 value &= ~MIPI_CAL_BIAS_PAD_VAUXP(0x7);
246 value |= MIPI_CAL_BIAS_PAD_VCLAMP(soc->pad_vclamp_level);
247 value |= MIPI_CAL_BIAS_PAD_VAUXP(soc->pad_vauxp_level);
248 tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG2);
250 for (i = 0; i < soc->num_pads; i++) {
251 u32 clk = 0, data = 0;
253 if (device->pads & BIT(i)) {
254 data = MIPI_CAL_CONFIG_SELECT |
255 MIPI_CAL_CONFIG_HSPDOS(soc->hspdos) |
256 MIPI_CAL_CONFIG_HSPUOS(soc->hspuos) |
257 MIPI_CAL_CONFIG_TERMOS(soc->termos);
258 clk = MIPI_CAL_CONFIG_SELECT |
259 MIPI_CAL_CONFIG_HSCLKPDOSD(soc->hsclkpdos) |
260 MIPI_CAL_CONFIG_HSCLKPUOSD(soc->hsclkpuos);
263 tegra_mipi_writel(device->mipi, data, soc->pads[i].data);
265 if (soc->has_clk_lane)
266 tegra_mipi_writel(device->mipi, clk, soc->pads[i].clk);
269 value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL);
270 value &= ~MIPI_CAL_CTRL_NOISE_FILTER(0xf);
271 value &= ~MIPI_CAL_CTRL_PRESCALE(0x3);
272 value |= MIPI_CAL_CTRL_NOISE_FILTER(0xa);
273 value |= MIPI_CAL_CTRL_PRESCALE(0x2);
275 if (!soc->clock_enable_override)
276 value &= ~MIPI_CAL_CTRL_CLKEN_OVR;
278 value |= MIPI_CAL_CTRL_CLKEN_OVR;
280 tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL);
282 /* clear any pending status bits */
283 value = tegra_mipi_readl(device->mipi, MIPI_CAL_STATUS);
284 tegra_mipi_writel(device->mipi, value, MIPI_CAL_STATUS);
286 value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL);
287 value |= MIPI_CAL_CTRL_START;
288 tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL);
290 err = tegra_mipi_wait(device->mipi);
292 mutex_unlock(&device->mipi->lock);
293 clk_disable(device->mipi->clk);
297 EXPORT_SYMBOL(tegra_mipi_calibrate);
299 static const struct tegra_mipi_pad tegra114_mipi_pads[] = {
300 { .data = MIPI_CAL_CONFIG_CSIA },
301 { .data = MIPI_CAL_CONFIG_CSIB },
302 { .data = MIPI_CAL_CONFIG_CSIC },
303 { .data = MIPI_CAL_CONFIG_CSID },
304 { .data = MIPI_CAL_CONFIG_CSIE },
305 { .data = MIPI_CAL_CONFIG_DSIA },
306 { .data = MIPI_CAL_CONFIG_DSIB },
307 { .data = MIPI_CAL_CONFIG_DSIC },
308 { .data = MIPI_CAL_CONFIG_DSID },
311 static const struct tegra_mipi_soc tegra114_mipi_soc = {
312 .has_clk_lane = false,
313 .pads = tegra114_mipi_pads,
314 .num_pads = ARRAY_SIZE(tegra114_mipi_pads),
315 .clock_enable_override = true,
316 .needs_vclamp_ref = true,
317 .pad_drive_down_ref = 0x2,
318 .pad_drive_up_ref = 0x0,
319 .pad_vclamp_level = 0x0,
320 .pad_vauxp_level = 0x0,
328 static const struct tegra_mipi_pad tegra124_mipi_pads[] = {
329 { .data = MIPI_CAL_CONFIG_CSIA, .clk = MIPI_CAL_CONFIG_CSIAB_CLK },
330 { .data = MIPI_CAL_CONFIG_CSIB, .clk = MIPI_CAL_CONFIG_CSIAB_CLK },
331 { .data = MIPI_CAL_CONFIG_CSIC, .clk = MIPI_CAL_CONFIG_CSICD_CLK },
332 { .data = MIPI_CAL_CONFIG_CSID, .clk = MIPI_CAL_CONFIG_CSICD_CLK },
333 { .data = MIPI_CAL_CONFIG_CSIE, .clk = MIPI_CAL_CONFIG_CSIE_CLK },
334 { .data = MIPI_CAL_CONFIG_DSIA, .clk = MIPI_CAL_CONFIG_DSIA_CLK },
335 { .data = MIPI_CAL_CONFIG_DSIB, .clk = MIPI_CAL_CONFIG_DSIB_CLK },
338 static const struct tegra_mipi_soc tegra124_mipi_soc = {
339 .has_clk_lane = true,
340 .pads = tegra124_mipi_pads,
341 .num_pads = ARRAY_SIZE(tegra124_mipi_pads),
342 .clock_enable_override = true,
343 .needs_vclamp_ref = true,
344 .pad_drive_down_ref = 0x2,
345 .pad_drive_up_ref = 0x0,
346 .pad_vclamp_level = 0x0,
347 .pad_vauxp_level = 0x0,
355 static const struct of_device_id tegra_mipi_of_match[] = {
356 { .compatible = "nvidia,tegra114-mipi", .data = &tegra114_mipi_soc },
357 { .compatible = "nvidia,tegra124-mipi", .data = &tegra124_mipi_soc },
361 static int tegra_mipi_probe(struct platform_device *pdev)
363 const struct of_device_id *match;
364 struct tegra_mipi *mipi;
365 struct resource *res;
368 match = of_match_node(tegra_mipi_of_match, pdev->dev.of_node);
372 mipi = devm_kzalloc(&pdev->dev, sizeof(*mipi), GFP_KERNEL);
376 mipi->soc = match->data;
378 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
379 mipi->regs = devm_ioremap_resource(&pdev->dev, res);
380 if (IS_ERR(mipi->regs))
381 return PTR_ERR(mipi->regs);
383 mutex_init(&mipi->lock);
385 mipi->clk = devm_clk_get(&pdev->dev, NULL);
386 if (IS_ERR(mipi->clk)) {
387 dev_err(&pdev->dev, "failed to get clock\n");
388 return PTR_ERR(mipi->clk);
391 err = clk_prepare(mipi->clk);
395 platform_set_drvdata(pdev, mipi);
400 static int tegra_mipi_remove(struct platform_device *pdev)
402 struct tegra_mipi *mipi = platform_get_drvdata(pdev);
404 clk_unprepare(mipi->clk);
409 struct platform_driver tegra_mipi_driver = {
411 .name = "tegra-mipi",
412 .of_match_table = tegra_mipi_of_match,
414 .probe = tegra_mipi_probe,
415 .remove = tegra_mipi_remove,