drivers/gpu/drm/vc4/vc4_crtc.c

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /**
  10  * DOC: VC4 CRTC module
  11  *
  12  * In VC4, the Pixel Valve is what most closely corresponds to the
  13  * DRM's concept of a CRTC.  The PV generates video timings from the
  14  * output's clock plus its configuration.  It pulls scaled pixels from
  15  * the HVS at that timing, and feeds it to the encoder.
  16  *
  17  * However, the DRM CRTC also collects the configuration of all the
  18  * DRM planes attached to it.  As a result, this file also manages
  19  * setup of the VC4 HVS's display elements on the CRTC.
  20  *
  21  * The 2835 has 3 different pixel valves.  pv0 in the audio power
  22  * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI.  pv2 in the
  23  * image domain can feed either HDMI or the SDTV controller.  The
  24  * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
  25  * SDTV, etc.) according to which output type is chosen in the mux.
  26  *
  27  * For power management, the pixel valve's registers are all clocked
  28  * by the AXI clock, while the timings and FIFOs make use of the
  29  * output-specific clock.  Since the encoders also directly consume
  30  * the CPRMAN clocks, and know what timings they need, they are the
  31  * ones that set the clock.
  32  */
  33
  34 #include "drm_atomic.h"
  35 #include "drm_atomic_helper.h"
  36 #include "drm_crtc_helper.h"
  37 #include "linux/clk.h"
  38 #include "linux/component.h"
  39 #include "linux/of_device.h"
  40 #include "vc4_drv.h"
  41 #include "vc4_regs.h"
  42
  43 struct vc4_crtc {
  44         struct drm_crtc base;
  45         const struct vc4_crtc_data *data;
  46         void __iomem *regs;
  47
  48         /* Which HVS channel we're using for our CRTC. */
  49         int channel;
  50
  51         /* Pointer to the actual hardware display list memory for the
  52          * crtc.
  53          */
  54         u32 __iomem *dlist;
  55
  56         u32 dlist_size; /* in dwords */
  57
  58         struct drm_pending_vblank_event *event;
  59 };
  60
  61 static inline struct vc4_crtc *
  62 to_vc4_crtc(struct drm_crtc *crtc)
  63 {
  64         return (struct vc4_crtc *)crtc;
  65 }
  66
  67 struct vc4_crtc_data {
  68         /* Which channel of the HVS this pixelvalve sources from. */
  69         int hvs_channel;
  70
  71         enum vc4_encoder_type encoder0_type;
  72         enum vc4_encoder_type encoder1_type;
  73 };
  74
  75 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
  76 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
  77
  78 #define CRTC_REG(reg) { reg, #reg }
  79 static const struct {
  80         u32 reg;
  81         const char *name;
  82 } crtc_regs[] = {
  83         CRTC_REG(PV_CONTROL),
  84         CRTC_REG(PV_V_CONTROL),
  85         CRTC_REG(PV_VSYNCD),
  86         CRTC_REG(PV_HORZA),
  87         CRTC_REG(PV_HORZB),
  88         CRTC_REG(PV_VERTA),
  89         CRTC_REG(PV_VERTB),
  90         CRTC_REG(PV_VERTA_EVEN),
  91         CRTC_REG(PV_VERTB_EVEN),
  92         CRTC_REG(PV_INTEN),
  93         CRTC_REG(PV_INTSTAT),
  94         CRTC_REG(PV_STAT),
  95         CRTC_REG(PV_HACT_ACT),
  96 };
  97
  98 static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc)
  99 {
 100         int i;
 101
 102         for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
 103                 DRM_INFO("0x%04x (%s): 0x%08x\n",
 104                          crtc_regs[i].reg, crtc_regs[i].name,
 105                          CRTC_READ(crtc_regs[i].reg));
 106         }
 107 }
 108
 109 #ifdef CONFIG_DEBUG_FS
 110 int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused)
 111 {
 112         struct drm_info_node *node = (struct drm_info_node *)m->private;
 113         struct drm_device *dev = node->minor->dev;
 114         int crtc_index = (uintptr_t)node->info_ent->data;
 115         struct drm_crtc *crtc;
 116         struct vc4_crtc *vc4_crtc;
 117         int i;
 118
 119         i = 0;
 120         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 121                 if (i == crtc_index)
 122                         break;
 123                 i++;
 124         }
 125         if (!crtc)
 126                 return 0;
 127         vc4_crtc = to_vc4_crtc(crtc);
 128
 129         for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
 130                 seq_printf(m, "%s (0x%04x): 0x%08x\n",
 131                            crtc_regs[i].name, crtc_regs[i].reg,
 132                            CRTC_READ(crtc_regs[i].reg));
 133         }
 134
 135         return 0;
 136 }
 137 #endif
 138
 139 static void vc4_crtc_destroy(struct drm_crtc *crtc)
 140 {
 141         drm_crtc_cleanup(crtc);
 142 }
 143
 144 static u32 vc4_get_fifo_full_level(u32 format)
 145 {
 146         static const u32 fifo_len_bytes = 64;
 147         static const u32 hvs_latency_pix = 6;
 148
 149         switch (format) {
 150         case PV_CONTROL_FORMAT_DSIV_16:
 151         case PV_CONTROL_FORMAT_DSIC_16:
 152                 return fifo_len_bytes - 2 * hvs_latency_pix;
 153         case PV_CONTROL_FORMAT_DSIV_18:
 154                 return fifo_len_bytes - 14;
 155         case PV_CONTROL_FORMAT_24:
 156         case PV_CONTROL_FORMAT_DSIV_24:
 157         default:
 158                 return fifo_len_bytes - 3 * hvs_latency_pix;
 159         }
 160 }
 161
 162 /*
 163  * Returns the clock select bit for the connector attached to the
 164  * CRTC.
 165  */
 166 static int vc4_get_clock_select(struct drm_crtc *crtc)
 167 {
 168         struct drm_connector *connector;
 169
 170         drm_for_each_connector(connector, crtc->dev) {
 171                 if (connector->state->crtc == crtc) {
 172                         struct drm_encoder *encoder = connector->encoder;
 173                         struct vc4_encoder *vc4_encoder =
 174                                 to_vc4_encoder(encoder);
 175
 176                         return vc4_encoder->clock_select;
 177                 }
 178         }
 179
 180         return -1;
 181 }
 182
 183 static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
 184 {
 185         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 186         struct drm_crtc_state *state = crtc->state;
 187         struct drm_display_mode *mode = &state->adjusted_mode;
 188         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 189         u32 vactive = (mode->vdisplay >> (interlace ? 1 : 0));
 190         u32 format = PV_CONTROL_FORMAT_24;
 191         bool debug_dump_regs = false;
 192         int clock_select = vc4_get_clock_select(crtc);
 193
 194         if (debug_dump_regs) {
 195                 DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
 196                 vc4_crtc_dump_regs(vc4_crtc);
 197         }
 198
 199         /* Reset the PV fifo. */
 200         CRTC_WRITE(PV_CONTROL, 0);
 201         CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
 202         CRTC_WRITE(PV_CONTROL, 0);
 203
 204         CRTC_WRITE(PV_HORZA,
 205                    VC4_SET_FIELD(mode->htotal - mode->hsync_end,
 206                                  PV_HORZA_HBP) |
 207                    VC4_SET_FIELD(mode->hsync_end - mode->hsync_start,
 208                                  PV_HORZA_HSYNC));
 209         CRTC_WRITE(PV_HORZB,
 210                    VC4_SET_FIELD(mode->hsync_start - mode->hdisplay,
 211                                  PV_HORZB_HFP) |
 212                    VC4_SET_FIELD(mode->hdisplay, PV_HORZB_HACTIVE));
 213
 214         if (interlace) {
 215                 CRTC_WRITE(PV_VERTA_EVEN,
 216                            VC4_SET_FIELD(mode->vtotal - mode->vsync_end - 1,
 217                                          PV_VERTA_VBP) |
 218                            VC4_SET_FIELD(mode->vsync_end - mode->vsync_start,
 219                                          PV_VERTA_VSYNC));
 220                 CRTC_WRITE(PV_VERTB_EVEN,
 221                            VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,
 222                                          PV_VERTB_VFP) |
 223                            VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE));
 224         }
 225
 226         CRTC_WRITE(PV_HACT_ACT, mode->hdisplay);
 227
 228         CRTC_WRITE(PV_V_CONTROL,
 229                    PV_VCONTROL_CONTINUOUS |
 230                    (interlace ? PV_VCONTROL_INTERLACE : 0));
 231
 232         CRTC_WRITE(PV_CONTROL,
 233                    VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
 234                    VC4_SET_FIELD(vc4_get_fifo_full_level(format),
 235                                  PV_CONTROL_FIFO_LEVEL) |
 236                    PV_CONTROL_CLR_AT_START |
 237                    PV_CONTROL_TRIGGER_UNDERFLOW |
 238                    PV_CONTROL_WAIT_HSTART |
 239                    VC4_SET_FIELD(clock_select, PV_CONTROL_CLK_SELECT) |
 240                    PV_CONTROL_FIFO_CLR |
 241                    PV_CONTROL_EN);
 242
 243         if (debug_dump_regs) {
 244                 DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
 245                 vc4_crtc_dump_regs(vc4_crtc);
 246         }
 247 }
 248
 249 static void require_hvs_enabled(struct drm_device *dev)
 250 {
 251         struct vc4_dev *vc4 = to_vc4_dev(dev);
 252
 253         WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
 254                      SCALER_DISPCTRL_ENABLE);
 255 }
 256
 257 static void vc4_crtc_disable(struct drm_crtc *crtc)
 258 {
 259         struct drm_device *dev = crtc->dev;
 260         struct vc4_dev *vc4 = to_vc4_dev(dev);
 261         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 262         u32 chan = vc4_crtc->channel;
 263         int ret;
 264         require_hvs_enabled(dev);
 265
 266         CRTC_WRITE(PV_V_CONTROL,
 267                    CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
 268         ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
 269         WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
 270
 271         if (HVS_READ(SCALER_DISPCTRLX(chan)) &
 272             SCALER_DISPCTRLX_ENABLE) {
 273                 HVS_WRITE(SCALER_DISPCTRLX(chan),
 274                           SCALER_DISPCTRLX_RESET);
 275
 276                 /* While the docs say that reset is self-clearing, it
 277                  * seems it doesn't actually.
 278                  */
 279                 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
 280         }
 281
 282         /* Once we leave, the scaler should be disabled and its fifo empty. */
 283
 284         WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
 285
 286         WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
 287                                    SCALER_DISPSTATX_MODE) !=
 288                      SCALER_DISPSTATX_MODE_DISABLED);
 289
 290         WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
 291                       (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
 292                      SCALER_DISPSTATX_EMPTY);
 293 }
 294
 295 static void vc4_crtc_enable(struct drm_crtc *crtc)
 296 {
 297         struct drm_device *dev = crtc->dev;
 298         struct vc4_dev *vc4 = to_vc4_dev(dev);
 299         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 300         struct drm_crtc_state *state = crtc->state;
 301         struct drm_display_mode *mode = &state->adjusted_mode;
 302
 303         require_hvs_enabled(dev);
 304
 305         /* Turn on the scaler, which will wait for vstart to start
 306          * compositing.
 307          */
 308         HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
 309                   VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
 310                   VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
 311                   SCALER_DISPCTRLX_ENABLE);
 312
 313         /* Turn on the pixel valve, which will emit the vstart signal. */
 314         CRTC_WRITE(PV_V_CONTROL,
 315                    CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
 316 }
 317
 318 static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
 319                                  struct drm_crtc_state *state)
 320 {
 321         struct drm_device *dev = crtc->dev;
 322         struct vc4_dev *vc4 = to_vc4_dev(dev);
 323         struct drm_plane *plane;
 324         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 325         u32 dlist_count = 0;
 326
 327         /* The pixelvalve can only feed one encoder (and encoders are
 328          * 1:1 with connectors.)
 329          */
 330         if (drm_atomic_connectors_for_crtc(state->state, crtc) > 1)
 331                 return -EINVAL;
 332
 333         drm_atomic_crtc_state_for_each_plane(plane, state) {
 334                 struct drm_plane_state *plane_state =
 335                         state->state->plane_states[drm_plane_index(plane)];
 336
 337                 /* plane might not have changed, in which case take
 338                  * current state:
 339                  */
 340                 if (!plane_state)
 341                         plane_state = plane->state;
 342
 343                 dlist_count += vc4_plane_dlist_size(plane_state);
 344         }
 345
 346         dlist_count++; /* Account for SCALER_CTL0_END. */
 347
 348         if (!vc4_crtc->dlist || dlist_count > vc4_crtc->dlist_size) {
 349                 vc4_crtc->dlist = ((u32 __iomem *)vc4->hvs->dlist +
 350                                    HVS_BOOTLOADER_DLIST_END);
 351                 vc4_crtc->dlist_size = ((SCALER_DLIST_SIZE >> 2) -
 352                                         HVS_BOOTLOADER_DLIST_END);
 353
 354                 if (dlist_count > vc4_crtc->dlist_size) {
 355                         DRM_DEBUG_KMS("dlist too large for CRTC (%d > %d).\n",
 356                                       dlist_count, vc4_crtc->dlist_size);
 357                         return -EINVAL;
 358                 }
 359         }
 360
 361         return 0;
 362 }
 363
 364 static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
 365                                   struct drm_crtc_state *old_state)
 366 {
 367         struct drm_device *dev = crtc->dev;
 368         struct vc4_dev *vc4 = to_vc4_dev(dev);
 369         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 370         struct drm_plane *plane;
 371         bool debug_dump_regs = false;
 372         u32 __iomem *dlist_next = vc4_crtc->dlist;
 373
 374         if (debug_dump_regs) {
 375                 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
 376                 vc4_hvs_dump_state(dev);
 377         }
 378
 379         /* Copy all the active planes' dlist contents to the hardware dlist.
 380          *
 381          * XXX: If the new display list was large enough that it
 382          * overlapped a currently-read display list, we need to do
 383          * something like disable scanout before putting in the new
 384          * list.  For now, we're safe because we only have the two
 385          * planes.
 386          */
 387         drm_atomic_crtc_for_each_plane(plane, crtc) {
 388                 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
 389         }
 390
 391         if (dlist_next == vc4_crtc->dlist) {
 392                 /* If no planes were enabled, use the SCALER_CTL0_END
 393                  * at the start of the display list memory (in the
 394                  * bootloader section).  We'll rewrite that
 395                  * SCALER_CTL0_END, just in case, though.
 396                  */
 397                 writel(SCALER_CTL0_END, vc4->hvs->dlist);
 398                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel), 0);
 399         } else {
 400                 writel(SCALER_CTL0_END, dlist_next);
 401                 dlist_next++;
 402
 403                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
 404                           (u32 *)vc4_crtc->dlist - (u32 *)vc4->hvs->dlist);
 405
 406                 /* Make the next display list start after ours. */
 407                 vc4_crtc->dlist_size -= (dlist_next - vc4_crtc->dlist);
 408                 vc4_crtc->dlist = dlist_next;
 409         }
 410
 411         if (debug_dump_regs) {
 412                 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
 413                 vc4_hvs_dump_state(dev);
 414         }
 415
 416         if (crtc->state->event) {
 417                 unsigned long flags;
 418
 419                 crtc->state->event->pipe = drm_crtc_index(crtc);
 420
 421                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 422
 423                 spin_lock_irqsave(&dev->event_lock, flags);
 424                 vc4_crtc->event = crtc->state->event;
 425                 spin_unlock_irqrestore(&dev->event_lock, flags);
 426                 crtc->state->event = NULL;
 427         }
 428 }
 429
 430 int vc4_enable_vblank(struct drm_device *dev, unsigned int crtc_id)
 431 {
 432         struct vc4_dev *vc4 = to_vc4_dev(dev);
 433         struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
 434
 435         CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
 436
 437         return 0;
 438 }
 439
 440 void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id)
 441 {
 442         struct vc4_dev *vc4 = to_vc4_dev(dev);
 443         struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
 444
 445         CRTC_WRITE(PV_INTEN, 0);
 446 }
 447
 448 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
 449 {
 450         struct drm_crtc *crtc = &vc4_crtc->base;
 451         struct drm_device *dev = crtc->dev;
 452         unsigned long flags;
 453
 454         spin_lock_irqsave(&dev->event_lock, flags);
 455         if (vc4_crtc->event) {
 456                 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
 457                 vc4_crtc->event = NULL;
 458         }
 459         spin_unlock_irqrestore(&dev->event_lock, flags);
 460 }
 461
 462 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
 463 {
 464         struct vc4_crtc *vc4_crtc = data;
 465         u32 stat = CRTC_READ(PV_INTSTAT);
 466         irqreturn_t ret = IRQ_NONE;
 467
 468         if (stat & PV_INT_VFP_START) {
 469                 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
 470                 drm_crtc_handle_vblank(&vc4_crtc->base);
 471                 vc4_crtc_handle_page_flip(vc4_crtc);
 472                 ret = IRQ_HANDLED;
 473         }
 474
 475         return ret;
 476 }
 477
 478 static const struct drm_crtc_funcs vc4_crtc_funcs = {
 479         .set_config = drm_atomic_helper_set_config,
 480         .destroy = vc4_crtc_destroy,
 481         .page_flip = drm_atomic_helper_page_flip,
 482         .set_property = NULL,
 483         .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
 484         .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
 485         .reset = drm_atomic_helper_crtc_reset,
 486         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 487         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 488 };
 489
 490 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
 491         .mode_set_nofb = vc4_crtc_mode_set_nofb,
 492         .disable = vc4_crtc_disable,
 493         .enable = vc4_crtc_enable,
 494         .atomic_check = vc4_crtc_atomic_check,
 495         .atomic_flush = vc4_crtc_atomic_flush,
 496 };
 497
 498 /* Frees the page flip event when the DRM device is closed with the
 499  * event still outstanding.
 500  */
 501 void vc4_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
 502 {
 503         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 504         struct drm_device *dev = crtc->dev;
 505         unsigned long flags;
 506
 507         spin_lock_irqsave(&dev->event_lock, flags);
 508
 509         if (vc4_crtc->event && vc4_crtc->event->base.file_priv == file) {
 510                 vc4_crtc->event->base.destroy(&vc4_crtc->event->base);
 511                 drm_crtc_vblank_put(crtc);
 512                 vc4_crtc->event = NULL;
 513         }
 514
 515         spin_unlock_irqrestore(&dev->event_lock, flags);
 516 }
 517
 518 static const struct vc4_crtc_data pv0_data = {
 519         .hvs_channel = 0,
 520         .encoder0_type = VC4_ENCODER_TYPE_DSI0,
 521         .encoder1_type = VC4_ENCODER_TYPE_DPI,
 522 };
 523
 524 static const struct vc4_crtc_data pv1_data = {
 525         .hvs_channel = 2,
 526         .encoder0_type = VC4_ENCODER_TYPE_DSI1,
 527         .encoder1_type = VC4_ENCODER_TYPE_SMI,
 528 };
 529
 530 static const struct vc4_crtc_data pv2_data = {
 531         .hvs_channel = 1,
 532         .encoder0_type = VC4_ENCODER_TYPE_VEC,
 533         .encoder1_type = VC4_ENCODER_TYPE_HDMI,
 534 };
 535
 536 static const struct of_device_id vc4_crtc_dt_match[] = {
 537         { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
 538         { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
 539         { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
 540         {}
 541 };
 542
 543 static void vc4_set_crtc_possible_masks(struct drm_device *drm,
 544                                         struct drm_crtc *crtc)
 545 {
 546         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 547         struct drm_encoder *encoder;
 548
 549         drm_for_each_encoder(encoder, drm) {
 550                 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 551
 552                 if (vc4_encoder->type == vc4_crtc->data->encoder0_type) {
 553                         vc4_encoder->clock_select = 0;
 554                         encoder->possible_crtcs |= drm_crtc_mask(crtc);
 555                 } else if (vc4_encoder->type == vc4_crtc->data->encoder1_type) {
 556                         vc4_encoder->clock_select = 1;
 557                         encoder->possible_crtcs |= drm_crtc_mask(crtc);
 558                 }
 559         }
 560 }
 561
 562 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
 563 {
 564         struct platform_device *pdev = to_platform_device(dev);
 565         struct drm_device *drm = dev_get_drvdata(master);
 566         struct vc4_dev *vc4 = to_vc4_dev(drm);
 567         struct vc4_crtc *vc4_crtc;
 568         struct drm_crtc *crtc;
 569         struct drm_plane *primary_plane, *cursor_plane;
 570         const struct of_device_id *match;
 571         int ret;
 572
 573         vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
 574         if (!vc4_crtc)
 575                 return -ENOMEM;
 576         crtc = &vc4_crtc->base;
 577
 578         match = of_match_device(vc4_crtc_dt_match, dev);
 579         if (!match)
 580                 return -ENODEV;
 581         vc4_crtc->data = match->data;
 582
 583         vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
 584         if (IS_ERR(vc4_crtc->regs))
 585                 return PTR_ERR(vc4_crtc->regs);
 586
 587         /* For now, we create just the primary and the legacy cursor
 588          * planes.  We should be able to stack more planes on easily,
 589          * but to do that we would need to compute the bandwidth
 590          * requirement of the plane configuration, and reject ones
 591          * that will take too much.
 592          */
 593         primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
 594         if (!primary_plane) {
 595                 dev_err(dev, "failed to construct primary plane\n");
 596                 ret = PTR_ERR(primary_plane);
 597                 goto err;
 598         }
 599
 600         cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
 601         if (!cursor_plane) {
 602                 dev_err(dev, "failed to construct cursor plane\n");
 603                 ret = PTR_ERR(cursor_plane);
 604                 goto err_primary;
 605         }
 606
 607         drm_crtc_init_with_planes(drm, crtc, primary_plane, cursor_plane,
 608                                   &vc4_crtc_funcs);
 609         drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
 610         primary_plane->crtc = crtc;
 611         cursor_plane->crtc = crtc;
 612         vc4->crtc[drm_crtc_index(crtc)] = vc4_crtc;
 613         vc4_crtc->channel = vc4_crtc->data->hvs_channel;
 614
 615         CRTC_WRITE(PV_INTEN, 0);
 616         CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
 617         ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
 618                                vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
 619         if (ret)
 620                 goto err_cursor;
 621
 622         vc4_set_crtc_possible_masks(drm, crtc);
 623
 624         platform_set_drvdata(pdev, vc4_crtc);
 625
 626         return 0;
 627
 628 err_cursor:
 629         cursor_plane->funcs->destroy(cursor_plane);
 630 err_primary:
 631         primary_plane->funcs->destroy(primary_plane);
 632 err:
 633         return ret;
 634 }
 635
 636 static void vc4_crtc_unbind(struct device *dev, struct device *master,
 637                             void *data)
 638 {
 639         struct platform_device *pdev = to_platform_device(dev);
 640         struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
 641
 642         vc4_crtc_destroy(&vc4_crtc->base);
 643
 644         CRTC_WRITE(PV_INTEN, 0);
 645
 646         platform_set_drvdata(pdev, NULL);
 647 }
 648
 649 static const struct component_ops vc4_crtc_ops = {
 650         .bind   = vc4_crtc_bind,
 651         .unbind = vc4_crtc_unbind,
 652 };
 653
 654 static int vc4_crtc_dev_probe(struct platform_device *pdev)
 655 {
 656         return component_add(&pdev->dev, &vc4_crtc_ops);
 657 }
 658
 659 static int vc4_crtc_dev_remove(struct platform_device *pdev)
 660 {
 661         component_del(&pdev->dev, &vc4_crtc_ops);
 662         return 0;
 663 }
 664
 665 struct platform_driver vc4_crtc_driver = {
 666         .probe = vc4_crtc_dev_probe,
 667         .remove = vc4_crtc_dev_remove,
 668         .driver = {
 669                 .name = "vc4_crtc",
 670                 .of_match_table = vc4_crtc_dt_match,
 671         },
 672 };