2 * Copyright (C) 2013 NVIDIA Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/delay.h>
11 #include <linux/gpio.h>
12 #include <linux/interrupt.h>
14 #include <linux/of_gpio.h>
15 #include <linux/platform_device.h>
16 #include <linux/reset.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/workqueue.h>
20 #include <drm/drm_dp_helper.h>
21 #include <drm/drm_panel.h>
26 static DEFINE_MUTEX(dpaux_lock);
27 static LIST_HEAD(dpaux_list);
30 struct drm_dp_aux aux;
36 struct tegra_output *output;
38 struct reset_control *rst;
39 struct clk *clk_parent;
42 struct regulator *vdd;
44 struct completion complete;
45 struct work_struct work;
46 struct list_head list;
49 static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux)
51 return container_of(aux, struct tegra_dpaux, aux);
54 static inline struct tegra_dpaux *work_to_dpaux(struct work_struct *work)
56 return container_of(work, struct tegra_dpaux, work);
59 static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux,
62 return readl(dpaux->regs + (offset << 2));
65 static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,
66 u32 value, unsigned long offset)
68 writel(value, dpaux->regs + (offset << 2));
71 static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,
76 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
77 size_t num = min_t(size_t, size - i * 4, 4);
80 for (j = 0; j < num; j++)
81 value |= buffer[i * 4 + j] << (j * 8);
83 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i));
87 static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,
92 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
93 size_t num = min_t(size_t, size - i * 4, 4);
96 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i));
98 for (j = 0; j < num; j++)
99 buffer[i * 4 + j] = value >> (j * 8);
103 static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux,
104 struct drm_dp_aux_msg *msg)
106 unsigned long timeout = msecs_to_jiffies(250);
107 struct tegra_dpaux *dpaux = to_dpaux(aux);
108 unsigned long status;
112 /* Tegra has 4x4 byte DP AUX transmit and receive FIFOs. */
117 * Allow zero-sized messages only for I2C, in which case they specify
118 * address-only transactions.
121 switch (msg->request & ~DP_AUX_I2C_MOT) {
122 case DP_AUX_I2C_WRITE:
123 case DP_AUX_I2C_READ:
124 value = DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY;
131 /* For non-zero-sized messages, set the CMDLEN field. */
132 value = DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1);
135 switch (msg->request & ~DP_AUX_I2C_MOT) {
136 case DP_AUX_I2C_WRITE:
137 if (msg->request & DP_AUX_I2C_MOT)
138 value |= DPAUX_DP_AUXCTL_CMD_MOT_WR;
140 value |= DPAUX_DP_AUXCTL_CMD_I2C_WR;
144 case DP_AUX_I2C_READ:
145 if (msg->request & DP_AUX_I2C_MOT)
146 value |= DPAUX_DP_AUXCTL_CMD_MOT_RD;
148 value |= DPAUX_DP_AUXCTL_CMD_I2C_RD;
152 case DP_AUX_I2C_STATUS:
153 if (msg->request & DP_AUX_I2C_MOT)
154 value |= DPAUX_DP_AUXCTL_CMD_MOT_RQ;
156 value |= DPAUX_DP_AUXCTL_CMD_I2C_RQ;
160 case DP_AUX_NATIVE_WRITE:
161 value |= DPAUX_DP_AUXCTL_CMD_AUX_WR;
164 case DP_AUX_NATIVE_READ:
165 value |= DPAUX_DP_AUXCTL_CMD_AUX_RD;
172 tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR);
173 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
175 if ((msg->request & DP_AUX_I2C_READ) == 0) {
176 tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size);
180 /* start transaction */
181 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);
182 value |= DPAUX_DP_AUXCTL_TRANSACTREQ;
183 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
185 status = wait_for_completion_timeout(&dpaux->complete, timeout);
189 /* read status and clear errors */
190 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
191 tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT);
193 if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR)
196 if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) ||
197 (value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) ||
198 (value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR))
201 switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) {
203 msg->reply = DP_AUX_NATIVE_REPLY_ACK;
207 msg->reply = DP_AUX_NATIVE_REPLY_NACK;
211 msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
215 msg->reply = DP_AUX_I2C_REPLY_NACK;
219 msg->reply = DP_AUX_I2C_REPLY_DEFER;
223 if ((msg->size > 0) && (msg->reply == DP_AUX_NATIVE_REPLY_ACK)) {
224 if (msg->request & DP_AUX_I2C_READ) {
225 size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK;
227 if (WARN_ON(count != msg->size))
228 count = min_t(size_t, count, msg->size);
230 tegra_dpaux_read_fifo(dpaux, msg->buffer, count);
238 static void tegra_dpaux_hotplug(struct work_struct *work)
240 struct tegra_dpaux *dpaux = work_to_dpaux(work);
243 drm_helper_hpd_irq_event(dpaux->output->connector.dev);
246 static irqreturn_t tegra_dpaux_irq(int irq, void *data)
248 struct tegra_dpaux *dpaux = data;
249 irqreturn_t ret = IRQ_HANDLED;
252 /* clear interrupts */
253 value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);
254 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
256 if (value & (DPAUX_INTR_PLUG_EVENT | DPAUX_INTR_UNPLUG_EVENT))
257 schedule_work(&dpaux->work);
259 if (value & DPAUX_INTR_IRQ_EVENT) {
260 /* TODO: handle this */
263 if (value & DPAUX_INTR_AUX_DONE)
264 complete(&dpaux->complete);
269 static int tegra_dpaux_probe(struct platform_device *pdev)
271 struct tegra_dpaux *dpaux;
272 struct resource *regs;
276 dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL);
280 INIT_WORK(&dpaux->work, tegra_dpaux_hotplug);
281 init_completion(&dpaux->complete);
282 INIT_LIST_HEAD(&dpaux->list);
283 dpaux->dev = &pdev->dev;
285 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
286 dpaux->regs = devm_ioremap_resource(&pdev->dev, regs);
287 if (IS_ERR(dpaux->regs))
288 return PTR_ERR(dpaux->regs);
290 dpaux->irq = platform_get_irq(pdev, 0);
291 if (dpaux->irq < 0) {
292 dev_err(&pdev->dev, "failed to get IRQ\n");
296 dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
297 if (IS_ERR(dpaux->rst)) {
298 dev_err(&pdev->dev, "failed to get reset control: %ld\n",
299 PTR_ERR(dpaux->rst));
300 return PTR_ERR(dpaux->rst);
303 dpaux->clk = devm_clk_get(&pdev->dev, NULL);
304 if (IS_ERR(dpaux->clk)) {
305 dev_err(&pdev->dev, "failed to get module clock: %ld\n",
306 PTR_ERR(dpaux->clk));
307 return PTR_ERR(dpaux->clk);
310 err = clk_prepare_enable(dpaux->clk);
312 dev_err(&pdev->dev, "failed to enable module clock: %d\n",
317 reset_control_deassert(dpaux->rst);
319 dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
320 if (IS_ERR(dpaux->clk_parent)) {
321 dev_err(&pdev->dev, "failed to get parent clock: %ld\n",
322 PTR_ERR(dpaux->clk_parent));
323 return PTR_ERR(dpaux->clk_parent);
326 err = clk_prepare_enable(dpaux->clk_parent);
328 dev_err(&pdev->dev, "failed to enable parent clock: %d\n",
333 err = clk_set_rate(dpaux->clk_parent, 270000000);
335 dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n",
340 dpaux->vdd = devm_regulator_get(&pdev->dev, "vdd");
341 if (IS_ERR(dpaux->vdd)) {
342 dev_err(&pdev->dev, "failed to get VDD supply: %ld\n",
343 PTR_ERR(dpaux->vdd));
344 return PTR_ERR(dpaux->vdd);
347 err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
348 dev_name(dpaux->dev), dpaux);
350 dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",
355 disable_irq(dpaux->irq);
357 dpaux->aux.transfer = tegra_dpaux_transfer;
358 dpaux->aux.dev = &pdev->dev;
360 err = drm_dp_aux_register(&dpaux->aux);
365 * Assume that by default the DPAUX/I2C pads will be used for HDMI,
366 * so power them up and configure them in I2C mode.
368 * The DPAUX code paths reconfigure the pads in AUX mode, but there
369 * is no possibility to perform the I2C mode configuration in the
372 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
373 value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
374 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
376 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_PADCTL);
377 value = DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV |
378 DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
379 DPAUX_HYBRID_PADCTL_MODE_I2C;
380 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
382 /* enable and clear all interrupts */
383 value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT |
384 DPAUX_INTR_UNPLUG_EVENT | DPAUX_INTR_PLUG_EVENT;
385 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);
386 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
388 mutex_lock(&dpaux_lock);
389 list_add_tail(&dpaux->list, &dpaux_list);
390 mutex_unlock(&dpaux_lock);
392 platform_set_drvdata(pdev, dpaux);
397 static int tegra_dpaux_remove(struct platform_device *pdev)
399 struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);
402 /* make sure pads are powered down when not in use */
403 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
404 value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
405 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
407 drm_dp_aux_unregister(&dpaux->aux);
409 mutex_lock(&dpaux_lock);
410 list_del(&dpaux->list);
411 mutex_unlock(&dpaux_lock);
413 cancel_work_sync(&dpaux->work);
415 clk_disable_unprepare(dpaux->clk_parent);
416 reset_control_assert(dpaux->rst);
417 clk_disable_unprepare(dpaux->clk);
422 static const struct of_device_id tegra_dpaux_of_match[] = {
423 { .compatible = "nvidia,tegra210-dpaux", },
424 { .compatible = "nvidia,tegra124-dpaux", },
427 MODULE_DEVICE_TABLE(of, tegra_dpaux_of_match);
429 struct platform_driver tegra_dpaux_driver = {
431 .name = "tegra-dpaux",
432 .of_match_table = tegra_dpaux_of_match,
434 .probe = tegra_dpaux_probe,
435 .remove = tegra_dpaux_remove,
438 struct tegra_dpaux *tegra_dpaux_find_by_of_node(struct device_node *np)
440 struct tegra_dpaux *dpaux;
442 mutex_lock(&dpaux_lock);
444 list_for_each_entry(dpaux, &dpaux_list, list)
445 if (np == dpaux->dev->of_node) {
446 mutex_unlock(&dpaux_lock);
450 mutex_unlock(&dpaux_lock);
455 int tegra_dpaux_attach(struct tegra_dpaux *dpaux, struct tegra_output *output)
457 unsigned long timeout;
460 output->connector.polled = DRM_CONNECTOR_POLL_HPD;
461 dpaux->output = output;
463 err = regulator_enable(dpaux->vdd);
467 timeout = jiffies + msecs_to_jiffies(250);
469 while (time_before(jiffies, timeout)) {
470 enum drm_connector_status status;
472 status = tegra_dpaux_detect(dpaux);
473 if (status == connector_status_connected) {
474 enable_irq(dpaux->irq);
478 usleep_range(1000, 2000);
484 int tegra_dpaux_detach(struct tegra_dpaux *dpaux)
486 unsigned long timeout;
489 disable_irq(dpaux->irq);
491 err = regulator_disable(dpaux->vdd);
495 timeout = jiffies + msecs_to_jiffies(250);
497 while (time_before(jiffies, timeout)) {
498 enum drm_connector_status status;
500 status = tegra_dpaux_detect(dpaux);
501 if (status == connector_status_disconnected) {
502 dpaux->output = NULL;
506 usleep_range(1000, 2000);
512 enum drm_connector_status tegra_dpaux_detect(struct tegra_dpaux *dpaux)
516 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
518 if (value & DPAUX_DP_AUXSTAT_HPD_STATUS)
519 return connector_status_connected;
521 return connector_status_disconnected;
524 int tegra_dpaux_enable(struct tegra_dpaux *dpaux)
528 value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
529 DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
530 DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
531 DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV |
532 DPAUX_HYBRID_PADCTL_MODE_AUX;
533 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
535 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
536 value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
537 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
542 int tegra_dpaux_disable(struct tegra_dpaux *dpaux)
546 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
547 value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
548 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
553 int tegra_dpaux_prepare(struct tegra_dpaux *dpaux, u8 encoding)
557 err = drm_dp_dpcd_writeb(&dpaux->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
565 int tegra_dpaux_train(struct tegra_dpaux *dpaux, struct drm_dp_link *link,
568 u8 tp = pattern & DP_TRAINING_PATTERN_MASK;
569 u8 status[DP_LINK_STATUS_SIZE], values[4];
573 err = drm_dp_dpcd_writeb(&dpaux->aux, DP_TRAINING_PATTERN_SET, pattern);
577 if (tp == DP_TRAINING_PATTERN_DISABLE)
580 for (i = 0; i < link->num_lanes; i++)
581 values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED |
582 DP_TRAIN_PRE_EMPH_LEVEL_0 |
583 DP_TRAIN_MAX_SWING_REACHED |
584 DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
586 err = drm_dp_dpcd_write(&dpaux->aux, DP_TRAINING_LANE0_SET, values,
591 usleep_range(500, 1000);
593 err = drm_dp_dpcd_read_link_status(&dpaux->aux, status);
598 case DP_TRAINING_PATTERN_1:
599 if (!drm_dp_clock_recovery_ok(status, link->num_lanes))
604 case DP_TRAINING_PATTERN_2:
605 if (!drm_dp_channel_eq_ok(status, link->num_lanes))
611 dev_err(dpaux->dev, "unsupported training pattern %u\n", tp);
615 err = drm_dp_dpcd_writeb(&dpaux->aux, DP_EDP_CONFIGURATION_SET, 0);