drivers/gpu/drm/tegra/dc.c

   1 /*
   2  * Copyright (C) 2012 Avionic Design GmbH
   3  * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/debugfs.h>
  12 #include <linux/iommu.h>
  13 #include <linux/reset.h>
  14
  15 #include <soc/tegra/pmc.h>
  16
  17 #include "dc.h"
  18 #include "drm.h"
  19 #include "gem.h"
  20
  21 #include <drm/drm_atomic.h>
  22 #include <drm/drm_atomic_helper.h>
  23 #include <drm/drm_plane_helper.h>
  24
  25 struct tegra_dc_soc_info {
  26         bool supports_border_color;
  27         bool supports_interlacing;
  28         bool supports_cursor;
  29         bool supports_block_linear;
  30         unsigned int pitch_align;
  31         bool has_powergate;
  32 };
  33
  34 struct tegra_plane {
  35         struct drm_plane base;
  36         unsigned int index;
  37 };
  38
  39 static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
  40 {
  41         return container_of(plane, struct tegra_plane, base);
  42 }
  43
  44 struct tegra_dc_state {
  45         struct drm_crtc_state base;
  46
  47         struct clk *clk;
  48         unsigned long pclk;
  49         unsigned int div;
  50
  51         u32 planes;
  52 };
  53
  54 static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state)
  55 {
  56         if (state)
  57                 return container_of(state, struct tegra_dc_state, base);
  58
  59         return NULL;
  60 }
  61
  62 struct tegra_plane_state {
  63         struct drm_plane_state base;
  64
  65         struct tegra_bo_tiling tiling;
  66         u32 format;
  67         u32 swap;
  68 };
  69
  70 static inline struct tegra_plane_state *
  71 to_tegra_plane_state(struct drm_plane_state *state)
  72 {
  73         if (state)
  74                 return container_of(state, struct tegra_plane_state, base);
  75
  76         return NULL;
  77 }
  78
  79 /*
  80  * Reads the active copy of a register. This takes the dc->lock spinlock to
  81  * prevent races with the VBLANK processing which also needs access to the
  82  * active copy of some registers.
  83  */
  84 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
  85 {
  86         unsigned long flags;
  87         u32 value;
  88
  89         spin_lock_irqsave(&dc->lock, flags);
  90
  91         tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
  92         value = tegra_dc_readl(dc, offset);
  93         tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
  94
  95         spin_unlock_irqrestore(&dc->lock, flags);
  96         return value;
  97 }
  98
  99 /*
 100  * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
 101  * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
 102  * Latching happens mmediately if the display controller is in STOP mode or
 103  * on the next frame boundary otherwise.
 104  *
 105  * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
 106  * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
 107  * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
 108  * into the ACTIVE copy, either immediately if the display controller is in
 109  * STOP mode, or at the next frame boundary otherwise.
 110  */
 111 void tegra_dc_commit(struct tegra_dc *dc)
 112 {
 113         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
 114         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
 115 }
 116
 117 static int tegra_dc_format(u32 fourcc, u32 *format, u32 *swap)
 118 {
 119         /* assume no swapping of fetched data */
 120         if (swap)
 121                 *swap = BYTE_SWAP_NOSWAP;
 122
 123         switch (fourcc) {
 124         case DRM_FORMAT_XBGR8888:
 125                 *format = WIN_COLOR_DEPTH_R8G8B8A8;
 126                 break;
 127
 128         case DRM_FORMAT_XRGB8888:
 129                 *format = WIN_COLOR_DEPTH_B8G8R8A8;
 130                 break;
 131
 132         case DRM_FORMAT_RGB565:
 133                 *format = WIN_COLOR_DEPTH_B5G6R5;
 134                 break;
 135
 136         case DRM_FORMAT_UYVY:
 137                 *format = WIN_COLOR_DEPTH_YCbCr422;
 138                 break;
 139
 140         case DRM_FORMAT_YUYV:
 141                 if (swap)
 142                         *swap = BYTE_SWAP_SWAP2;
 143
 144                 *format = WIN_COLOR_DEPTH_YCbCr422;
 145                 break;
 146
 147         case DRM_FORMAT_YUV420:
 148                 *format = WIN_COLOR_DEPTH_YCbCr420P;
 149                 break;
 150
 151         case DRM_FORMAT_YUV422:
 152                 *format = WIN_COLOR_DEPTH_YCbCr422P;
 153                 break;
 154
 155         default:
 156                 return -EINVAL;
 157         }
 158
 159         return 0;
 160 }
 161
 162 static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
 163 {
 164         switch (format) {
 165         case WIN_COLOR_DEPTH_YCbCr422:
 166         case WIN_COLOR_DEPTH_YUV422:
 167                 if (planar)
 168                         *planar = false;
 169
 170                 return true;
 171
 172         case WIN_COLOR_DEPTH_YCbCr420P:
 173         case WIN_COLOR_DEPTH_YUV420P:
 174         case WIN_COLOR_DEPTH_YCbCr422P:
 175         case WIN_COLOR_DEPTH_YUV422P:
 176         case WIN_COLOR_DEPTH_YCbCr422R:
 177         case WIN_COLOR_DEPTH_YUV422R:
 178         case WIN_COLOR_DEPTH_YCbCr422RA:
 179         case WIN_COLOR_DEPTH_YUV422RA:
 180                 if (planar)
 181                         *planar = true;
 182
 183                 return true;
 184         }
 185
 186         if (planar)
 187                 *planar = false;
 188
 189         return false;
 190 }
 191
 192 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
 193                                   unsigned int bpp)
 194 {
 195         fixed20_12 outf = dfixed_init(out);
 196         fixed20_12 inf = dfixed_init(in);
 197         u32 dda_inc;
 198         int max;
 199
 200         if (v)
 201                 max = 15;
 202         else {
 203                 switch (bpp) {
 204                 case 2:
 205                         max = 8;
 206                         break;
 207
 208                 default:
 209                         WARN_ON_ONCE(1);
 210                         /* fallthrough */
 211                 case 4:
 212                         max = 4;
 213                         break;
 214                 }
 215         }
 216
 217         outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
 218         inf.full -= dfixed_const(1);
 219
 220         dda_inc = dfixed_div(inf, outf);
 221         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
 222
 223         return dda_inc;
 224 }
 225
 226 static inline u32 compute_initial_dda(unsigned int in)
 227 {
 228         fixed20_12 inf = dfixed_init(in);
 229         return dfixed_frac(inf);
 230 }
 231
 232 static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
 233                                   const struct tegra_dc_window *window)
 234 {
 235         unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
 236         unsigned long value, flags;
 237         bool yuv, planar;
 238
 239         /*
 240          * For YUV planar modes, the number of bytes per pixel takes into
 241          * account only the luma component and therefore is 1.
 242          */
 243         yuv = tegra_dc_format_is_yuv(window->format, &planar);
 244         if (!yuv)
 245                 bpp = window->bits_per_pixel / 8;
 246         else
 247                 bpp = planar ? 1 : 2;
 248
 249         spin_lock_irqsave(&dc->lock, flags);
 250
 251         value = WINDOW_A_SELECT << index;
 252         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
 253
 254         tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
 255         tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
 256
 257         value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
 258         tegra_dc_writel(dc, value, DC_WIN_POSITION);
 259
 260         value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
 261         tegra_dc_writel(dc, value, DC_WIN_SIZE);
 262
 263         h_offset = window->src.x * bpp;
 264         v_offset = window->src.y;
 265         h_size = window->src.w * bpp;
 266         v_size = window->src.h;
 267
 268         value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
 269         tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
 270
 271         /*
 272          * For DDA computations the number of bytes per pixel for YUV planar
 273          * modes needs to take into account all Y, U and V components.
 274          */
 275         if (yuv && planar)
 276                 bpp = 2;
 277
 278         h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
 279         v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
 280
 281         value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
 282         tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
 283
 284         h_dda = compute_initial_dda(window->src.x);
 285         v_dda = compute_initial_dda(window->src.y);
 286
 287         tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
 288         tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
 289
 290         tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
 291         tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
 292
 293         tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
 294
 295         if (yuv && planar) {
 296                 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
 297                 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
 298                 value = window->stride[1] << 16 | window->stride[0];
 299                 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
 300         } else {
 301                 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
 302         }
 303
 304         if (window->bottom_up)
 305                 v_offset += window->src.h - 1;
 306
 307         tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
 308         tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
 309
 310         if (dc->soc->supports_block_linear) {
 311                 unsigned long height = window->tiling.value;
 312
 313                 switch (window->tiling.mode) {
 314                 case TEGRA_BO_TILING_MODE_PITCH:
 315                         value = DC_WINBUF_SURFACE_KIND_PITCH;
 316                         break;
 317
 318                 case TEGRA_BO_TILING_MODE_TILED:
 319                         value = DC_WINBUF_SURFACE_KIND_TILED;
 320                         break;
 321
 322                 case TEGRA_BO_TILING_MODE_BLOCK:
 323                         value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
 324                                 DC_WINBUF_SURFACE_KIND_BLOCK;
 325                         break;
 326                 }
 327
 328                 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
 329         } else {
 330                 switch (window->tiling.mode) {
 331                 case TEGRA_BO_TILING_MODE_PITCH:
 332                         value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
 333                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
 334                         break;
 335
 336                 case TEGRA_BO_TILING_MODE_TILED:
 337                         value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
 338                                 DC_WIN_BUFFER_ADDR_MODE_TILE;
 339                         break;
 340
 341                 case TEGRA_BO_TILING_MODE_BLOCK:
 342                         /*
 343                          * No need to handle this here because ->atomic_check
 344                          * will already have filtered it out.
 345                          */
 346                         break;
 347                 }
 348
 349                 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
 350         }
 351
 352         value = WIN_ENABLE;
 353
 354         if (yuv) {
 355                 /* setup default colorspace conversion coefficients */
 356                 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
 357                 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
 358                 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
 359                 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
 360                 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
 361                 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
 362                 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
 363                 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
 364
 365                 value |= CSC_ENABLE;
 366         } else if (window->bits_per_pixel < 24) {
 367                 value |= COLOR_EXPAND;
 368         }
 369
 370         if (window->bottom_up)
 371                 value |= V_DIRECTION;
 372
 373         tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
 374
 375         /*
 376          * Disable blending and assume Window A is the bottom-most window,
 377          * Window C is the top-most window and Window B is in the middle.
 378          */
 379         tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
 380         tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
 381
 382         switch (index) {
 383         case 0:
 384                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
 385                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
 386                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
 387                 break;
 388
 389         case 1:
 390                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
 391                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
 392                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
 393                 break;
 394
 395         case 2:
 396                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
 397                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
 398                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
 399                 break;
 400         }
 401
 402         spin_unlock_irqrestore(&dc->lock, flags);
 403 }
 404
 405 static void tegra_plane_destroy(struct drm_plane *plane)
 406 {
 407         struct tegra_plane *p = to_tegra_plane(plane);
 408
 409         drm_plane_cleanup(plane);
 410         kfree(p);
 411 }
 412
 413 static const u32 tegra_primary_plane_formats[] = {
 414         DRM_FORMAT_XBGR8888,
 415         DRM_FORMAT_XRGB8888,
 416         DRM_FORMAT_RGB565,
 417 };
 418
 419 static void tegra_primary_plane_destroy(struct drm_plane *plane)
 420 {
 421         tegra_plane_destroy(plane);
 422 }
 423
 424 static void tegra_plane_reset(struct drm_plane *plane)
 425 {
 426         struct tegra_plane_state *state;
 427
 428         if (plane->state)
 429                 __drm_atomic_helper_plane_destroy_state(plane, plane->state);
 430
 431         kfree(plane->state);
 432         plane->state = NULL;
 433
 434         state = kzalloc(sizeof(*state), GFP_KERNEL);
 435         if (state) {
 436                 plane->state = &state->base;
 437                 plane->state->plane = plane;
 438         }
 439 }
 440
 441 static struct drm_plane_state *tegra_plane_atomic_duplicate_state(struct drm_plane *plane)
 442 {
 443         struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
 444         struct tegra_plane_state *copy;
 445
 446         copy = kmalloc(sizeof(*copy), GFP_KERNEL);
 447         if (!copy)
 448                 return NULL;
 449
 450         __drm_atomic_helper_plane_duplicate_state(plane, &copy->base);
 451         copy->tiling = state->tiling;
 452         copy->format = state->format;
 453         copy->swap = state->swap;
 454
 455         return &copy->base;
 456 }
 457
 458 static void tegra_plane_atomic_destroy_state(struct drm_plane *plane,
 459                                              struct drm_plane_state *state)
 460 {
 461         __drm_atomic_helper_plane_destroy_state(plane, state);
 462         kfree(state);
 463 }
 464
 465 static const struct drm_plane_funcs tegra_primary_plane_funcs = {
 466         .update_plane = drm_atomic_helper_update_plane,
 467         .disable_plane = drm_atomic_helper_disable_plane,
 468         .destroy = tegra_primary_plane_destroy,
 469         .reset = tegra_plane_reset,
 470         .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
 471         .atomic_destroy_state = tegra_plane_atomic_destroy_state,
 472 };
 473
 474 static int tegra_plane_prepare_fb(struct drm_plane *plane,
 475                                   struct drm_framebuffer *fb,
 476                                   const struct drm_plane_state *new_state)
 477 {
 478         return 0;
 479 }
 480
 481 static void tegra_plane_cleanup_fb(struct drm_plane *plane,
 482                                    struct drm_framebuffer *fb,
 483                                    const struct drm_plane_state *old_fb)
 484 {
 485 }
 486
 487 static int tegra_plane_state_add(struct tegra_plane *plane,
 488                                  struct drm_plane_state *state)
 489 {
 490         struct drm_crtc_state *crtc_state;
 491         struct tegra_dc_state *tegra;
 492
 493         /* Propagate errors from allocation or locking failures. */
 494         crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
 495         if (IS_ERR(crtc_state))
 496                 return PTR_ERR(crtc_state);
 497
 498         tegra = to_dc_state(crtc_state);
 499
 500         tegra->planes |= WIN_A_ACT_REQ << plane->index;
 501
 502         return 0;
 503 }
 504
 505 static int tegra_plane_atomic_check(struct drm_plane *plane,
 506                                     struct drm_plane_state *state)
 507 {
 508         struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
 509         struct tegra_bo_tiling *tiling = &plane_state->tiling;
 510         struct tegra_plane *tegra = to_tegra_plane(plane);
 511         struct tegra_dc *dc = to_tegra_dc(state->crtc);
 512         int err;
 513
 514         /* no need for further checks if the plane is being disabled */
 515         if (!state->crtc)
 516                 return 0;
 517
 518         err = tegra_dc_format(state->fb->pixel_format, &plane_state->format,
 519                               &plane_state->swap);
 520         if (err < 0)
 521                 return err;
 522
 523         err = tegra_fb_get_tiling(state->fb, tiling);
 524         if (err < 0)
 525                 return err;
 526
 527         if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
 528             !dc->soc->supports_block_linear) {
 529                 DRM_ERROR("hardware doesn't support block linear mode\n");
 530                 return -EINVAL;
 531         }
 532
 533         /*
 534          * Tegra doesn't support different strides for U and V planes so we
 535          * error out if the user tries to display a framebuffer with such a
 536          * configuration.
 537          */
 538         if (drm_format_num_planes(state->fb->pixel_format) > 2) {
 539                 if (state->fb->pitches[2] != state->fb->pitches[1]) {
 540                         DRM_ERROR("unsupported UV-plane configuration\n");
 541                         return -EINVAL;
 542                 }
 543         }
 544
 545         err = tegra_plane_state_add(tegra, state);
 546         if (err < 0)
 547                 return err;
 548
 549         return 0;
 550 }
 551
 552 static void tegra_plane_atomic_update(struct drm_plane *plane,
 553                                       struct drm_plane_state *old_state)
 554 {
 555         struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
 556         struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
 557         struct drm_framebuffer *fb = plane->state->fb;
 558         struct tegra_plane *p = to_tegra_plane(plane);
 559         struct tegra_dc_window window;
 560         unsigned int i;
 561
 562         /* rien ne va plus */
 563         if (!plane->state->crtc || !plane->state->fb)
 564                 return;
 565
 566         memset(&window, 0, sizeof(window));
 567         window.src.x = plane->state->src_x >> 16;
 568         window.src.y = plane->state->src_y >> 16;
 569         window.src.w = plane->state->src_w >> 16;
 570         window.src.h = plane->state->src_h >> 16;
 571         window.dst.x = plane->state->crtc_x;
 572         window.dst.y = plane->state->crtc_y;
 573         window.dst.w = plane->state->crtc_w;
 574         window.dst.h = plane->state->crtc_h;
 575         window.bits_per_pixel = fb->bits_per_pixel;
 576         window.bottom_up = tegra_fb_is_bottom_up(fb);
 577
 578         /* copy from state */
 579         window.tiling = state->tiling;
 580         window.format = state->format;
 581         window.swap = state->swap;
 582
 583         for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
 584                 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
 585
 586                 window.base[i] = bo->paddr + fb->offsets[i];
 587                 window.stride[i] = fb->pitches[i];
 588         }
 589
 590         tegra_dc_setup_window(dc, p->index, &window);
 591 }
 592
 593 static void tegra_plane_atomic_disable(struct drm_plane *plane,
 594                                        struct drm_plane_state *old_state)
 595 {
 596         struct tegra_plane *p = to_tegra_plane(plane);
 597         struct tegra_dc *dc;
 598         unsigned long flags;
 599         u32 value;
 600
 601         /* rien ne va plus */
 602         if (!old_state || !old_state->crtc)
 603                 return;
 604
 605         dc = to_tegra_dc(old_state->crtc);
 606
 607         spin_lock_irqsave(&dc->lock, flags);
 608
 609         value = WINDOW_A_SELECT << p->index;
 610         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
 611
 612         value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
 613         value &= ~WIN_ENABLE;
 614         tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
 615
 616         spin_unlock_irqrestore(&dc->lock, flags);
 617 }
 618
 619 static const struct drm_plane_helper_funcs tegra_primary_plane_helper_funcs = {
 620         .prepare_fb = tegra_plane_prepare_fb,
 621         .cleanup_fb = tegra_plane_cleanup_fb,
 622         .atomic_check = tegra_plane_atomic_check,
 623         .atomic_update = tegra_plane_atomic_update,
 624         .atomic_disable = tegra_plane_atomic_disable,
 625 };
 626
 627 static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm,
 628                                                        struct tegra_dc *dc)
 629 {
 630         /*
 631          * Ideally this would use drm_crtc_mask(), but that would require the
 632          * CRTC to already be in the mode_config's list of CRTCs. However, it
 633          * will only be added to that list in the drm_crtc_init_with_planes()
 634          * (in tegra_dc_init()), which in turn requires registration of these
 635          * planes. So we have ourselves a nice little chicken and egg problem
 636          * here.
 637          *
 638          * We work around this by manually creating the mask from the number
 639          * of CRTCs that have been registered, and should therefore always be
 640          * the same as drm_crtc_index() after registration.
 641          */
 642         unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc;
 643         struct tegra_plane *plane;
 644         unsigned int num_formats;
 645         const u32 *formats;
 646         int err;
 647
 648         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 649         if (!plane)
 650                 return ERR_PTR(-ENOMEM);
 651
 652         num_formats = ARRAY_SIZE(tegra_primary_plane_formats);
 653         formats = tegra_primary_plane_formats;
 654
 655         err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
 656                                        &tegra_primary_plane_funcs, formats,
 657                                        num_formats, DRM_PLANE_TYPE_PRIMARY);
 658         if (err < 0) {
 659                 kfree(plane);
 660                 return ERR_PTR(err);
 661         }
 662
 663         drm_plane_helper_add(&plane->base, &tegra_primary_plane_helper_funcs);
 664
 665         return &plane->base;
 666 }
 667
 668 static const u32 tegra_cursor_plane_formats[] = {
 669         DRM_FORMAT_RGBA8888,
 670 };
 671
 672 static int tegra_cursor_atomic_check(struct drm_plane *plane,
 673                                      struct drm_plane_state *state)
 674 {
 675         struct tegra_plane *tegra = to_tegra_plane(plane);
 676         int err;
 677
 678         /* no need for further checks if the plane is being disabled */
 679         if (!state->crtc)
 680                 return 0;
 681
 682         /* scaling not supported for cursor */
 683         if ((state->src_w >> 16 != state->crtc_w) ||
 684             (state->src_h >> 16 != state->crtc_h))
 685                 return -EINVAL;
 686
 687         /* only square cursors supported */
 688         if (state->src_w != state->src_h)
 689                 return -EINVAL;
 690
 691         if (state->crtc_w != 32 && state->crtc_w != 64 &&
 692             state->crtc_w != 128 && state->crtc_w != 256)
 693                 return -EINVAL;
 694
 695         err = tegra_plane_state_add(tegra, state);
 696         if (err < 0)
 697                 return err;
 698
 699         return 0;
 700 }
 701
 702 static void tegra_cursor_atomic_update(struct drm_plane *plane,
 703                                        struct drm_plane_state *old_state)
 704 {
 705         struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0);
 706         struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
 707         struct drm_plane_state *state = plane->state;
 708         u32 value = CURSOR_CLIP_DISPLAY;
 709
 710         /* rien ne va plus */
 711         if (!plane->state->crtc || !plane->state->fb)
 712                 return;
 713
 714         switch (state->crtc_w) {
 715         case 32:
 716                 value |= CURSOR_SIZE_32x32;
 717                 break;
 718
 719         case 64:
 720                 value |= CURSOR_SIZE_64x64;
 721                 break;
 722
 723         case 128:
 724                 value |= CURSOR_SIZE_128x128;
 725                 break;
 726
 727         case 256:
 728                 value |= CURSOR_SIZE_256x256;
 729                 break;
 730
 731         default:
 732                 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w,
 733                      state->crtc_h);
 734                 return;
 735         }
 736
 737         value |= (bo->paddr >> 10) & 0x3fffff;
 738         tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
 739
 740 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
 741         value = (bo->paddr >> 32) & 0x3;
 742         tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
 743 #endif
 744
 745         /* enable cursor and set blend mode */
 746         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
 747         value |= CURSOR_ENABLE;
 748         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
 749
 750         value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
 751         value &= ~CURSOR_DST_BLEND_MASK;
 752         value &= ~CURSOR_SRC_BLEND_MASK;
 753         value |= CURSOR_MODE_NORMAL;
 754         value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
 755         value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
 756         value |= CURSOR_ALPHA;
 757         tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
 758
 759         /* position the cursor */
 760         value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);
 761         tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
 762 }
 763
 764 static void tegra_cursor_atomic_disable(struct drm_plane *plane,
 765                                         struct drm_plane_state *old_state)
 766 {
 767         struct tegra_dc *dc;
 768         u32 value;
 769
 770         /* rien ne va plus */
 771         if (!old_state || !old_state->crtc)
 772                 return;
 773
 774         dc = to_tegra_dc(old_state->crtc);
 775
 776         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
 777         value &= ~CURSOR_ENABLE;
 778         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
 779 }
 780
 781 static const struct drm_plane_funcs tegra_cursor_plane_funcs = {
 782         .update_plane = drm_atomic_helper_update_plane,
 783         .disable_plane = drm_atomic_helper_disable_plane,
 784         .destroy = tegra_plane_destroy,
 785         .reset = tegra_plane_reset,
 786         .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
 787         .atomic_destroy_state = tegra_plane_atomic_destroy_state,
 788 };
 789
 790 static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
 791         .prepare_fb = tegra_plane_prepare_fb,
 792         .cleanup_fb = tegra_plane_cleanup_fb,
 793         .atomic_check = tegra_cursor_atomic_check,
 794         .atomic_update = tegra_cursor_atomic_update,
 795         .atomic_disable = tegra_cursor_atomic_disable,
 796 };
 797
 798 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
 799                                                       struct tegra_dc *dc)
 800 {
 801         struct tegra_plane *plane;
 802         unsigned int num_formats;
 803         const u32 *formats;
 804         int err;
 805
 806         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 807         if (!plane)
 808                 return ERR_PTR(-ENOMEM);
 809
 810         /*
 811          * This index is kind of fake. The cursor isn't a regular plane, but
 812          * its update and activation request bits in DC_CMD_STATE_CONTROL do
 813          * use the same programming. Setting this fake index here allows the
 814          * code in tegra_add_plane_state() to do the right thing without the
 815          * need to special-casing the cursor plane.
 816          */
 817         plane->index = 6;
 818
 819         num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
 820         formats = tegra_cursor_plane_formats;
 821
 822         err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
 823                                        &tegra_cursor_plane_funcs, formats,
 824                                        num_formats, DRM_PLANE_TYPE_CURSOR);
 825         if (err < 0) {
 826                 kfree(plane);
 827                 return ERR_PTR(err);
 828         }
 829
 830         drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
 831
 832         return &plane->base;
 833 }
 834
 835 static void tegra_overlay_plane_destroy(struct drm_plane *plane)
 836 {
 837         tegra_plane_destroy(plane);
 838 }
 839
 840 static const struct drm_plane_funcs tegra_overlay_plane_funcs = {
 841         .update_plane = drm_atomic_helper_update_plane,
 842         .disable_plane = drm_atomic_helper_disable_plane,
 843         .destroy = tegra_overlay_plane_destroy,
 844         .reset = tegra_plane_reset,
 845         .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
 846         .atomic_destroy_state = tegra_plane_atomic_destroy_state,
 847 };
 848
 849 static const uint32_t tegra_overlay_plane_formats[] = {
 850         DRM_FORMAT_XBGR8888,
 851         DRM_FORMAT_XRGB8888,
 852         DRM_FORMAT_RGB565,
 853         DRM_FORMAT_UYVY,
 854         DRM_FORMAT_YUYV,
 855         DRM_FORMAT_YUV420,
 856         DRM_FORMAT_YUV422,
 857 };
 858
 859 static const struct drm_plane_helper_funcs tegra_overlay_plane_helper_funcs = {
 860         .prepare_fb = tegra_plane_prepare_fb,
 861         .cleanup_fb = tegra_plane_cleanup_fb,
 862         .atomic_check = tegra_plane_atomic_check,
 863         .atomic_update = tegra_plane_atomic_update,
 864         .atomic_disable = tegra_plane_atomic_disable,
 865 };
 866
 867 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
 868                                                        struct tegra_dc *dc,
 869                                                        unsigned int index)
 870 {
 871         struct tegra_plane *plane;
 872         unsigned int num_formats;
 873         const u32 *formats;
 874         int err;
 875
 876         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 877         if (!plane)
 878                 return ERR_PTR(-ENOMEM);
 879
 880         plane->index = index;
 881
 882         num_formats = ARRAY_SIZE(tegra_overlay_plane_formats);
 883         formats = tegra_overlay_plane_formats;
 884
 885         err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
 886                                        &tegra_overlay_plane_funcs, formats,
 887                                        num_formats, DRM_PLANE_TYPE_OVERLAY);
 888         if (err < 0) {
 889                 kfree(plane);
 890                 return ERR_PTR(err);
 891         }
 892
 893         drm_plane_helper_add(&plane->base, &tegra_overlay_plane_helper_funcs);
 894
 895         return &plane->base;
 896 }
 897
 898 static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
 899 {
 900         struct drm_plane *plane;
 901         unsigned int i;
 902
 903         for (i = 0; i < 2; i++) {
 904                 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i);
 905                 if (IS_ERR(plane))
 906                         return PTR_ERR(plane);
 907         }
 908
 909         return 0;
 910 }
 911
 912 u32 tegra_dc_get_vblank_counter(struct tegra_dc *dc)
 913 {
 914         if (dc->syncpt)
 915                 return host1x_syncpt_read(dc->syncpt);
 916
 917         /* fallback to software emulated VBLANK counter */
 918         return drm_crtc_vblank_count(&dc->base);
 919 }
 920
 921 void tegra_dc_enable_vblank(struct tegra_dc *dc)
 922 {
 923         unsigned long value, flags;
 924
 925         spin_lock_irqsave(&dc->lock, flags);
 926
 927         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
 928         value |= VBLANK_INT;
 929         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
 930
 931         spin_unlock_irqrestore(&dc->lock, flags);
 932 }
 933
 934 void tegra_dc_disable_vblank(struct tegra_dc *dc)
 935 {
 936         unsigned long value, flags;
 937
 938         spin_lock_irqsave(&dc->lock, flags);
 939
 940         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
 941         value &= ~VBLANK_INT;
 942         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
 943
 944         spin_unlock_irqrestore(&dc->lock, flags);
 945 }
 946
 947 static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
 948 {
 949         struct drm_device *drm = dc->base.dev;
 950         struct drm_crtc *crtc = &dc->base;
 951         unsigned long flags, base;
 952         struct tegra_bo *bo;
 953
 954         spin_lock_irqsave(&drm->event_lock, flags);
 955
 956         if (!dc->event) {
 957                 spin_unlock_irqrestore(&drm->event_lock, flags);
 958                 return;
 959         }
 960
 961         bo = tegra_fb_get_plane(crtc->primary->fb, 0);
 962
 963         spin_lock(&dc->lock);
 964
 965         /* check if new start address has been latched */
 966         tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
 967         tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
 968         base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
 969         tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
 970
 971         spin_unlock(&dc->lock);
 972
 973         if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
 974                 drm_crtc_send_vblank_event(crtc, dc->event);
 975                 drm_crtc_vblank_put(crtc);
 976                 dc->event = NULL;
 977         }
 978
 979         spin_unlock_irqrestore(&drm->event_lock, flags);
 980 }
 981
 982 void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
 983 {
 984         struct tegra_dc *dc = to_tegra_dc(crtc);
 985         struct drm_device *drm = crtc->dev;
 986         unsigned long flags;
 987
 988         spin_lock_irqsave(&drm->event_lock, flags);
 989
 990         if (dc->event && dc->event->base.file_priv == file) {
 991                 dc->event->base.destroy(&dc->event->base);
 992                 drm_crtc_vblank_put(crtc);
 993                 dc->event = NULL;
 994         }
 995
 996         spin_unlock_irqrestore(&drm->event_lock, flags);
 997 }
 998
 999 static void tegra_dc_destroy(struct drm_crtc *crtc)
1000 {
1001         drm_crtc_cleanup(crtc);
1002 }
1003
1004 static void tegra_crtc_reset(struct drm_crtc *crtc)
1005 {
1006         struct tegra_dc_state *state;
1007
1008         if (crtc->state)
1009                 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
1010
1011         kfree(crtc->state);
1012         crtc->state = NULL;
1013
1014         state = kzalloc(sizeof(*state), GFP_KERNEL);
1015         if (state) {
1016                 crtc->state = &state->base;
1017                 crtc->state->crtc = crtc;
1018         }
1019
1020         drm_crtc_vblank_reset(crtc);
1021 }
1022
1023 static struct drm_crtc_state *
1024 tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1025 {
1026         struct tegra_dc_state *state = to_dc_state(crtc->state);
1027         struct tegra_dc_state *copy;
1028
1029         copy = kmalloc(sizeof(*copy), GFP_KERNEL);
1030         if (!copy)
1031                 return NULL;
1032
1033         __drm_atomic_helper_crtc_duplicate_state(crtc, &copy->base);
1034         copy->clk = state->clk;
1035         copy->pclk = state->pclk;
1036         copy->div = state->div;
1037         copy->planes = state->planes;
1038
1039         return &copy->base;
1040 }
1041
1042 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1043                                             struct drm_crtc_state *state)
1044 {
1045         __drm_atomic_helper_crtc_destroy_state(crtc, state);
1046         kfree(state);
1047 }
1048
1049 static const struct drm_crtc_funcs tegra_crtc_funcs = {
1050         .page_flip = drm_atomic_helper_page_flip,
1051         .set_config = drm_atomic_helper_set_config,
1052         .destroy = tegra_dc_destroy,
1053         .reset = tegra_crtc_reset,
1054         .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1055         .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1056 };
1057
1058 static void tegra_dc_stop(struct tegra_dc *dc)
1059 {
1060         u32 value;
1061
1062         /* stop the display controller */
1063         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1064         value &= ~DISP_CTRL_MODE_MASK;
1065         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1066
1067         tegra_dc_commit(dc);
1068 }
1069
1070 static bool tegra_dc_idle(struct tegra_dc *dc)
1071 {
1072         u32 value;
1073
1074         value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1075
1076         return (value & DISP_CTRL_MODE_MASK) == 0;
1077 }
1078
1079 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1080 {
1081         timeout = jiffies + msecs_to_jiffies(timeout);
1082
1083         while (time_before(jiffies, timeout)) {
1084                 if (tegra_dc_idle(dc))
1085                         return 0;
1086
1087                 usleep_range(1000, 2000);
1088         }
1089
1090         dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1091         return -ETIMEDOUT;
1092 }
1093
1094 static void tegra_crtc_disable(struct drm_crtc *crtc)
1095 {
1096         struct tegra_dc *dc = to_tegra_dc(crtc);
1097         u32 value;
1098
1099         if (!tegra_dc_idle(dc)) {
1100                 tegra_dc_stop(dc);
1101
1102                 /*
1103                  * Ignore the return value, there isn't anything useful to do
1104                  * in case this fails.
1105                  */
1106                 tegra_dc_wait_idle(dc, 100);
1107         }
1108
1109         /*
1110          * This should really be part of the RGB encoder driver, but clearing
1111          * these bits has the side-effect of stopping the display controller.
1112          * When that happens no VBLANK interrupts will be raised. At the same
1113          * time the encoder is disabled before the display controller, so the
1114          * above code is always going to timeout waiting for the controller
1115          * to go idle.
1116          *
1117          * Given the close coupling between the RGB encoder and the display
1118          * controller doing it here is still kind of okay. None of the other
1119          * encoder drivers require these bits to be cleared.
1120          *
1121          * XXX: Perhaps given that the display controller is switched off at
1122          * this point anyway maybe clearing these bits isn't even useful for
1123          * the RGB encoder?
1124          */
1125         if (dc->rgb) {
1126                 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1127                 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1128                            PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1129                 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1130         }
1131
1132         drm_crtc_vblank_off(crtc);
1133 }
1134
1135 static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
1136                                   const struct drm_display_mode *mode,
1137                                   struct drm_display_mode *adjusted)
1138 {
1139         return true;
1140 }
1141
1142 static int tegra_dc_set_timings(struct tegra_dc *dc,
1143                                 struct drm_display_mode *mode)
1144 {
1145         unsigned int h_ref_to_sync = 1;
1146         unsigned int v_ref_to_sync = 1;
1147         unsigned long value;
1148
1149         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1150
1151         value = (v_ref_to_sync << 16) | h_ref_to_sync;
1152         tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1153
1154         value = ((mode->vsync_end - mode->vsync_start) << 16) |
1155                 ((mode->hsync_end - mode->hsync_start) <<  0);
1156         tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1157
1158         value = ((mode->vtotal - mode->vsync_end) << 16) |
1159                 ((mode->htotal - mode->hsync_end) <<  0);
1160         tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1161
1162         value = ((mode->vsync_start - mode->vdisplay) << 16) |
1163                 ((mode->hsync_start - mode->hdisplay) <<  0);
1164         tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1165
1166         value = (mode->vdisplay << 16) | mode->hdisplay;
1167         tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1168
1169         return 0;
1170 }
1171
1172 /**
1173  * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1174  *     state
1175  * @dc: display controller
1176  * @crtc_state: CRTC atomic state
1177  * @clk: parent clock for display controller
1178  * @pclk: pixel clock
1179  * @div: shift clock divider
1180  *
1181  * Returns:
1182  * 0 on success or a negative error-code on failure.
1183  */
1184 int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1185                                struct drm_crtc_state *crtc_state,
1186                                struct clk *clk, unsigned long pclk,
1187                                unsigned int div)
1188 {
1189         struct tegra_dc_state *state = to_dc_state(crtc_state);
1190
1191         if (!clk_has_parent(dc->clk, clk))
1192                 return -EINVAL;
1193
1194         state->clk = clk;
1195         state->pclk = pclk;
1196         state->div = div;
1197
1198         return 0;
1199 }
1200
1201 static void tegra_dc_commit_state(struct tegra_dc *dc,
1202                                   struct tegra_dc_state *state)
1203 {
1204         u32 value;
1205         int err;
1206
1207         err = clk_set_parent(dc->clk, state->clk);
1208         if (err < 0)
1209                 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1210
1211         /*
1212          * Outputs may not want to change the parent clock rate. This is only
1213          * relevant to Tegra20 where only a single display PLL is available.
1214          * Since that PLL would typically be used for HDMI, an internal LVDS
1215          * panel would need to be driven by some other clock such as PLL_P
1216          * which is shared with other peripherals. Changing the clock rate
1217          * should therefore be avoided.
1218          */
1219         if (state->pclk > 0) {
1220                 err = clk_set_rate(state->clk, state->pclk);
1221                 if (err < 0)
1222                         dev_err(dc->dev,
1223                                 "failed to set clock rate to %lu Hz\n",
1224                                 state->pclk);
1225         }
1226
1227         DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1228                       state->div);
1229         DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1230
1231         value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1232         tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1233 }
1234
1235 static void tegra_crtc_mode_set_nofb(struct drm_crtc *crtc)
1236 {
1237         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1238         struct tegra_dc_state *state = to_dc_state(crtc->state);
1239         struct tegra_dc *dc = to_tegra_dc(crtc);
1240         u32 value;
1241
1242         tegra_dc_commit_state(dc, state);
1243
1244         /* program display mode */
1245         tegra_dc_set_timings(dc, mode);
1246
1247         /* interlacing isn't supported yet, so disable it */
1248         if (dc->soc->supports_interlacing) {
1249                 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1250                 value &= ~INTERLACE_ENABLE;
1251                 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1252         }
1253
1254         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1255         value &= ~DISP_CTRL_MODE_MASK;
1256         value |= DISP_CTRL_MODE_C_DISPLAY;
1257         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1258
1259         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1260         value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1261                  PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1262         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1263
1264         tegra_dc_commit(dc);
1265 }
1266
1267 static void tegra_crtc_prepare(struct drm_crtc *crtc)
1268 {
1269         drm_crtc_vblank_off(crtc);
1270 }
1271
1272 static void tegra_crtc_commit(struct drm_crtc *crtc)
1273 {
1274         drm_crtc_vblank_on(crtc);
1275 }
1276
1277 static int tegra_crtc_atomic_check(struct drm_crtc *crtc,
1278                                    struct drm_crtc_state *state)
1279 {
1280         return 0;
1281 }
1282
1283 static void tegra_crtc_atomic_begin(struct drm_crtc *crtc)
1284 {
1285         struct tegra_dc *dc = to_tegra_dc(crtc);
1286
1287         if (crtc->state->event) {
1288                 crtc->state->event->pipe = drm_crtc_index(crtc);
1289
1290                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1291
1292                 dc->event = crtc->state->event;
1293                 crtc->state->event = NULL;
1294         }
1295 }
1296
1297 static void tegra_crtc_atomic_flush(struct drm_crtc *crtc)
1298 {
1299         struct tegra_dc_state *state = to_dc_state(crtc->state);
1300         struct tegra_dc *dc = to_tegra_dc(crtc);
1301
1302         tegra_dc_writel(dc, state->planes << 8, DC_CMD_STATE_CONTROL);
1303         tegra_dc_writel(dc, state->planes, DC_CMD_STATE_CONTROL);
1304 }
1305
1306 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
1307         .disable = tegra_crtc_disable,
1308         .mode_fixup = tegra_crtc_mode_fixup,
1309         .mode_set_nofb = tegra_crtc_mode_set_nofb,
1310         .prepare = tegra_crtc_prepare,
1311         .commit = tegra_crtc_commit,
1312         .atomic_check = tegra_crtc_atomic_check,
1313         .atomic_begin = tegra_crtc_atomic_begin,
1314         .atomic_flush = tegra_crtc_atomic_flush,
1315 };
1316
1317 static irqreturn_t tegra_dc_irq(int irq, void *data)
1318 {
1319         struct tegra_dc *dc = data;
1320         unsigned long status;
1321
1322         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1323         tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1324
1325         if (status & FRAME_END_INT) {
1326                 /*
1327                 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1328                 */
1329         }
1330
1331         if (status & VBLANK_INT) {
1332                 /*
1333                 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1334                 */
1335                 drm_crtc_handle_vblank(&dc->base);
1336                 tegra_dc_finish_page_flip(dc);
1337         }
1338
1339         if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1340                 /*
1341                 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1342                 */
1343         }
1344
1345         return IRQ_HANDLED;
1346 }
1347
1348 static int tegra_dc_show_regs(struct seq_file *s, void *data)
1349 {
1350         struct drm_info_node *node = s->private;
1351         struct tegra_dc *dc = node->info_ent->data;
1352
1353 #define DUMP_REG(name)                                          \
1354         seq_printf(s, "%-40s %#05x %08x\n", #name, name,        \
1355                    tegra_dc_readl(dc, name))
1356
1357         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
1358         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1359         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
1360         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
1361         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
1362         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
1363         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
1364         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
1365         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
1366         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
1367         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
1368         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
1369         DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
1370         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
1371         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
1372         DUMP_REG(DC_CMD_SIGNAL_RAISE);
1373         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
1374         DUMP_REG(DC_CMD_INT_STATUS);
1375         DUMP_REG(DC_CMD_INT_MASK);
1376         DUMP_REG(DC_CMD_INT_ENABLE);
1377         DUMP_REG(DC_CMD_INT_TYPE);
1378         DUMP_REG(DC_CMD_INT_POLARITY);
1379         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
1380         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
1381         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
1382         DUMP_REG(DC_CMD_STATE_ACCESS);
1383         DUMP_REG(DC_CMD_STATE_CONTROL);
1384         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
1385         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
1386         DUMP_REG(DC_COM_CRC_CONTROL);
1387         DUMP_REG(DC_COM_CRC_CHECKSUM);
1388         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
1389         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
1390         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
1391         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
1392         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
1393         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
1394         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
1395         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
1396         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
1397         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
1398         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
1399         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
1400         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
1401         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
1402         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
1403         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
1404         DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
1405         DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
1406         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
1407         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
1408         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
1409         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
1410         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
1411         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
1412         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
1413         DUMP_REG(DC_COM_PIN_MISC_CONTROL);
1414         DUMP_REG(DC_COM_PIN_PM0_CONTROL);
1415         DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
1416         DUMP_REG(DC_COM_PIN_PM1_CONTROL);
1417         DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
1418         DUMP_REG(DC_COM_SPI_CONTROL);
1419         DUMP_REG(DC_COM_SPI_START_BYTE);
1420         DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
1421         DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
1422         DUMP_REG(DC_COM_HSPI_CS_DC);
1423         DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
1424         DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
1425         DUMP_REG(DC_COM_GPIO_CTRL);
1426         DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
1427         DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
1428         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
1429         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
1430         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
1431         DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
1432         DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1433         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
1434         DUMP_REG(DC_DISP_REF_TO_SYNC);
1435         DUMP_REG(DC_DISP_SYNC_WIDTH);
1436         DUMP_REG(DC_DISP_BACK_PORCH);
1437         DUMP_REG(DC_DISP_ACTIVE);
1438         DUMP_REG(DC_DISP_FRONT_PORCH);
1439         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
1440         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
1441         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
1442         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
1443         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
1444         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
1445         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
1446         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
1447         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
1448         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
1449         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
1450         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
1451         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
1452         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
1453         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
1454         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
1455         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
1456         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
1457         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
1458         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
1459         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
1460         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
1461         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
1462         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
1463         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
1464         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
1465         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
1466         DUMP_REG(DC_DISP_M0_CONTROL);
1467         DUMP_REG(DC_DISP_M1_CONTROL);
1468         DUMP_REG(DC_DISP_DI_CONTROL);
1469         DUMP_REG(DC_DISP_PP_CONTROL);
1470         DUMP_REG(DC_DISP_PP_SELECT_A);
1471         DUMP_REG(DC_DISP_PP_SELECT_B);
1472         DUMP_REG(DC_DISP_PP_SELECT_C);
1473         DUMP_REG(DC_DISP_PP_SELECT_D);
1474         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
1475         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
1476         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
1477         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
1478         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
1479         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
1480         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
1481         DUMP_REG(DC_DISP_BORDER_COLOR);
1482         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
1483         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
1484         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
1485         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
1486         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
1487         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
1488         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
1489         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
1490         DUMP_REG(DC_DISP_CURSOR_POSITION);
1491         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
1492         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
1493         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
1494         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
1495         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
1496         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
1497         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
1498         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
1499         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
1500         DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
1501         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
1502         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
1503         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
1504         DUMP_REG(DC_DISP_SD_CONTROL);
1505         DUMP_REG(DC_DISP_SD_CSC_COEFF);
1506         DUMP_REG(DC_DISP_SD_LUT(0));
1507         DUMP_REG(DC_DISP_SD_LUT(1));
1508         DUMP_REG(DC_DISP_SD_LUT(2));
1509         DUMP_REG(DC_DISP_SD_LUT(3));
1510         DUMP_REG(DC_DISP_SD_LUT(4));
1511         DUMP_REG(DC_DISP_SD_LUT(5));
1512         DUMP_REG(DC_DISP_SD_LUT(6));
1513         DUMP_REG(DC_DISP_SD_LUT(7));
1514         DUMP_REG(DC_DISP_SD_LUT(8));
1515         DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
1516         DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
1517         DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1518         DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1519         DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1520         DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1521         DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1522         DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1523         DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1524         DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1525         DUMP_REG(DC_DISP_SD_BL_TF(0));
1526         DUMP_REG(DC_DISP_SD_BL_TF(1));
1527         DUMP_REG(DC_DISP_SD_BL_TF(2));
1528         DUMP_REG(DC_DISP_SD_BL_TF(3));
1529         DUMP_REG(DC_DISP_SD_BL_CONTROL);
1530         DUMP_REG(DC_DISP_SD_HW_K_VALUES);
1531         DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
1532         DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
1533         DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL);
1534         DUMP_REG(DC_WIN_WIN_OPTIONS);
1535         DUMP_REG(DC_WIN_BYTE_SWAP);
1536         DUMP_REG(DC_WIN_BUFFER_CONTROL);
1537         DUMP_REG(DC_WIN_COLOR_DEPTH);
1538         DUMP_REG(DC_WIN_POSITION);
1539         DUMP_REG(DC_WIN_SIZE);
1540         DUMP_REG(DC_WIN_PRESCALED_SIZE);
1541         DUMP_REG(DC_WIN_H_INITIAL_DDA);
1542         DUMP_REG(DC_WIN_V_INITIAL_DDA);
1543         DUMP_REG(DC_WIN_DDA_INC);
1544         DUMP_REG(DC_WIN_LINE_STRIDE);
1545         DUMP_REG(DC_WIN_BUF_STRIDE);
1546         DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1547         DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1548         DUMP_REG(DC_WIN_DV_CONTROL);
1549         DUMP_REG(DC_WIN_BLEND_NOKEY);
1550         DUMP_REG(DC_WIN_BLEND_1WIN);
1551         DUMP_REG(DC_WIN_BLEND_2WIN_X);
1552         DUMP_REG(DC_WIN_BLEND_2WIN_Y);
1553         DUMP_REG(DC_WIN_BLEND_3WIN_XY);
1554         DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1555         DUMP_REG(DC_WINBUF_START_ADDR);
1556         DUMP_REG(DC_WINBUF_START_ADDR_NS);
1557         DUMP_REG(DC_WINBUF_START_ADDR_U);
1558         DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1559         DUMP_REG(DC_WINBUF_START_ADDR_V);
1560         DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1561         DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1562         DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1563         DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1564         DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1565         DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1566         DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1567         DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1568         DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1569
1570 #undef DUMP_REG
1571
1572         return 0;
1573 }
1574
1575 static int tegra_dc_show_crc(struct seq_file *s, void *data)
1576 {
1577         struct drm_info_node *node = s->private;
1578         struct tegra_dc *dc = node->info_ent->data;
1579         u32 value;
1580
1581         value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1582         tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1583         tegra_dc_commit(dc);
1584
1585         drm_crtc_wait_one_vblank(&dc->base);
1586         drm_crtc_wait_one_vblank(&dc->base);
1587
1588         value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1589         seq_printf(s, "%08x\n", value);
1590
1591         tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1592
1593         return 0;
1594 }
1595
1596 static struct drm_info_list debugfs_files[] = {
1597         { "regs", tegra_dc_show_regs, 0, NULL },
1598         { "crc", tegra_dc_show_crc, 0, NULL },
1599 };
1600
1601 static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1602 {
1603         unsigned int i;
1604         char *name;
1605         int err;
1606
1607         name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1608         dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1609         kfree(name);
1610
1611         if (!dc->debugfs)
1612                 return -ENOMEM;
1613
1614         dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1615                                     GFP_KERNEL);
1616         if (!dc->debugfs_files) {
1617                 err = -ENOMEM;
1618                 goto remove;
1619         }
1620
1621         for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1622                 dc->debugfs_files[i].data = dc;
1623
1624         err = drm_debugfs_create_files(dc->debugfs_files,
1625                                        ARRAY_SIZE(debugfs_files),
1626                                        dc->debugfs, minor);
1627         if (err < 0)
1628                 goto free;
1629
1630         dc->minor = minor;
1631
1632         return 0;
1633
1634 free:
1635         kfree(dc->debugfs_files);
1636         dc->debugfs_files = NULL;
1637 remove:
1638         debugfs_remove(dc->debugfs);
1639         dc->debugfs = NULL;
1640
1641         return err;
1642 }
1643
1644 static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1645 {
1646         drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1647                                  dc->minor);
1648         dc->minor = NULL;
1649
1650         kfree(dc->debugfs_files);
1651         dc->debugfs_files = NULL;
1652
1653         debugfs_remove(dc->debugfs);
1654         dc->debugfs = NULL;
1655
1656         return 0;
1657 }
1658
1659 static int tegra_dc_init(struct host1x_client *client)
1660 {
1661         struct drm_device *drm = dev_get_drvdata(client->parent);
1662         struct tegra_dc *dc = host1x_client_to_dc(client);
1663         struct tegra_drm *tegra = drm->dev_private;
1664         struct drm_plane *primary = NULL;
1665         struct drm_plane *cursor = NULL;
1666         u32 value;
1667         int err;
1668
1669         if (tegra->domain) {
1670                 err = iommu_attach_device(tegra->domain, dc->dev);
1671                 if (err < 0) {
1672                         dev_err(dc->dev, "failed to attach to domain: %d\n",
1673                                 err);
1674                         return err;
1675                 }
1676
1677                 dc->domain = tegra->domain;
1678         }
1679
1680         primary = tegra_dc_primary_plane_create(drm, dc);
1681         if (IS_ERR(primary)) {
1682                 err = PTR_ERR(primary);
1683                 goto cleanup;
1684         }
1685
1686         if (dc->soc->supports_cursor) {
1687                 cursor = tegra_dc_cursor_plane_create(drm, dc);
1688                 if (IS_ERR(cursor)) {
1689                         err = PTR_ERR(cursor);
1690                         goto cleanup;
1691                 }
1692         }
1693
1694         err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
1695                                         &tegra_crtc_funcs);
1696         if (err < 0)
1697                 goto cleanup;
1698
1699         drm_mode_crtc_set_gamma_size(&dc->base, 256);
1700         drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1701
1702         /*
1703          * Keep track of the minimum pitch alignment across all display
1704          * controllers.
1705          */
1706         if (dc->soc->pitch_align > tegra->pitch_align)
1707                 tegra->pitch_align = dc->soc->pitch_align;
1708
1709         err = tegra_dc_rgb_init(drm, dc);
1710         if (err < 0 && err != -ENODEV) {
1711                 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1712                 goto cleanup;
1713         }
1714
1715         err = tegra_dc_add_planes(drm, dc);
1716         if (err < 0)
1717                 goto cleanup;
1718
1719         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1720                 err = tegra_dc_debugfs_init(dc, drm->primary);
1721                 if (err < 0)
1722                         dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1723         }
1724
1725         err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
1726                                dev_name(dc->dev), dc);
1727         if (err < 0) {
1728                 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1729                         err);
1730                 goto cleanup;
1731         }
1732
1733         /* initialize display controller */
1734         if (dc->syncpt) {
1735                 u32 syncpt = host1x_syncpt_id(dc->syncpt);
1736
1737                 value = SYNCPT_CNTRL_NO_STALL;
1738                 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1739
1740                 value = SYNCPT_VSYNC_ENABLE | syncpt;
1741                 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1742         }
1743
1744         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
1745         tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1746
1747         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1748                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1749         tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1750
1751         /* initialize timer */
1752         value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1753                 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1754         tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1755
1756         value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1757                 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1758         tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1759
1760         value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
1761         tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1762
1763         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
1764         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1765
1766         if (dc->soc->supports_border_color)
1767                 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1768
1769         return 0;
1770
1771 cleanup:
1772         if (cursor)
1773                 drm_plane_cleanup(cursor);
1774
1775         if (primary)
1776                 drm_plane_cleanup(primary);
1777
1778         if (tegra->domain) {
1779                 iommu_detach_device(tegra->domain, dc->dev);
1780                 dc->domain = NULL;
1781         }
1782
1783         return err;
1784 }
1785
1786 static int tegra_dc_exit(struct host1x_client *client)
1787 {
1788         struct tegra_dc *dc = host1x_client_to_dc(client);
1789         int err;
1790
1791         devm_free_irq(dc->dev, dc->irq, dc);
1792
1793         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1794                 err = tegra_dc_debugfs_exit(dc);
1795                 if (err < 0)
1796                         dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1797         }
1798
1799         err = tegra_dc_rgb_exit(dc);
1800         if (err) {
1801                 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1802                 return err;
1803         }
1804
1805         if (dc->domain) {
1806                 iommu_detach_device(dc->domain, dc->dev);
1807                 dc->domain = NULL;
1808         }
1809
1810         return 0;
1811 }
1812
1813 static const struct host1x_client_ops dc_client_ops = {
1814         .init = tegra_dc_init,
1815         .exit = tegra_dc_exit,
1816 };
1817
1818 static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
1819         .supports_border_color = true,
1820         .supports_interlacing = false,
1821         .supports_cursor = false,
1822         .supports_block_linear = false,
1823         .pitch_align = 8,
1824         .has_powergate = false,
1825 };
1826
1827 static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
1828         .supports_border_color = true,
1829         .supports_interlacing = false,
1830         .supports_cursor = false,
1831         .supports_block_linear = false,
1832         .pitch_align = 8,
1833         .has_powergate = false,
1834 };
1835
1836 static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
1837         .supports_border_color = true,
1838         .supports_interlacing = false,
1839         .supports_cursor = false,
1840         .supports_block_linear = false,
1841         .pitch_align = 64,
1842         .has_powergate = true,
1843 };
1844
1845 static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
1846         .supports_border_color = false,
1847         .supports_interlacing = true,
1848         .supports_cursor = true,
1849         .supports_block_linear = true,
1850         .pitch_align = 64,
1851         .has_powergate = true,
1852 };
1853
1854 static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
1855         .supports_border_color = false,
1856         .supports_interlacing = true,
1857         .supports_cursor = true,
1858         .supports_block_linear = true,
1859         .pitch_align = 64,
1860         .has_powergate = true,
1861 };
1862
1863 static const struct of_device_id tegra_dc_of_match[] = {
1864         {
1865                 .compatible = "nvidia,tegra210-dc",
1866                 .data = &tegra210_dc_soc_info,
1867         }, {
1868                 .compatible = "nvidia,tegra124-dc",
1869                 .data = &tegra124_dc_soc_info,
1870         }, {
1871                 .compatible = "nvidia,tegra114-dc",
1872                 .data = &tegra114_dc_soc_info,
1873         }, {
1874                 .compatible = "nvidia,tegra30-dc",
1875                 .data = &tegra30_dc_soc_info,
1876         }, {
1877                 .compatible = "nvidia,tegra20-dc",
1878                 .data = &tegra20_dc_soc_info,
1879         }, {
1880                 /* sentinel */
1881         }
1882 };
1883 MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
1884
1885 static int tegra_dc_parse_dt(struct tegra_dc *dc)
1886 {
1887         struct device_node *np;
1888         u32 value = 0;
1889         int err;
1890
1891         err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1892         if (err < 0) {
1893                 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1894
1895                 /*
1896                  * If the nvidia,head property isn't present, try to find the
1897                  * correct head number by looking up the position of this
1898                  * display controller's node within the device tree. Assuming
1899                  * that the nodes are ordered properly in the DTS file and
1900                  * that the translation into a flattened device tree blob
1901                  * preserves that ordering this will actually yield the right
1902                  * head number.
1903                  *
1904                  * If those assumptions don't hold, this will still work for
1905                  * cases where only a single display controller is used.
1906                  */
1907                 for_each_matching_node(np, tegra_dc_of_match) {
1908                         if (np == dc->dev->of_node)
1909                                 break;
1910
1911                         value++;
1912                 }
1913         }
1914
1915         dc->pipe = value;
1916
1917         return 0;
1918 }
1919
1920 static int tegra_dc_probe(struct platform_device *pdev)
1921 {
1922         unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
1923         const struct of_device_id *id;
1924         struct resource *regs;
1925         struct tegra_dc *dc;
1926         int err;
1927
1928         dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1929         if (!dc)
1930                 return -ENOMEM;
1931
1932         id = of_match_node(tegra_dc_of_match, pdev->dev.of_node);
1933         if (!id)
1934                 return -ENODEV;
1935
1936         spin_lock_init(&dc->lock);
1937         INIT_LIST_HEAD(&dc->list);
1938         dc->dev = &pdev->dev;
1939         dc->soc = id->data;
1940
1941         err = tegra_dc_parse_dt(dc);
1942         if (err < 0)
1943                 return err;
1944
1945         dc->clk = devm_clk_get(&pdev->dev, NULL);
1946         if (IS_ERR(dc->clk)) {
1947                 dev_err(&pdev->dev, "failed to get clock\n");
1948                 return PTR_ERR(dc->clk);
1949         }
1950
1951         dc->rst = devm_reset_control_get(&pdev->dev, "dc");
1952         if (IS_ERR(dc->rst)) {
1953                 dev_err(&pdev->dev, "failed to get reset\n");
1954                 return PTR_ERR(dc->rst);
1955         }
1956
1957         if (dc->soc->has_powergate) {
1958                 if (dc->pipe == 0)
1959                         dc->powergate = TEGRA_POWERGATE_DIS;
1960                 else
1961                         dc->powergate = TEGRA_POWERGATE_DISB;
1962
1963                 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
1964                                                         dc->rst);
1965                 if (err < 0) {
1966                         dev_err(&pdev->dev, "failed to power partition: %d\n",
1967                                 err);
1968                         return err;
1969                 }
1970         } else {
1971                 err = clk_prepare_enable(dc->clk);
1972                 if (err < 0) {
1973                         dev_err(&pdev->dev, "failed to enable clock: %d\n",
1974                                 err);
1975                         return err;
1976                 }
1977
1978                 err = reset_control_deassert(dc->rst);
1979                 if (err < 0) {
1980                         dev_err(&pdev->dev, "failed to deassert reset: %d\n",
1981                                 err);
1982                         return err;
1983                 }
1984         }
1985
1986         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1987         dc->regs = devm_ioremap_resource(&pdev->dev, regs);
1988         if (IS_ERR(dc->regs))
1989                 return PTR_ERR(dc->regs);
1990
1991         dc->irq = platform_get_irq(pdev, 0);
1992         if (dc->irq < 0) {
1993                 dev_err(&pdev->dev, "failed to get IRQ\n");
1994                 return -ENXIO;
1995         }
1996
1997         INIT_LIST_HEAD(&dc->client.list);
1998         dc->client.ops = &dc_client_ops;
1999         dc->client.dev = &pdev->dev;
2000
2001         err = tegra_dc_rgb_probe(dc);
2002         if (err < 0 && err != -ENODEV) {
2003                 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
2004                 return err;
2005         }
2006
2007         err = host1x_client_register(&dc->client);
2008         if (err < 0) {
2009                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2010                         err);
2011                 return err;
2012         }
2013
2014         dc->syncpt = host1x_syncpt_request(&pdev->dev, flags);
2015         if (!dc->syncpt)
2016                 dev_warn(&pdev->dev, "failed to allocate syncpoint\n");
2017
2018         platform_set_drvdata(pdev, dc);
2019
2020         return 0;
2021 }
2022
2023 static int tegra_dc_remove(struct platform_device *pdev)
2024 {
2025         struct tegra_dc *dc = platform_get_drvdata(pdev);
2026         int err;
2027
2028         host1x_syncpt_free(dc->syncpt);
2029
2030         err = host1x_client_unregister(&dc->client);
2031         if (err < 0) {
2032                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2033                         err);
2034                 return err;
2035         }
2036
2037         err = tegra_dc_rgb_remove(dc);
2038         if (err < 0) {
2039                 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2040                 return err;
2041         }
2042
2043         reset_control_assert(dc->rst);
2044
2045         if (dc->soc->has_powergate)
2046                 tegra_powergate_power_off(dc->powergate);
2047
2048         clk_disable_unprepare(dc->clk);
2049
2050         return 0;
2051 }
2052
2053 struct platform_driver tegra_dc_driver = {
2054         .driver = {
2055                 .name = "tegra-dc",
2056                 .owner = THIS_MODULE,
2057                 .of_match_table = tegra_dc_of_match,
2058         },
2059         .probe = tegra_dc_probe,
2060         .remove = tegra_dc_remove,
2061 };