2 * Copyright (C) STMicroelectronics SA 2014
3 * Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
4 * License terms: GNU General Public License (GPL), version 2
8 #include <linux/component.h>
9 #include <linux/module.h>
10 #include <linux/platform_device.h>
13 #include <drm/drm_crtc_helper.h>
15 /* HDformatter registers */
16 #define HDA_ANA_CFG 0x0000
17 #define HDA_ANA_SCALE_CTRL_Y 0x0004
18 #define HDA_ANA_SCALE_CTRL_CB 0x0008
19 #define HDA_ANA_SCALE_CTRL_CR 0x000C
20 #define HDA_ANA_ANC_CTRL 0x0010
21 #define HDA_ANA_SRC_Y_CFG 0x0014
22 #define HDA_COEFF_Y_PH1_TAP123 0x0018
23 #define HDA_COEFF_Y_PH1_TAP456 0x001C
24 #define HDA_COEFF_Y_PH2_TAP123 0x0020
25 #define HDA_COEFF_Y_PH2_TAP456 0x0024
26 #define HDA_COEFF_Y_PH3_TAP123 0x0028
27 #define HDA_COEFF_Y_PH3_TAP456 0x002C
28 #define HDA_COEFF_Y_PH4_TAP123 0x0030
29 #define HDA_COEFF_Y_PH4_TAP456 0x0034
30 #define HDA_ANA_SRC_C_CFG 0x0040
31 #define HDA_COEFF_C_PH1_TAP123 0x0044
32 #define HDA_COEFF_C_PH1_TAP456 0x0048
33 #define HDA_COEFF_C_PH2_TAP123 0x004C
34 #define HDA_COEFF_C_PH2_TAP456 0x0050
35 #define HDA_COEFF_C_PH3_TAP123 0x0054
36 #define HDA_COEFF_C_PH3_TAP456 0x0058
37 #define HDA_COEFF_C_PH4_TAP123 0x005C
38 #define HDA_COEFF_C_PH4_TAP456 0x0060
39 #define HDA_SYNC_AWGI 0x0300
42 #define CFG_AWG_ASYNC_EN BIT(0)
43 #define CFG_AWG_ASYNC_HSYNC_MTD BIT(1)
44 #define CFG_AWG_ASYNC_VSYNC_MTD BIT(2)
45 #define CFG_AWG_SYNC_DEL BIT(3)
46 #define CFG_AWG_FLTR_MODE_SHIFT 4
47 #define CFG_AWG_FLTR_MODE_MASK (0xF << CFG_AWG_FLTR_MODE_SHIFT)
48 #define CFG_AWG_FLTR_MODE_SD (0 << CFG_AWG_FLTR_MODE_SHIFT)
49 #define CFG_AWG_FLTR_MODE_ED (1 << CFG_AWG_FLTR_MODE_SHIFT)
50 #define CFG_AWG_FLTR_MODE_HD (2 << CFG_AWG_FLTR_MODE_SHIFT)
51 #define CFG_SYNC_ON_PBPR_MASK BIT(8)
52 #define CFG_PREFILTER_EN_MASK BIT(9)
53 #define CFG_PBPR_SYNC_OFF_SHIFT 16
54 #define CFG_PBPR_SYNC_OFF_MASK (0x7FF << CFG_PBPR_SYNC_OFF_SHIFT)
55 #define CFG_PBPR_SYNC_OFF_VAL 0x117 /* Voltage dependent. stiH416 */
57 /* Default scaling values */
58 #define SCALE_CTRL_Y_DFLT 0x00C50256
59 #define SCALE_CTRL_CB_DFLT 0x00DB0249
60 #define SCALE_CTRL_CR_DFLT 0x00DB0249
62 /* Video DACs control */
63 #define VIDEO_DACS_CONTROL_MASK 0x0FFF
64 #define VIDEO_DACS_CONTROL_SYSCFG2535 0x085C /* for stih416 */
65 #define DAC_CFG_HD_OFF_SHIFT 5
66 #define DAC_CFG_HD_OFF_MASK (0x7 << DAC_CFG_HD_OFF_SHIFT)
67 #define VIDEO_DACS_CONTROL_SYSCFG5072 0x0120 /* for stih407 */
68 #define DAC_CFG_HD_HZUVW_OFF_MASK BIT(1)
71 /* Upsampler values for the alternative 2X Filter */
72 #define SAMPLER_COEF_NB 8
73 #define HDA_ANA_SRC_Y_CFG_ALT_2X 0x01130000
74 static u32 coef_y_alt_2x[] = {
75 0x00FE83FB, 0x1F900401, 0x00000000, 0x00000000,
76 0x00F408F9, 0x055F7C25, 0x00000000, 0x00000000
79 #define HDA_ANA_SRC_C_CFG_ALT_2X 0x01750004
80 static u32 coef_c_alt_2x[] = {
81 0x001305F7, 0x05274BD0, 0x00000000, 0x00000000,
82 0x0004907C, 0x09C80B9D, 0x00000000, 0x00000000
85 /* Upsampler values for the 4X Filter */
86 #define HDA_ANA_SRC_Y_CFG_4X 0x01ED0005
87 #define HDA_ANA_SRC_C_CFG_4X 0x01ED0004
88 static u32 coef_yc_4x[] = {
89 0x00FC827F, 0x008FE20B, 0x00F684FC, 0x050F7C24,
90 0x00F4857C, 0x0A1F402E, 0x00FA027F, 0x0E076E1D
93 /* AWG instructions for some video modes */
94 #define AWG_MAX_INST 64
97 static u32 AWGi_720p_50[] = {
98 0x00000971, 0x00000C26, 0x0000013B, 0x00000CDA,
99 0x00000104, 0x00000E7E, 0x00000E7F, 0x0000013B,
100 0x00000D8E, 0x00000104, 0x00001804, 0x00000971,
101 0x00000C26, 0x0000003B, 0x00000FB4, 0x00000FB5,
102 0x00000104, 0x00001AE8
105 #define NN_720p_50 ARRAY_SIZE(AWGi_720p_50)
108 static u32 AWGi_720p_60[] = {
109 0x00000971, 0x00000C26, 0x0000013B, 0x00000CDA,
110 0x00000104, 0x00000E7E, 0x00000E7F, 0x0000013B,
111 0x00000C44, 0x00000104, 0x00001804, 0x00000971,
112 0x00000C26, 0x0000003B, 0x00000F0F, 0x00000F10,
113 0x00000104, 0x00001AE8
116 #define NN_720p_60 ARRAY_SIZE(AWGi_720p_60)
119 static u32 AWGi_1080p_30[] = {
120 0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
121 0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
122 0x00000C2A, 0x00000104, 0x00001804, 0x00000971,
123 0x00000C2A, 0x0000003B, 0x00000EBE, 0x00000EBF,
124 0x00000EBF, 0x00000104, 0x00001A2F, 0x00001C4B,
128 #define NN_1080p_30 ARRAY_SIZE(AWGi_1080p_30)
131 static u32 AWGi_1080p_25[] = {
132 0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
133 0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
134 0x00000DE2, 0x00000104, 0x00001804, 0x00000971,
135 0x00000C2A, 0x0000003B, 0x00000F51, 0x00000F51,
136 0x00000F52, 0x00000104, 0x00001A2F, 0x00001C4B,
140 #define NN_1080p_25 ARRAY_SIZE(AWGi_1080p_25)
143 static u32 AWGi_1080p_24[] = {
144 0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
145 0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
146 0x00000E50, 0x00000104, 0x00001804, 0x00000971,
147 0x00000C2A, 0x0000003B, 0x00000F76, 0x00000F76,
148 0x00000F76, 0x00000104, 0x00001A2F, 0x00001C4B,
152 #define NN_1080p_24 ARRAY_SIZE(AWGi_1080p_24)
155 static u32 AWGi_720x480p_60[] = {
156 0x00000904, 0x00000F18, 0x0000013B, 0x00001805,
157 0x00000904, 0x00000C3D, 0x0000003B, 0x00001A06
160 #define NN_720x480p_60 ARRAY_SIZE(AWGi_720x480p_60)
162 /* Video mode category */
163 enum sti_hda_vid_cat {
170 struct sti_hda_video_config {
171 struct drm_display_mode mode;
174 enum sti_hda_vid_cat vid_cat;
177 /* HD analog supported modes
178 * Interlaced modes may be added when supported by the whole display chain
180 static const struct sti_hda_video_config hda_supported_modes[] = {
181 /* 1080p30 74.250Mhz */
182 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
183 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
184 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
185 AWGi_1080p_30, NN_1080p_30, VID_HD_74M},
186 /* 1080p30 74.176Mhz */
187 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74176, 1920, 2008,
188 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
190 AWGi_1080p_30, NN_1080p_30, VID_HD_74M},
191 /* 1080p24 74.250Mhz */
192 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
193 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
195 AWGi_1080p_24, NN_1080p_24, VID_HD_74M},
196 /* 1080p24 74.176Mhz */
197 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74176, 1920, 2558,
198 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
200 AWGi_1080p_24, NN_1080p_24, VID_HD_74M},
201 /* 1080p25 74.250Mhz */
202 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
203 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
205 AWGi_1080p_25, NN_1080p_25, VID_HD_74M},
206 /* 720p60 74.250Mhz */
207 {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
208 1430, 1650, 0, 720, 725, 730, 750, 0,
209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
210 AWGi_720p_60, NN_720p_60, VID_HD_74M},
211 /* 720p60 74.176Mhz */
212 {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74176, 1280, 1390,
213 1430, 1650, 0, 720, 725, 730, 750, 0,
214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
215 AWGi_720p_60, NN_720p_60, VID_HD_74M},
216 /* 720p50 74.250Mhz */
217 {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
218 1760, 1980, 0, 720, 725, 730, 750, 0,
219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
220 AWGi_720p_50, NN_720p_50, VID_HD_74M},
221 /* 720x480p60 27.027Mhz */
222 {{DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27027, 720, 736,
223 798, 858, 0, 480, 489, 495, 525, 0,
224 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)},
225 AWGi_720x480p_60, NN_720x480p_60, VID_ED},
226 /* 720x480p60 27.000Mhz */
227 {{DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
228 798, 858, 0, 480, 489, 495, 525, 0,
229 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)},
230 AWGi_720x480p_60, NN_720x480p_60, VID_ED}
234 * STI hd analog structure
236 * @dev: driver device
237 * @drm_dev: pointer to drm device
238 * @mode: current display mode selected
239 * @regs: HD analog register
240 * @video_dacs_ctrl: video DACS control register
241 * @enabled: true if HD analog is enabled else false
245 struct drm_device *drm_dev;
246 struct drm_display_mode mode;
248 void __iomem *video_dacs_ctrl;
250 struct clk *clk_hddac;
254 struct sti_hda_connector {
255 struct drm_connector drm_connector;
256 struct drm_encoder *encoder;
260 #define to_sti_hda_connector(x) \
261 container_of(x, struct sti_hda_connector, drm_connector)
263 static u32 hda_read(struct sti_hda *hda, int offset)
265 return readl(hda->regs + offset);
268 static void hda_write(struct sti_hda *hda, u32 val, int offset)
270 writel(val, hda->regs + offset);
274 * Search for a video mode in the supported modes table
276 * @mode: mode being searched
277 * @idx: index of the found mode
279 * Return true if mode is found
281 static bool hda_get_mode_idx(struct drm_display_mode mode, int *idx)
285 for (i = 0; i < ARRAY_SIZE(hda_supported_modes); i++)
286 if (drm_mode_equal(&hda_supported_modes[i].mode, &mode)) {
296 * @hda: pointer to HD analog structure
297 * @enable: true if HD DACS need to be enabled, else false
299 static void hda_enable_hd_dacs(struct sti_hda *hda, bool enable)
303 if (hda->video_dacs_ctrl) {
306 switch ((u32)hda->video_dacs_ctrl & VIDEO_DACS_CONTROL_MASK) {
307 case VIDEO_DACS_CONTROL_SYSCFG2535:
308 mask = DAC_CFG_HD_OFF_MASK;
310 case VIDEO_DACS_CONTROL_SYSCFG5072:
311 mask = DAC_CFG_HD_HZUVW_OFF_MASK;
314 DRM_INFO("Video DACS control register not supported!");
318 val = readl(hda->video_dacs_ctrl);
324 writel(val, hda->video_dacs_ctrl);
329 * Configure AWG, writing instructions
331 * @hda: pointer to HD analog structure
332 * @awg_instr: pointer to AWG instructions table
333 * @nb: nb of AWG instructions
335 static void sti_hda_configure_awg(struct sti_hda *hda, u32 *awg_instr, int nb)
339 DRM_DEBUG_DRIVER("\n");
341 for (i = 0; i < nb; i++)
342 hda_write(hda, awg_instr[i], HDA_SYNC_AWGI + i * 4);
343 for (i = nb; i < AWG_MAX_INST; i++)
344 hda_write(hda, 0, HDA_SYNC_AWGI + i * 4);
347 static void sti_hda_disable(struct drm_bridge *bridge)
349 struct sti_hda *hda = bridge->driver_private;
355 DRM_DEBUG_DRIVER("\n");
357 /* Disable HD DAC and AWG */
358 val = hda_read(hda, HDA_ANA_CFG);
359 val &= ~CFG_AWG_ASYNC_EN;
360 hda_write(hda, val, HDA_ANA_CFG);
361 hda_write(hda, 0, HDA_ANA_ANC_CTRL);
363 hda_enable_hd_dacs(hda, false);
365 /* Disable/unprepare hda clock */
366 clk_disable_unprepare(hda->clk_hddac);
367 clk_disable_unprepare(hda->clk_pix);
369 hda->enabled = false;
372 static void sti_hda_pre_enable(struct drm_bridge *bridge)
374 struct sti_hda *hda = bridge->driver_private;
375 u32 val, i, mode_idx;
376 u32 src_filter_y, src_filter_c;
377 u32 *coef_y, *coef_c;
380 DRM_DEBUG_DRIVER("\n");
385 /* Prepare/enable clocks */
386 if (clk_prepare_enable(hda->clk_pix))
387 DRM_ERROR("Failed to prepare/enable hda_pix clk\n");
388 if (clk_prepare_enable(hda->clk_hddac))
389 DRM_ERROR("Failed to prepare/enable hda_hddac clk\n");
391 if (!hda_get_mode_idx(hda->mode, &mode_idx)) {
392 DRM_ERROR("Undefined mode\n");
396 switch (hda_supported_modes[mode_idx].vid_cat) {
398 DRM_ERROR("Beyond HD analog capabilities\n");
401 /* HD use alternate 2x filter */
402 filter_mode = CFG_AWG_FLTR_MODE_HD;
403 src_filter_y = HDA_ANA_SRC_Y_CFG_ALT_2X;
404 src_filter_c = HDA_ANA_SRC_C_CFG_ALT_2X;
405 coef_y = coef_y_alt_2x;
406 coef_c = coef_c_alt_2x;
409 /* ED uses 4x filter */
410 filter_mode = CFG_AWG_FLTR_MODE_ED;
411 src_filter_y = HDA_ANA_SRC_Y_CFG_4X;
412 src_filter_c = HDA_ANA_SRC_C_CFG_4X;
417 DRM_ERROR("Not supported\n");
420 DRM_ERROR("Undefined resolution\n");
423 DRM_DEBUG_DRIVER("Using HDA mode #%d\n", mode_idx);
425 /* Enable HD Video DACs */
426 hda_enable_hd_dacs(hda, true);
428 /* Configure scaler */
429 hda_write(hda, SCALE_CTRL_Y_DFLT, HDA_ANA_SCALE_CTRL_Y);
430 hda_write(hda, SCALE_CTRL_CB_DFLT, HDA_ANA_SCALE_CTRL_CB);
431 hda_write(hda, SCALE_CTRL_CR_DFLT, HDA_ANA_SCALE_CTRL_CR);
433 /* Configure sampler */
434 hda_write(hda , src_filter_y, HDA_ANA_SRC_Y_CFG);
435 hda_write(hda, src_filter_c, HDA_ANA_SRC_C_CFG);
436 for (i = 0; i < SAMPLER_COEF_NB; i++) {
437 hda_write(hda, coef_y[i], HDA_COEFF_Y_PH1_TAP123 + i * 4);
438 hda_write(hda, coef_c[i], HDA_COEFF_C_PH1_TAP123 + i * 4);
441 /* Configure main HDFormatter */
443 val |= (hda->mode.flags & DRM_MODE_FLAG_INTERLACE) ?
444 0 : CFG_AWG_ASYNC_VSYNC_MTD;
445 val |= (CFG_PBPR_SYNC_OFF_VAL << CFG_PBPR_SYNC_OFF_SHIFT);
447 hda_write(hda, val, HDA_ANA_CFG);
450 sti_hda_configure_awg(hda, hda_supported_modes[mode_idx].awg_instr,
451 hda_supported_modes[mode_idx].nb_instr);
454 val = hda_read(hda, HDA_ANA_CFG);
455 val |= CFG_AWG_ASYNC_EN;
456 hda_write(hda, val, HDA_ANA_CFG);
461 static void sti_hda_set_mode(struct drm_bridge *bridge,
462 struct drm_display_mode *mode,
463 struct drm_display_mode *adjusted_mode)
465 struct sti_hda *hda = bridge->driver_private;
470 DRM_DEBUG_DRIVER("\n");
472 memcpy(&hda->mode, mode, sizeof(struct drm_display_mode));
474 if (!hda_get_mode_idx(hda->mode, &mode_idx)) {
475 DRM_ERROR("Undefined mode\n");
479 switch (hda_supported_modes[mode_idx].vid_cat) {
481 /* HD use alternate 2x filter */
482 hddac_rate = mode->clock * 1000 * 2;
485 /* ED uses 4x filter */
486 hddac_rate = mode->clock * 1000 * 4;
489 DRM_ERROR("Undefined mode\n");
493 /* HD DAC = 148.5Mhz or 108 Mhz */
494 ret = clk_set_rate(hda->clk_hddac, hddac_rate);
496 DRM_ERROR("Cannot set rate (%dHz) for hda_hddac clk\n",
499 /* HDformatter clock = compositor clock */
500 ret = clk_set_rate(hda->clk_pix, mode->clock * 1000);
502 DRM_ERROR("Cannot set rate (%dHz) for hda_pix clk\n",
506 static void sti_hda_bridge_nope(struct drm_bridge *bridge)
511 static void sti_hda_brigde_destroy(struct drm_bridge *bridge)
513 drm_bridge_cleanup(bridge);
517 static const struct drm_bridge_funcs sti_hda_bridge_funcs = {
518 .pre_enable = sti_hda_pre_enable,
519 .enable = sti_hda_bridge_nope,
520 .disable = sti_hda_disable,
521 .post_disable = sti_hda_bridge_nope,
522 .mode_set = sti_hda_set_mode,
523 .destroy = sti_hda_brigde_destroy,
526 static int sti_hda_connector_get_modes(struct drm_connector *connector)
530 struct sti_hda_connector *hda_connector
531 = to_sti_hda_connector(connector);
532 struct sti_hda *hda = hda_connector->hda;
534 DRM_DEBUG_DRIVER("\n");
536 for (i = 0; i < ARRAY_SIZE(hda_supported_modes); i++) {
537 struct drm_display_mode *mode =
538 drm_mode_duplicate(hda->drm_dev,
539 &hda_supported_modes[i].mode);
542 mode->vrefresh = drm_mode_vrefresh(mode);
544 /* the first mode is the preferred mode */
546 mode->type |= DRM_MODE_TYPE_PREFERRED;
548 drm_mode_probed_add(connector, mode);
552 drm_mode_sort(&connector->modes);
557 #define CLK_TOLERANCE_HZ 50
559 static int sti_hda_connector_mode_valid(struct drm_connector *connector,
560 struct drm_display_mode *mode)
562 int target = mode->clock * 1000;
563 int target_min = target - CLK_TOLERANCE_HZ;
564 int target_max = target + CLK_TOLERANCE_HZ;
567 struct sti_hda_connector *hda_connector
568 = to_sti_hda_connector(connector);
569 struct sti_hda *hda = hda_connector->hda;
571 if (!hda_get_mode_idx(*mode, &idx)) {
574 result = clk_round_rate(hda->clk_pix, target);
576 DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n",
579 if ((result < target_min) || (result > target_max)) {
580 DRM_DEBUG_DRIVER("hda pixclk=%d not supported\n",
589 struct drm_encoder *sti_hda_best_encoder(struct drm_connector *connector)
591 struct sti_hda_connector *hda_connector
592 = to_sti_hda_connector(connector);
594 /* Best encoder is the one associated during connector creation */
595 return hda_connector->encoder;
598 static struct drm_connector_helper_funcs sti_hda_connector_helper_funcs = {
599 .get_modes = sti_hda_connector_get_modes,
600 .mode_valid = sti_hda_connector_mode_valid,
601 .best_encoder = sti_hda_best_encoder,
604 static enum drm_connector_status
605 sti_hda_connector_detect(struct drm_connector *connector, bool force)
607 return connector_status_connected;
610 static void sti_hda_connector_destroy(struct drm_connector *connector)
612 struct sti_hda_connector *hda_connector
613 = to_sti_hda_connector(connector);
615 drm_connector_unregister(connector);
616 drm_connector_cleanup(connector);
617 kfree(hda_connector);
620 static struct drm_connector_funcs sti_hda_connector_funcs = {
621 .dpms = drm_helper_connector_dpms,
622 .fill_modes = drm_helper_probe_single_connector_modes,
623 .detect = sti_hda_connector_detect,
624 .destroy = sti_hda_connector_destroy,
627 static struct drm_encoder *sti_hda_find_encoder(struct drm_device *dev)
629 struct drm_encoder *encoder;
631 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
632 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC)
639 static int sti_hda_bind(struct device *dev, struct device *master, void *data)
641 struct sti_hda *hda = dev_get_drvdata(dev);
642 struct drm_device *drm_dev = data;
643 struct drm_encoder *encoder;
644 struct sti_hda_connector *connector;
645 struct drm_connector *drm_connector;
646 struct drm_bridge *bridge;
649 /* Set the drm device handle */
650 hda->drm_dev = drm_dev;
652 encoder = sti_hda_find_encoder(drm_dev);
656 connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL);
660 connector->hda = hda;
662 bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);
666 bridge->driver_private = hda;
667 drm_bridge_init(drm_dev, bridge, &sti_hda_bridge_funcs);
669 encoder->bridge = bridge;
670 connector->encoder = encoder;
672 drm_connector = (struct drm_connector *)connector;
674 drm_connector->polled = DRM_CONNECTOR_POLL_HPD;
676 drm_connector_init(drm_dev, drm_connector,
677 &sti_hda_connector_funcs, DRM_MODE_CONNECTOR_Component);
678 drm_connector_helper_add(drm_connector,
679 &sti_hda_connector_helper_funcs);
681 err = drm_connector_register(drm_connector);
685 err = drm_mode_connector_attach_encoder(drm_connector, encoder);
687 DRM_ERROR("Failed to attach a connector to a encoder\n");
694 drm_connector_unregister(drm_connector);
696 drm_bridge_cleanup(bridge);
697 drm_connector_cleanup(drm_connector);
701 static void sti_hda_unbind(struct device *dev,
702 struct device *master, void *data)
707 static const struct component_ops sti_hda_ops = {
708 .bind = sti_hda_bind,
709 .unbind = sti_hda_unbind,
712 static int sti_hda_probe(struct platform_device *pdev)
714 struct device *dev = &pdev->dev;
716 struct resource *res;
718 DRM_INFO("%s\n", __func__);
720 hda = devm_kzalloc(dev, sizeof(*hda), GFP_KERNEL);
724 hda->dev = pdev->dev;
727 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hda-reg");
729 DRM_ERROR("Invalid hda resource\n");
732 hda->regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
736 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
739 hda->video_dacs_ctrl = devm_ioremap_nocache(dev, res->start,
741 if (!hda->video_dacs_ctrl)
744 /* If no existing video-dacs-ctrl resource continue the probe */
745 DRM_DEBUG_DRIVER("No video-dacs-ctrl resource\n");
746 hda->video_dacs_ctrl = NULL;
749 /* Get clock resources */
750 hda->clk_pix = devm_clk_get(dev, "pix");
751 if (IS_ERR(hda->clk_pix)) {
752 DRM_ERROR("Cannot get hda_pix clock\n");
753 return PTR_ERR(hda->clk_pix);
756 hda->clk_hddac = devm_clk_get(dev, "hddac");
757 if (IS_ERR(hda->clk_hddac)) {
758 DRM_ERROR("Cannot get hda_hddac clock\n");
759 return PTR_ERR(hda->clk_hddac);
762 platform_set_drvdata(pdev, hda);
764 return component_add(&pdev->dev, &sti_hda_ops);
767 static int sti_hda_remove(struct platform_device *pdev)
769 component_del(&pdev->dev, &sti_hda_ops);
773 static const struct of_device_id hda_of_match[] = {
774 { .compatible = "st,stih416-hda", },
775 { .compatible = "st,stih407-hda", },
778 MODULE_DEVICE_TABLE(of, hda_of_match);
780 struct platform_driver sti_hda_driver = {
783 .owner = THIS_MODULE,
784 .of_match_table = hda_of_match,
786 .probe = sti_hda_probe,
787 .remove = sti_hda_remove,
790 module_platform_driver(sti_hda_driver);
792 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
793 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
794 MODULE_LICENSE("GPL");