2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #include <linux/kernel.h>
18 #include <linux/component.h>
20 #include "rockchip_drm_vop.h"
21 #include "rockchip_vop_reg.h"
23 #define VOP_REG_VER_MASK(off, _mask, s, _write_mask, _major, \
24 _begin_minor, _end_minor) \
28 .write_mask = _write_mask, \
30 .begin_minor = _begin_minor, \
31 .end_minor = _end_minor,}
33 #define VOP_REG(off, _mask, s) \
34 VOP_REG_VER_MASK(off, _mask, s, false, 0, 0, -1)
36 #define VOP_REG_MASK(off, _mask, s) \
37 VOP_REG_VER_MASK(off, _mask, s, true, 0, 0, -1)
39 #define VOP_REG_VER(off, _mask, s, _major, _begin_minor, _end_minor) \
40 VOP_REG_VER_MASK(off, _mask, s, false, \
41 _major, _begin_minor, _end_minor)
44 static const uint32_t formats_win_full[] = {
58 static const uint32_t formats_win_lite[] = {
69 static const struct vop_scl_extension rk3288_win_full_scl_ext = {
70 .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
71 .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
72 .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28),
73 .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26),
74 .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24),
75 .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23),
76 .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22),
77 .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20),
78 .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18),
79 .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16),
80 .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15),
81 .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12),
82 .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8),
83 .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7),
84 .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6),
85 .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5),
86 .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4),
87 .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2),
88 .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1),
89 .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0),
90 .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5),
93 static const struct vop_scl_regs rk3288_win_full_scl = {
94 .ext = &rk3288_win_full_scl_ext,
95 .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
96 .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
97 .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
98 .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
101 static const struct vop_win_phy rk3288_win01_data = {
102 .scl = &rk3288_win_full_scl,
103 .data_formats = formats_win_full,
104 .nformats = ARRAY_SIZE(formats_win_full),
105 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
106 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
107 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
108 .xmirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 21, 3, 2, -1),
109 .ymirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 22, 3, 2, -1),
110 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
111 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
112 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
113 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
114 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
115 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
116 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
117 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xffffffff, 0),
118 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xffffffff, 0),
121 static const struct vop_win_phy rk3288_win23_data = {
122 .data_formats = formats_win_lite,
123 .nformats = ARRAY_SIZE(formats_win_lite),
124 .gate = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
125 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4),
126 .format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
127 .rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
128 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
129 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0),
130 .yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0),
131 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0),
132 .src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
133 .dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0),
136 static const struct vop_win_phy rk3288_area1_data = {
137 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 5),
138 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO1, 0x0fff0fff, 0),
139 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST1, 0x1fff1fff, 0),
140 .yrgb_mst = VOP_REG(RK3288_WIN2_MST1, 0xffffffff, 0),
141 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 16),
144 static const struct vop_win_phy rk3288_area2_data = {
145 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 6),
146 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO2, 0x0fff0fff, 0),
147 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST2, 0x1fff1fff, 0),
148 .yrgb_mst = VOP_REG(RK3288_WIN2_MST2, 0xffffffff, 0),
149 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 0),
152 static const struct vop_win_phy rk3288_area3_data = {
153 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 7),
154 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO3, 0x0fff0fff, 0),
155 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST3, 0x1fff1fff, 0),
156 .yrgb_mst = VOP_REG(RK3288_WIN2_MST3, 0xffffffff, 0),
157 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 16),
160 static const struct vop_win_phy *rk3288_area_data[] = {
166 static const struct vop_ctrl rk3288_ctrl_data = {
167 .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
168 .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
169 .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
170 .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
171 .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
172 .vact_st_end_f1 = VOP_REG(RK3288_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
173 .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
174 .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
175 .vpost_st_end_f1 = VOP_REG(RK3288_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
176 .dsp_interlace = VOP_REG(RK3288_DSP_CTRL0, 0x1, 10),
177 .auto_gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
178 .dsp_layer_sel = VOP_REG(RK3288_DSP_CTRL1, 0xff, 8),
179 .post_lb_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 18, 3, 2, -1),
180 .global_regdone_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 2, -1),
181 .overlay_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 16, 3, 2, -1),
182 .core_dclk_div = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 4, 3, 4, -1),
183 .p2i_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 5, 3, 4, -1),
184 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
185 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
186 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
187 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
188 .pin_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0xf, 4, 3, 0, 1),
189 .rgb_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 16, 3, 2, -1),
190 .hdmi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 20, 3, 2, -1),
191 .edp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 24, 3, 2, -1),
192 .mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 28, 3, 2, -1),
194 .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
195 .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
197 .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12),
198 .dsp_ccir656_avg = VOP_REG(RK3288_DSP_CTRL0, 0x1, 20),
199 .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
200 .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0),
201 .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
203 .xmirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 22),
204 .ymirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 23),
206 .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0),
208 .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
212 * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
213 * special support to get alpha blending working. For now, just use overlay
214 * window 3 for the drm cursor.
217 static const struct vop_win_data rk3288_vop_win_data[] = {
218 { .base = 0x00, .phy = &rk3288_win01_data,
219 .type = DRM_PLANE_TYPE_PRIMARY },
220 { .base = 0x40, .phy = &rk3288_win01_data,
221 .type = DRM_PLANE_TYPE_OVERLAY },
222 { .base = 0x00, .phy = &rk3288_win23_data,
223 .type = DRM_PLANE_TYPE_OVERLAY,
224 .area = rk3288_area_data,
225 .area_size = ARRAY_SIZE(rk3288_area_data), },
226 { .base = 0x50, .phy = &rk3288_win23_data,
227 .type = DRM_PLANE_TYPE_CURSOR,
228 .area = rk3288_area_data,
229 .area_size = ARRAY_SIZE(rk3288_area_data), },
232 static const int rk3288_vop_intrs[] = {
239 static const struct vop_intr rk3288_vop_intr = {
240 .intrs = rk3288_vop_intrs,
241 .nintrs = ARRAY_SIZE(rk3288_vop_intrs),
242 .status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
243 .enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
244 .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
247 static const struct vop_data rk3288_vop = {
248 .version = VOP_VERSION(3, 1),
249 .feature = VOP_FEATURE_OUTPUT_10BIT,
250 .intr = &rk3288_vop_intr,
251 .ctrl = &rk3288_ctrl_data,
252 .win = rk3288_vop_win_data,
253 .win_size = ARRAY_SIZE(rk3288_vop_win_data),
256 static const int rk3368_vop_intrs[] = {
273 static const struct vop_intr rk3368_vop_intr = {
274 .intrs = rk3368_vop_intrs,
275 .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
276 .status = VOP_REG_MASK(RK3368_INTR_STATUS, 0x3fff, 0),
277 .enable = VOP_REG_MASK(RK3368_INTR_EN, 0x3fff, 0),
278 .clear = VOP_REG_MASK(RK3368_INTR_CLEAR, 0x3fff, 0),
281 static const struct vop_win_phy rk3368_win23_data = {
282 .data_formats = formats_win_lite,
283 .nformats = ARRAY_SIZE(formats_win_lite),
284 .gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0),
285 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4),
286 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5),
287 .ymirror = VOP_REG(RK3368_WIN2_CTRL1, 0x1, 15),
288 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20),
289 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0),
290 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0),
291 .yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0),
292 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0),
293 .src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
294 .dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xff, 0),
297 static const struct vop_win_phy rk3368_area1_data = {
298 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 8),
299 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 9),
300 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 23),
301 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO1, 0x0fff0fff, 0),
302 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST1, 0x1fff1fff, 0),
303 .yrgb_mst = VOP_REG(RK3368_WIN2_MST1, 0xffffffff, 0),
304 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 16),
307 static const struct vop_win_phy rk3368_area2_data = {
308 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 12),
309 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 13),
310 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 26),
311 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO2, 0x0fff0fff, 0),
312 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST2, 0x1fff1fff, 0),
313 .yrgb_mst = VOP_REG(RK3368_WIN2_MST2, 0xffffffff, 0),
314 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR2_3, 0x1fff, 0),
317 static const struct vop_win_phy rk3368_area3_data = {
318 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 16),
319 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 17),
320 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 29),
321 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO3, 0x0fff0fff, 0),
322 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST3, 0x1fff1fff, 0),
323 .yrgb_mst = VOP_REG(RK3368_WIN2_MST3, 0xffffffff, 0),
324 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR2_3, 0x1fff, 16),
327 static const struct vop_win_phy *rk3368_area_data[] = {
333 static const struct vop_win_data rk3368_vop_win_data[] = {
334 { .base = 0x00, .phy = &rk3288_win01_data,
335 .type = DRM_PLANE_TYPE_PRIMARY },
336 { .base = 0x40, .phy = &rk3288_win01_data,
337 .type = DRM_PLANE_TYPE_OVERLAY },
338 { .base = 0x00, .phy = &rk3368_win23_data,
339 .type = DRM_PLANE_TYPE_OVERLAY,
340 .area = rk3368_area_data,
341 .area_size = ARRAY_SIZE(rk3368_area_data), },
342 { .base = 0x50, .phy = &rk3368_win23_data,
343 .type = DRM_PLANE_TYPE_CURSOR,
344 .area = rk3368_area_data,
345 .area_size = ARRAY_SIZE(rk3368_area_data), },
348 static const struct vop_data rk3368_vop = {
349 .version = VOP_VERSION(3, 2),
350 .feature = VOP_FEATURE_OUTPUT_10BIT,
351 .intr = &rk3368_vop_intr,
352 .ctrl = &rk3288_ctrl_data,
353 .win = rk3368_vop_win_data,
354 .win_size = ARRAY_SIZE(rk3368_vop_win_data),
357 static const struct vop_intr rk3366_vop_intr = {
358 .intrs = rk3368_vop_intrs,
359 .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
360 .status = VOP_REG_MASK(RK3366_INTR_STATUS0, 0xffff, 0),
361 .enable = VOP_REG_MASK(RK3366_INTR_EN0, 0xffff, 0),
362 .clear = VOP_REG_MASK(RK3366_INTR_CLEAR0, 0xffff, 0),
365 static const struct vop_data rk3366_vop = {
366 .version = VOP_VERSION(3, 4),
367 .feature = VOP_FEATURE_OUTPUT_10BIT,
368 .intr = &rk3366_vop_intr,
369 .ctrl = &rk3288_ctrl_data,
370 .win = rk3368_vop_win_data,
371 .win_size = ARRAY_SIZE(rk3368_vop_win_data),
374 static const struct vop_data rk3399_vop_big = {
375 .version = VOP_VERSION(3, 5),
376 .feature = VOP_FEATURE_OUTPUT_10BIT,
377 .intr = &rk3366_vop_intr,
378 .ctrl = &rk3288_ctrl_data,
379 .win = rk3368_vop_win_data,
380 .win_size = ARRAY_SIZE(rk3368_vop_win_data),
383 static const struct vop_win_data rk3399_vop_lit_win_data[] = {
384 { .base = 0x00, .phy = &rk3288_win01_data,
385 .type = DRM_PLANE_TYPE_PRIMARY },
387 { .base = 0x00, .phy = &rk3368_win23_data,
388 .type = DRM_PLANE_TYPE_CURSOR,
389 .area = rk3368_area_data,
390 .area_size = ARRAY_SIZE(rk3368_area_data), },
395 static const struct vop_data rk3399_vop_lit = {
396 .version = VOP_VERSION(3, 6),
397 .intr = &rk3366_vop_intr,
398 .ctrl = &rk3288_ctrl_data,
399 .win = rk3399_vop_lit_win_data,
400 .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data),
403 static const struct vop_data rk322x_vop = {
404 .version = VOP_VERSION(3, 7),
405 .feature = VOP_FEATURE_OUTPUT_10BIT,
406 .intr = &rk3366_vop_intr,
407 .ctrl = &rk3288_ctrl_data,
408 .win = rk3368_vop_win_data,
409 .win_size = ARRAY_SIZE(rk3368_vop_win_data),
412 static const struct vop_scl_regs rk3066_win_scl = {
413 .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
414 .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
415 .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
416 .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
419 static const struct vop_win_phy rk3036_win0_data = {
420 .scl = &rk3066_win_scl,
421 .data_formats = formats_win_full,
422 .nformats = ARRAY_SIZE(formats_win_full),
423 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
424 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
425 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
426 .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
427 .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
428 .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
429 .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
430 .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
431 .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
432 .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16),
433 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 18),
434 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0)
437 static const struct vop_win_phy rk3036_win1_data = {
438 .data_formats = formats_win_lite,
439 .nformats = ARRAY_SIZE(formats_win_lite),
440 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
441 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
442 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
443 .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
444 .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
445 .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
446 .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
447 .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
448 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 19),
449 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1)
452 static const struct vop_win_data rk3036_vop_win_data[] = {
453 { .base = 0x00, .phy = &rk3036_win0_data,
454 .type = DRM_PLANE_TYPE_PRIMARY },
455 { .base = 0x00, .phy = &rk3036_win1_data,
456 .type = DRM_PLANE_TYPE_CURSOR },
459 static const int rk3036_vop_intrs[] = {
466 static const struct vop_intr rk3036_intr = {
467 .intrs = rk3036_vop_intrs,
468 .nintrs = ARRAY_SIZE(rk3036_vop_intrs),
469 .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
470 .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
471 .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
474 static const struct vop_ctrl rk3036_ctrl_data = {
475 .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
476 .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
477 .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
478 .dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8),
479 .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
480 .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
481 .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
482 .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
483 .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
486 static const struct vop_data rk3036_vop = {
487 .version = VOP_VERSION(2, 2),
488 .ctrl = &rk3036_ctrl_data,
489 .intr = &rk3036_intr,
490 .win = rk3036_vop_win_data,
491 .win_size = ARRAY_SIZE(rk3036_vop_win_data),
494 static const struct of_device_id vop_driver_dt_match[] = {
495 { .compatible = "rockchip,rk3036-vop",
496 .data = &rk3036_vop },
497 { .compatible = "rockchip,rk3288-vop",
498 .data = &rk3288_vop },
499 { .compatible = "rockchip,rk3368-vop",
500 .data = &rk3368_vop },
501 { .compatible = "rockchip,rk3366-vop",
502 .data = &rk3366_vop },
503 { .compatible = "rockchip,rk3399-vop-big",
504 .data = &rk3399_vop_big },
505 { .compatible = "rockchip,rk3399-vop-lit",
506 .data = &rk3399_vop_lit },
507 { .compatible = "rockchip,rk322x-vop",
508 .data = &rk322x_vop },
511 MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
513 static int vop_probe(struct platform_device *pdev)
515 struct device *dev = &pdev->dev;
518 dev_err(dev, "can't find vop devices\n");
522 return component_add(dev, &vop_component_ops);
525 static int vop_remove(struct platform_device *pdev)
527 component_del(&pdev->dev, &vop_component_ops);
532 struct platform_driver vop_platform_driver = {
534 .remove = vop_remove,
536 .name = "rockchip-vop",
537 .owner = THIS_MODULE,
538 .of_match_table = of_match_ptr(vop_driver_dt_match),
542 module_platform_driver(vop_platform_driver);
544 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
545 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
546 MODULE_LICENSE("GPL v2");