2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #include <linux/kernel.h>
18 #include <linux/component.h>
20 #include "rockchip_drm_vop.h"
21 #include "rockchip_vop_reg.h"
23 #define VOP_REG(off, _mask, s) \
29 #define VOP_REG_MASK(off, _mask, s) \
35 static const uint32_t formats_win_full[] = {
49 static const uint32_t formats_win_lite[] = {
60 static const struct vop_scl_extension rk3288_win_full_scl_ext = {
61 .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
62 .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
63 .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28),
64 .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26),
65 .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24),
66 .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23),
67 .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22),
68 .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20),
69 .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18),
70 .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16),
71 .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15),
72 .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12),
73 .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8),
74 .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7),
75 .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6),
76 .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5),
77 .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4),
78 .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2),
79 .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1),
80 .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0),
81 .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5),
84 static const struct vop_scl_regs rk3288_win_full_scl = {
85 .ext = &rk3288_win_full_scl_ext,
86 .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
87 .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
88 .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
89 .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
92 static const struct vop_win_phy rk3288_win01_data = {
93 .scl = &rk3288_win_full_scl,
94 .data_formats = formats_win_full,
95 .nformats = ARRAY_SIZE(formats_win_full),
96 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
97 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
98 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
99 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
100 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
101 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
102 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
103 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
104 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
105 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
106 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
107 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
110 static const struct vop_win_phy rk3288_win23_data = {
111 .data_formats = formats_win_lite,
112 .nformats = ARRAY_SIZE(formats_win_lite),
113 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
114 .format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
115 .rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
116 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
117 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0),
118 .yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0),
119 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0),
120 .src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
121 .dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0),
124 static const struct vop_ctrl rk3288_ctrl_data = {
125 .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
126 .gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
127 .mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20),
128 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
129 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
130 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
131 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
132 .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
133 .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
134 .data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19),
135 .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
136 .pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),
137 .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
138 .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
139 .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
140 .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
141 .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
142 .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
143 .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
146 static const struct vop_reg_data rk3288_init_reg_table[] = {
147 {RK3288_SYS_CTRL, 0x00c00000},
148 {RK3288_DSP_CTRL0, 0x00000000},
149 {RK3288_WIN0_CTRL0, 0x00000080},
150 {RK3288_WIN1_CTRL0, 0x00000080},
151 /* TODO: Win2/3 support multiple area function, but we haven't found
152 * a suitable way to use it yet, so let's just use them as other windows
153 * with only area 0 enabled.
155 {RK3288_WIN2_CTRL0, 0x00000010},
156 {RK3288_WIN3_CTRL0, 0x00000010},
160 * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
161 * special support to get alpha blending working. For now, just use overlay
162 * window 3 for the drm cursor.
165 static const struct vop_win_data rk3288_vop_win_data[] = {
166 { .base = 0x00, .phy = &rk3288_win01_data,
167 .type = DRM_PLANE_TYPE_PRIMARY },
168 { .base = 0x40, .phy = &rk3288_win01_data,
169 .type = DRM_PLANE_TYPE_OVERLAY },
170 { .base = 0x00, .phy = &rk3288_win23_data,
171 .type = DRM_PLANE_TYPE_OVERLAY },
172 { .base = 0x50, .phy = &rk3288_win23_data,
173 .type = DRM_PLANE_TYPE_CURSOR },
176 static const int rk3288_vop_intrs[] = {
183 static const struct vop_intr rk3288_vop_intr = {
184 .intrs = rk3288_vop_intrs,
185 .nintrs = ARRAY_SIZE(rk3288_vop_intrs),
186 .status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
187 .enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
188 .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
191 static const struct vop_data rk3288_vop = {
192 .init_table = rk3288_init_reg_table,
193 .table_size = ARRAY_SIZE(rk3288_init_reg_table),
194 .intr = &rk3288_vop_intr,
195 .ctrl = &rk3288_ctrl_data,
196 .win = rk3288_vop_win_data,
197 .win_size = ARRAY_SIZE(rk3288_vop_win_data),
200 static const struct vop_ctrl rk3399_ctrl_data = {
201 .standby = VOP_REG(RK3399_SYS_CTRL, 0x1, 22),
202 .gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23),
203 .rgb_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 12),
204 .hdmi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 13),
205 .edp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 14),
206 .mipi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 15),
207 .dither_down = VOP_REG(RK3399_DSP_CTRL1, 0xf, 1),
208 .dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6),
209 .data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19),
210 .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0),
211 .rgb_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16),
212 .hdmi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 20),
213 .edp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 24),
214 .mipi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 28),
215 .htotal_pw = VOP_REG(RK3399_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
216 .hact_st_end = VOP_REG(RK3399_DSP_HACT_ST_END, 0x1fff1fff, 0),
217 .vtotal_pw = VOP_REG(RK3399_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
218 .vact_st_end = VOP_REG(RK3399_DSP_VACT_ST_END, 0x1fff1fff, 0),
219 .hpost_st_end = VOP_REG(RK3399_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
220 .vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
221 .cfg_done = VOP_REG_MASK(RK3399_REG_CFG_DONE, 0x1, 0),
224 static const int rk3399_vop_intrs[] = {
234 static const struct vop_intr rk3399_vop_intr = {
235 .intrs = rk3399_vop_intrs,
236 .nintrs = ARRAY_SIZE(rk3399_vop_intrs),
237 .status = VOP_REG_MASK(RK3399_INTR_STATUS0, 0xffff, 0),
238 .enable = VOP_REG_MASK(RK3399_INTR_EN0, 0xffff, 0),
239 .clear = VOP_REG_MASK(RK3399_INTR_CLEAR0, 0xffff, 0),
242 static const struct vop_reg_data rk3399_init_reg_table[] = {
243 {RK3399_SYS_CTRL, 0x2000f800},
244 {RK3399_DSP_CTRL0, 0x00000000},
245 {RK3399_WIN0_CTRL0, 0x00000080},
246 {RK3399_WIN1_CTRL0, 0x00000080},
247 /* TODO: Win2/3 support multiple area function, but we haven't found
248 * a suitable way to use it yet, so let's just use them as other windows
249 * with only area 0 enabled.
251 {RK3399_WIN2_CTRL0, 0x00000010},
252 {RK3399_WIN3_CTRL0, 0x00000010},
255 static const struct vop_data rk3399_vop_big = {
256 .init_table = rk3399_init_reg_table,
257 .table_size = ARRAY_SIZE(rk3399_init_reg_table),
258 .intr = &rk3399_vop_intr,
259 .ctrl = &rk3399_ctrl_data,
261 * rk3399 vop big windows register layout is same as rk3288.
263 .win = rk3288_vop_win_data,
264 .win_size = ARRAY_SIZE(rk3288_vop_win_data),
267 static const struct vop_win_data rk3399_vop_lit_win_data[] = {
268 { .base = 0x00, .phy = &rk3288_win01_data,
269 .type = DRM_PLANE_TYPE_PRIMARY },
270 { .base = 0x00, .phy = &rk3288_win23_data,
271 .type = DRM_PLANE_TYPE_CURSOR},
275 static const struct vop_data rk3399_vop_lit = {
276 .init_table = rk3399_init_reg_table,
277 .table_size = ARRAY_SIZE(rk3399_init_reg_table),
278 .intr = &rk3399_vop_intr,
279 .ctrl = &rk3399_ctrl_data,
281 * rk3399 vop lit windows register layout is same as rk3288,
282 * but cut off the win1 and win3 windows.
284 .win = rk3399_vop_lit_win_data,
285 .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data),
288 static const struct vop_scl_regs rk3066_win_scl = {
289 .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
290 .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
291 .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
292 .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
295 static const struct vop_win_phy rk3036_win0_data = {
296 .scl = &rk3066_win_scl,
297 .data_formats = formats_win_full,
298 .nformats = ARRAY_SIZE(formats_win_full),
299 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
300 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
301 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
302 .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
303 .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
304 .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
305 .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
306 .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
307 .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
310 static const struct vop_win_phy rk3036_win1_data = {
311 .data_formats = formats_win_lite,
312 .nformats = ARRAY_SIZE(formats_win_lite),
313 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
314 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
315 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
316 .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
317 .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
318 .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
319 .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
320 .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
323 static const struct vop_win_data rk3036_vop_win_data[] = {
324 { .base = 0x00, .phy = &rk3036_win0_data,
325 .type = DRM_PLANE_TYPE_PRIMARY },
326 { .base = 0x00, .phy = &rk3036_win1_data,
327 .type = DRM_PLANE_TYPE_CURSOR },
330 static const int rk3036_vop_intrs[] = {
337 static const struct vop_intr rk3036_intr = {
338 .intrs = rk3036_vop_intrs,
339 .nintrs = ARRAY_SIZE(rk3036_vop_intrs),
340 .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
341 .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
342 .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
345 static const struct vop_ctrl rk3036_ctrl_data = {
346 .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
347 .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
348 .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
349 .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
350 .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
351 .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
352 .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
353 .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
356 static const struct vop_reg_data rk3036_vop_init_reg_table[] = {
357 {RK3036_DSP_CTRL1, 0x00000000},
360 static const struct vop_data rk3036_vop = {
361 .init_table = rk3036_vop_init_reg_table,
362 .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table),
363 .ctrl = &rk3036_ctrl_data,
364 .intr = &rk3036_intr,
365 .win = rk3036_vop_win_data,
366 .win_size = ARRAY_SIZE(rk3036_vop_win_data),
369 static const struct of_device_id vop_driver_dt_match[] = {
370 { .compatible = "rockchip,rk3288-vop",
371 .data = &rk3288_vop },
372 { .compatible = "rockchip,rk3036-vop",
373 .data = &rk3036_vop },
374 { .compatible = "rockchip,rk3399-vop-big",
375 .data = &rk3399_vop_big },
376 { .compatible = "rockchip,rk3399-vop-lit",
377 .data = &rk3399_vop_lit },
380 MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
382 static int vop_probe(struct platform_device *pdev)
384 struct device *dev = &pdev->dev;
387 dev_err(dev, "can't find vop devices\n");
391 return component_add(dev, &vop_component_ops);
394 static int vop_remove(struct platform_device *pdev)
396 component_del(&pdev->dev, &vop_component_ops);
401 struct platform_driver vop_platform_driver = {
403 .remove = vop_remove,
405 .name = "rockchip-vop",
406 .owner = THIS_MODULE,
407 .of_match_table = of_match_ptr(vop_driver_dt_match),
411 module_platform_driver(vop_platform_driver);
413 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
414 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
415 MODULE_LICENSE("GPL v2");