2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #include <linux/kernel.h>
18 #include <linux/component.h>
20 #include "rockchip_drm_vop.h"
21 #include "rockchip_vop_reg.h"
23 #define VOP_REG_VER_MASK(off, _mask, s, _write_mask, _major, \
24 _begin_minor, _end_minor) \
28 .write_mask = _write_mask, \
30 .begin_minor = _begin_minor, \
31 .end_minor = _end_minor,}
33 #define VOP_REG(off, _mask, s) \
34 VOP_REG_VER_MASK(off, _mask, s, false, 0, 0, -1)
36 #define VOP_REG_MASK(off, _mask, s) \
37 VOP_REG_VER_MASK(off, _mask, s, true, 0, 0, -1)
39 #define VOP_REG_VER(off, _mask, s, _major, _begin_minor, _end_minor) \
40 VOP_REG_VER_MASK(off, _mask, s, false, \
41 _major, _begin_minor, _end_minor)
44 static const uint32_t formats_win_full[] = {
58 static const uint32_t formats_win_lite[] = {
69 static const struct vop_scl_extension rk3288_win_full_scl_ext = {
70 .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
71 .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
72 .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28),
73 .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26),
74 .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24),
75 .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23),
76 .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22),
77 .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20),
78 .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18),
79 .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16),
80 .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15),
81 .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12),
82 .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8),
83 .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7),
84 .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6),
85 .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5),
86 .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4),
87 .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2),
88 .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1),
89 .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0),
90 .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5),
93 static const struct vop_scl_regs rk3288_win_full_scl = {
94 .ext = &rk3288_win_full_scl_ext,
95 .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
96 .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
97 .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
98 .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
101 static const struct vop_win_phy rk3288_win01_data = {
102 .scl = &rk3288_win_full_scl,
103 .data_formats = formats_win_full,
104 .nformats = ARRAY_SIZE(formats_win_full),
105 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
106 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
107 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
108 .xmirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 21, 3, 2, -1),
109 .ymirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 22, 3, 2, -1),
110 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
111 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
112 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
113 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
114 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
115 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
116 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
117 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xffffffff, 0),
118 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xffffffff, 0),
121 static const struct vop_win_phy rk3288_win23_data = {
122 .data_formats = formats_win_lite,
123 .nformats = ARRAY_SIZE(formats_win_lite),
124 .gate = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
125 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4),
126 .format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
127 .rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
128 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
129 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0),
130 .yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0),
131 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0),
132 .src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
133 .dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0),
136 static const struct vop_win_phy rk3288_area1_data = {
137 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 5),
138 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO1, 0x0fff0fff, 0),
139 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST1, 0x1fff1fff, 0),
140 .yrgb_mst = VOP_REG(RK3288_WIN2_MST1, 0xffffffff, 0),
141 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 16),
144 static const struct vop_win_phy rk3288_area2_data = {
145 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 6),
146 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO2, 0x0fff0fff, 0),
147 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST2, 0x1fff1fff, 0),
148 .yrgb_mst = VOP_REG(RK3288_WIN2_MST2, 0xffffffff, 0),
149 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 0),
152 static const struct vop_win_phy rk3288_area3_data = {
153 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 7),
154 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO3, 0x0fff0fff, 0),
155 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST3, 0x1fff1fff, 0),
156 .yrgb_mst = VOP_REG(RK3288_WIN2_MST3, 0xffffffff, 0),
157 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 16),
160 static const struct vop_win_phy *rk3288_area_data[] = {
166 static const struct vop_ctrl rk3288_ctrl_data = {
167 .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
168 .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
169 .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
170 .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
171 .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
172 .vact_st_end_f1 = VOP_REG(RK3288_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
173 .vs_st_end_f1 = VOP_REG(RK3288_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
174 .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
175 .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
176 .vpost_st_end_f1 = VOP_REG(RK3288_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
177 .dsp_interlace = VOP_REG(RK3288_DSP_CTRL0, 0x1, 10),
178 .auto_gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
179 .dsp_layer_sel = VOP_REG(RK3288_DSP_CTRL1, 0xff, 8),
180 .post_lb_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 18, 3, 2, -1),
181 .global_regdone_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 2, -1),
182 .overlay_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 16, 3, 2, -1),
183 .core_dclk_div = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 4, 3, 4, -1),
184 .p2i_en = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 5, 3, 4, -1),
185 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
186 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
187 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
188 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
189 .pin_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0xf, 4, 3, 0, 1),
190 .rgb_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 16, 3, 2, -1),
191 .hdmi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 20, 3, 2, -1),
192 .edp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 24, 3, 2, -1),
193 .mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 28, 3, 2, -1),
195 .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
196 .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
198 .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12),
199 .dsp_ccir656_avg = VOP_REG(RK3288_DSP_CTRL0, 0x1, 20),
200 .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
201 .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0),
202 .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
204 .xmirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 22),
205 .ymirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 23),
207 .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0),
209 .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
213 * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
214 * special support to get alpha blending working. For now, just use overlay
215 * window 3 for the drm cursor.
218 static const struct vop_win_data rk3288_vop_win_data[] = {
219 { .base = 0x00, .phy = &rk3288_win01_data,
220 .type = DRM_PLANE_TYPE_PRIMARY },
221 { .base = 0x40, .phy = &rk3288_win01_data,
222 .type = DRM_PLANE_TYPE_OVERLAY },
223 { .base = 0x00, .phy = &rk3288_win23_data,
224 .type = DRM_PLANE_TYPE_OVERLAY,
225 .area = rk3288_area_data,
226 .area_size = ARRAY_SIZE(rk3288_area_data), },
227 { .base = 0x50, .phy = &rk3288_win23_data,
228 .type = DRM_PLANE_TYPE_CURSOR,
229 .area = rk3288_area_data,
230 .area_size = ARRAY_SIZE(rk3288_area_data), },
233 static const int rk3288_vop_intrs[] = {
240 static const struct vop_intr rk3288_vop_intr = {
241 .intrs = rk3288_vop_intrs,
242 .nintrs = ARRAY_SIZE(rk3288_vop_intrs),
243 .status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
244 .enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
245 .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
248 static const struct vop_data rk3288_vop = {
249 .version = VOP_VERSION(3, 1),
250 .feature = VOP_FEATURE_OUTPUT_10BIT,
251 .intr = &rk3288_vop_intr,
252 .ctrl = &rk3288_ctrl_data,
253 .win = rk3288_vop_win_data,
254 .win_size = ARRAY_SIZE(rk3288_vop_win_data),
257 static const int rk3368_vop_intrs[] = {
274 static const struct vop_intr rk3368_vop_intr = {
275 .intrs = rk3368_vop_intrs,
276 .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
277 .status = VOP_REG_MASK(RK3368_INTR_STATUS, 0x3fff, 0),
278 .enable = VOP_REG_MASK(RK3368_INTR_EN, 0x3fff, 0),
279 .clear = VOP_REG_MASK(RK3368_INTR_CLEAR, 0x3fff, 0),
282 static const struct vop_win_phy rk3368_win23_data = {
283 .data_formats = formats_win_lite,
284 .nformats = ARRAY_SIZE(formats_win_lite),
285 .gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0),
286 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4),
287 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5),
288 .ymirror = VOP_REG(RK3368_WIN2_CTRL1, 0x1, 15),
289 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20),
290 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0),
291 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0),
292 .yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0),
293 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0),
294 .src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
295 .dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xff, 0),
298 static const struct vop_win_phy rk3368_area1_data = {
299 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 8),
300 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 9),
301 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 23),
302 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO1, 0x0fff0fff, 0),
303 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST1, 0x1fff1fff, 0),
304 .yrgb_mst = VOP_REG(RK3368_WIN2_MST1, 0xffffffff, 0),
305 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 16),
308 static const struct vop_win_phy rk3368_area2_data = {
309 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 12),
310 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 13),
311 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 26),
312 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO2, 0x0fff0fff, 0),
313 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST2, 0x1fff1fff, 0),
314 .yrgb_mst = VOP_REG(RK3368_WIN2_MST2, 0xffffffff, 0),
315 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR2_3, 0x1fff, 0),
318 static const struct vop_win_phy rk3368_area3_data = {
319 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 16),
320 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 17),
321 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 29),
322 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO3, 0x0fff0fff, 0),
323 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST3, 0x1fff1fff, 0),
324 .yrgb_mst = VOP_REG(RK3368_WIN2_MST3, 0xffffffff, 0),
325 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR2_3, 0x1fff, 16),
328 static const struct vop_win_phy *rk3368_area_data[] = {
334 static const struct vop_win_data rk3368_vop_win_data[] = {
335 { .base = 0x00, .phy = &rk3288_win01_data,
336 .type = DRM_PLANE_TYPE_PRIMARY },
337 { .base = 0x40, .phy = &rk3288_win01_data,
338 .type = DRM_PLANE_TYPE_OVERLAY },
339 { .base = 0x00, .phy = &rk3368_win23_data,
340 .type = DRM_PLANE_TYPE_OVERLAY,
341 .area = rk3368_area_data,
342 .area_size = ARRAY_SIZE(rk3368_area_data), },
343 { .base = 0x50, .phy = &rk3368_win23_data,
344 .type = DRM_PLANE_TYPE_CURSOR,
345 .area = rk3368_area_data,
346 .area_size = ARRAY_SIZE(rk3368_area_data), },
349 static const struct vop_data rk3368_vop = {
350 .version = VOP_VERSION(3, 2),
351 .feature = VOP_FEATURE_OUTPUT_10BIT,
352 .intr = &rk3368_vop_intr,
353 .ctrl = &rk3288_ctrl_data,
354 .win = rk3368_vop_win_data,
355 .win_size = ARRAY_SIZE(rk3368_vop_win_data),
358 static const struct vop_intr rk3366_vop_intr = {
359 .intrs = rk3368_vop_intrs,
360 .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
361 .status = VOP_REG_MASK(RK3366_INTR_STATUS0, 0xffff, 0),
362 .enable = VOP_REG_MASK(RK3366_INTR_EN0, 0xffff, 0),
363 .clear = VOP_REG_MASK(RK3366_INTR_CLEAR0, 0xffff, 0),
366 static const struct vop_data rk3366_vop = {
367 .version = VOP_VERSION(3, 4),
368 .feature = VOP_FEATURE_OUTPUT_10BIT,
369 .intr = &rk3366_vop_intr,
370 .ctrl = &rk3288_ctrl_data,
371 .win = rk3368_vop_win_data,
372 .win_size = ARRAY_SIZE(rk3368_vop_win_data),
375 static const uint32_t vop_csc_y2r_bt601[] = {
376 0x00000400, 0x0400059c, 0xfd25fea0, 0x07170400,
377 0x00000000, 0xfffecab4, 0x00087932, 0xfff1d4f2,
380 static const uint32_t vop_csc_y2r_bt601_12_235[] = {
381 0x000004a8, 0x04a80662, 0xfcbffe6f, 0x081204a8,
382 0x00000000, 0xfff2134e, 0x00087b58, 0xffeeb4b0,
385 static const uint32_t vop_csc_r2y_bt601[] = {
386 0x02590132, 0xff530075, 0x0200fead, 0xfe530200,
387 0x0000ffad, 0x00000200, 0x00080200, 0x00080200,
390 static const uint32_t vop_csc_r2y_bt601_12_235[] = {
391 0x02040107, 0xff680064, 0x01c2fed6, 0xffb7fe87,
392 0x0000ffb7, 0x00010200, 0x00080200, 0x00080200,
395 static const uint32_t vop_csc_y2r_bt709[] = {
396 0x000004a8, 0x04a8072c, 0xfddeff26, 0x087304a8,
397 0x00000000, 0xfff08077, 0x0004cfed, 0xffedf1b8,
400 static const uint32_t vop_csc_r2y_bt709[] = {
401 0x027500bb, 0xff99003f, 0x01c2fea5, 0xfe6801c2,
402 0xffd7fe68, 0x00010200, 0x00080200, 0x00080200,
405 static const uint32_t vop_csc_y2r_bt2020[] = {
406 0x000004a8, 0x04a806b6, 0xfd66ff40, 0x089004a8,
407 0x00000000, 0xfff16bfc, 0x00058ae9, 0xffedb828,
410 static const uint32_t vop_csc_r2y_bt2020[] = {
411 0x025300e6, 0xff830034, 0x01c1febd, 0xfe6401c1,
412 0x0000ffdc, 0x00010200, 0x00080200, 0x00080200,
415 static const uint32_t vop_csc_r2r_bt709_to_bt2020[] = {
416 0xfda606a4, 0xff80ffb5, 0xfff80488, 0xff99ffed,
417 0x0000047a, 0x00000200, 0x00000200, 0x00000200,
420 static const uint32_t vop_csc_r2r_bt2020_to_bt709[] = {
421 0x01510282, 0x0047002c, 0x000c03ae, 0x005a0011,
422 0x00000394, 0x00000200, 0x00000200, 0x00000200,
425 static const struct vop_csc_table rk3399_csc_table = {
426 .y2r_bt601 = vop_csc_y2r_bt601,
427 .y2r_bt601_12_235 = vop_csc_y2r_bt601_12_235,
428 .r2y_bt601 = vop_csc_r2y_bt601,
429 .r2y_bt601_12_235 = vop_csc_r2y_bt601_12_235,
431 .y2r_bt709 = vop_csc_y2r_bt709,
432 .r2y_bt709 = vop_csc_r2y_bt709,
434 .y2r_bt2020 = vop_csc_y2r_bt2020,
435 .r2y_bt2020 = vop_csc_r2y_bt2020,
437 .r2r_bt709_to_bt2020 = vop_csc_r2r_bt709_to_bt2020,
438 .r2r_bt2020_to_bt709 = vop_csc_r2r_bt2020_to_bt709,
441 static const struct vop_csc rk3399_win0_csc = {
442 .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 0),
443 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1),
444 .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 2),
445 .y2r_offset = RK3399_WIN0_YUV2YUV_Y2R,
446 .r2r_offset = RK3399_WIN0_YUV2YUV_3X3,
447 .r2y_offset = RK3399_WIN0_YUV2YUV_R2Y,
450 static const struct vop_csc rk3399_win1_csc = {
451 .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 8),
452 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 9),
453 .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 10),
454 .y2r_offset = RK3399_WIN1_YUV2YUV_Y2R,
455 .r2r_offset = RK3399_WIN1_YUV2YUV_3X3,
456 .r2y_offset = RK3399_WIN1_YUV2YUV_R2Y,
459 static const struct vop_win_data rk3399_vop_win_data[] = {
460 { .base = 0x00, .phy = &rk3288_win01_data, .csc = &rk3399_win0_csc,
461 .type = DRM_PLANE_TYPE_PRIMARY },
462 { .base = 0x40, .phy = &rk3288_win01_data, .csc = &rk3399_win1_csc,
463 .type = DRM_PLANE_TYPE_OVERLAY },
464 { .base = 0x00, .phy = &rk3368_win23_data,
465 .type = DRM_PLANE_TYPE_OVERLAY,
466 .area = rk3368_area_data,
467 .area_size = ARRAY_SIZE(rk3368_area_data), },
468 { .base = 0x50, .phy = &rk3368_win23_data,
469 .type = DRM_PLANE_TYPE_CURSOR,
470 .area = rk3368_area_data,
471 .area_size = ARRAY_SIZE(rk3368_area_data), },
474 static const struct vop_data rk3399_vop_big = {
475 .version = VOP_VERSION(3, 5),
476 .feature = VOP_FEATURE_OUTPUT_10BIT,
477 .intr = &rk3366_vop_intr,
478 .ctrl = &rk3288_ctrl_data,
479 .win = rk3399_vop_win_data,
480 .win_size = ARRAY_SIZE(rk3399_vop_win_data),
483 static const struct vop_win_data rk3399_vop_lit_win_data[] = {
484 { .base = 0x00, .phy = &rk3288_win01_data, .csc = &rk3399_win0_csc,
485 .type = DRM_PLANE_TYPE_PRIMARY },
487 { .base = 0x00, .phy = &rk3368_win23_data,
488 .type = DRM_PLANE_TYPE_CURSOR,
489 .area = rk3368_area_data,
490 .area_size = ARRAY_SIZE(rk3368_area_data), },
495 static const struct vop_data rk3399_vop_lit = {
496 .version = VOP_VERSION(3, 6),
497 .csc_table = &rk3399_csc_table,
498 .intr = &rk3366_vop_intr,
499 .ctrl = &rk3288_ctrl_data,
500 .win = rk3399_vop_lit_win_data,
501 .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data),
504 static const struct vop_data rk322x_vop = {
505 .version = VOP_VERSION(3, 7),
506 .feature = VOP_FEATURE_OUTPUT_10BIT,
507 .intr = &rk3366_vop_intr,
508 .ctrl = &rk3288_ctrl_data,
509 .win = rk3368_vop_win_data,
510 .win_size = ARRAY_SIZE(rk3368_vop_win_data),
513 static const struct vop_scl_regs rk3066_win_scl = {
514 .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
515 .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
516 .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
517 .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
520 static const struct vop_win_phy rk3036_win0_data = {
521 .scl = &rk3066_win_scl,
522 .data_formats = formats_win_full,
523 .nformats = ARRAY_SIZE(formats_win_full),
524 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
525 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
526 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
527 .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
528 .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
529 .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
530 .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
531 .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
532 .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
533 .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16),
534 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 18),
535 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0)
538 static const struct vop_win_phy rk3036_win1_data = {
539 .data_formats = formats_win_lite,
540 .nformats = ARRAY_SIZE(formats_win_lite),
541 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
542 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
543 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
544 .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
545 .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
546 .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
547 .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
548 .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
549 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 19),
550 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1)
553 static const struct vop_win_data rk3036_vop_win_data[] = {
554 { .base = 0x00, .phy = &rk3036_win0_data,
555 .type = DRM_PLANE_TYPE_PRIMARY },
556 { .base = 0x00, .phy = &rk3036_win1_data,
557 .type = DRM_PLANE_TYPE_CURSOR },
560 static const int rk3036_vop_intrs[] = {
567 static const struct vop_intr rk3036_intr = {
568 .intrs = rk3036_vop_intrs,
569 .nintrs = ARRAY_SIZE(rk3036_vop_intrs),
570 .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
571 .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
572 .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
575 static const struct vop_ctrl rk3036_ctrl_data = {
576 .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
577 .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
578 .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24),
579 .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
580 .dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8),
581 .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
582 .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
583 .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
584 .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
585 .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
588 static const struct vop_data rk3036_vop = {
589 .version = VOP_VERSION(2, 2),
590 .ctrl = &rk3036_ctrl_data,
591 .intr = &rk3036_intr,
592 .win = rk3036_vop_win_data,
593 .win_size = ARRAY_SIZE(rk3036_vop_win_data),
596 static const struct of_device_id vop_driver_dt_match[] = {
597 { .compatible = "rockchip,rk3036-vop",
598 .data = &rk3036_vop },
599 { .compatible = "rockchip,rk3288-vop",
600 .data = &rk3288_vop },
601 { .compatible = "rockchip,rk3368-vop",
602 .data = &rk3368_vop },
603 { .compatible = "rockchip,rk3366-vop",
604 .data = &rk3366_vop },
605 { .compatible = "rockchip,rk3399-vop-big",
606 .data = &rk3399_vop_big },
607 { .compatible = "rockchip,rk3399-vop-lit",
608 .data = &rk3399_vop_lit },
609 { .compatible = "rockchip,rk322x-vop",
610 .data = &rk322x_vop },
613 MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
615 static int vop_probe(struct platform_device *pdev)
617 struct device *dev = &pdev->dev;
620 dev_err(dev, "can't find vop devices\n");
624 return component_add(dev, &vop_component_ops);
627 static int vop_remove(struct platform_device *pdev)
629 component_del(&pdev->dev, &vop_component_ops);
634 struct platform_driver vop_platform_driver = {
636 .remove = vop_remove,
638 .name = "rockchip-vop",
639 .owner = THIS_MODULE,
640 .of_match_table = of_match_ptr(vop_driver_dt_match),
644 module_platform_driver(vop_platform_driver);
646 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
647 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
648 MODULE_LICENSE("GPL v2");