drivers/gpu/drm/rockchip/rockchip_vop_reg.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drmP.h>
  16
  17 #include <linux/kernel.h>
  18 #include <linux/component.h>
  19
  20 #include "rockchip_drm_vop.h"
  21 #include "rockchip_vop_reg.h"
  22
  23 #define VOP_REG(off, _mask, s) \
  24                 {.offset = off, \
  25                  .mask = _mask, \
  26                  .shift = s,}
  27
  28 static const uint32_t formats_01[] = {
  29         DRM_FORMAT_XRGB8888,
  30         DRM_FORMAT_ARGB8888,
  31         DRM_FORMAT_XBGR8888,
  32         DRM_FORMAT_ABGR8888,
  33         DRM_FORMAT_RGB888,
  34         DRM_FORMAT_BGR888,
  35         DRM_FORMAT_RGB565,
  36         DRM_FORMAT_BGR565,
  37         DRM_FORMAT_NV12,
  38         DRM_FORMAT_NV16,
  39         DRM_FORMAT_NV24,
  40 };
  41
  42 static const uint32_t formats_234[] = {
  43         DRM_FORMAT_XRGB8888,
  44         DRM_FORMAT_ARGB8888,
  45         DRM_FORMAT_XBGR8888,
  46         DRM_FORMAT_ABGR8888,
  47         DRM_FORMAT_RGB888,
  48         DRM_FORMAT_BGR888,
  49         DRM_FORMAT_RGB565,
  50         DRM_FORMAT_BGR565,
  51 };
  52
  53 static const struct vop_scl_extension win_full_ext = {
  54         .cbcr_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 31),
  55         .cbcr_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 30),
  56         .cbcr_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 28),
  57         .cbcr_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 26),
  58         .cbcr_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 24),
  59         .yrgb_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 23),
  60         .yrgb_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 22),
  61         .yrgb_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 20),
  62         .yrgb_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 18),
  63         .yrgb_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 16),
  64         .line_load_mode = VOP_REG(WIN0_CTRL1, 0x1, 15),
  65         .cbcr_axi_gather_num = VOP_REG(WIN0_CTRL1, 0x7, 12),
  66         .yrgb_axi_gather_num = VOP_REG(WIN0_CTRL1, 0xf, 8),
  67         .vsd_cbcr_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 7),
  68         .vsd_cbcr_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 6),
  69         .vsd_yrgb_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 5),
  70         .vsd_yrgb_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 4),
  71         .bic_coe_sel = VOP_REG(WIN0_CTRL1, 0x3, 2),
  72         .cbcr_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 1),
  73         .yrgb_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 0),
  74         .lb_mode = VOP_REG(WIN0_CTRL0, 0x7, 5),
  75 };
  76
  77 static const struct vop_scl_regs win_full_scl = {
  78         .scale_yrgb_x = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
  79         .scale_yrgb_y = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
  80         .scale_cbcr_x = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
  81         .scale_cbcr_y = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 16),
  82 };
  83
  84 static const struct vop_win_phy win01_data = {
  85         .scl = &win_full_scl,
  86         .data_formats = formats_01,
  87         .nformats = ARRAY_SIZE(formats_01),
  88         .enable = VOP_REG(WIN0_CTRL0, 0x1, 0),
  89         .format = VOP_REG(WIN0_CTRL0, 0x7, 1),
  90         .rb_swap = VOP_REG(WIN0_CTRL0, 0x1, 12),
  91         .act_info = VOP_REG(WIN0_ACT_INFO, 0x1fff1fff, 0),
  92         .dsp_info = VOP_REG(WIN0_DSP_INFO, 0x0fff0fff, 0),
  93         .dsp_st = VOP_REG(WIN0_DSP_ST, 0x1fff1fff, 0),
  94         .yrgb_mst = VOP_REG(WIN0_YRGB_MST, 0xffffffff, 0),
  95         .uv_mst = VOP_REG(WIN0_CBR_MST, 0xffffffff, 0),
  96         .yrgb_vir = VOP_REG(WIN0_VIR, 0x3fff, 0),
  97         .uv_vir = VOP_REG(WIN0_VIR, 0x3fff, 16),
  98         .src_alpha_ctl = VOP_REG(WIN0_SRC_ALPHA_CTRL, 0xff, 0),
  99         .dst_alpha_ctl = VOP_REG(WIN0_DST_ALPHA_CTRL, 0xff, 0),
 100 };
 101
 102 static const struct vop_win_phy win23_data = {
 103         .data_formats = formats_234,
 104         .nformats = ARRAY_SIZE(formats_234),
 105         .enable = VOP_REG(WIN2_CTRL0, 0x1, 0),
 106         .format = VOP_REG(WIN2_CTRL0, 0x7, 1),
 107         .rb_swap = VOP_REG(WIN2_CTRL0, 0x1, 12),
 108         .dsp_info = VOP_REG(WIN2_DSP_INFO0, 0x0fff0fff, 0),
 109         .dsp_st = VOP_REG(WIN2_DSP_ST0, 0x1fff1fff, 0),
 110         .yrgb_mst = VOP_REG(WIN2_MST0, 0xffffffff, 0),
 111         .yrgb_vir = VOP_REG(WIN2_VIR0_1, 0x1fff, 0),
 112         .src_alpha_ctl = VOP_REG(WIN2_SRC_ALPHA_CTRL, 0xff, 0),
 113         .dst_alpha_ctl = VOP_REG(WIN2_DST_ALPHA_CTRL, 0xff, 0),
 114 };
 115
 116 static const struct vop_ctrl ctrl_data = {
 117         .standby = VOP_REG(SYS_CTRL, 0x1, 22),
 118         .gate_en = VOP_REG(SYS_CTRL, 0x1, 23),
 119         .mmu_en = VOP_REG(SYS_CTRL, 0x1, 20),
 120         .rgb_en = VOP_REG(SYS_CTRL, 0x1, 12),
 121         .hdmi_en = VOP_REG(SYS_CTRL, 0x1, 13),
 122         .edp_en = VOP_REG(SYS_CTRL, 0x1, 14),
 123         .mipi_en = VOP_REG(SYS_CTRL, 0x1, 15),
 124         .dither_down = VOP_REG(DSP_CTRL1, 0xf, 1),
 125         .dither_up = VOP_REG(DSP_CTRL1, 0x1, 6),
 126         .data_blank = VOP_REG(DSP_CTRL0, 0x1, 19),
 127         .out_mode = VOP_REG(DSP_CTRL0, 0xf, 0),
 128         .pin_pol = VOP_REG(DSP_CTRL0, 0xf, 4),
 129         .htotal_pw = VOP_REG(DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 130         .hact_st_end = VOP_REG(DSP_HACT_ST_END, 0x1fff1fff, 0),
 131         .vtotal_pw = VOP_REG(DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 132         .vact_st_end = VOP_REG(DSP_VACT_ST_END, 0x1fff1fff, 0),
 133         .hpost_st_end = VOP_REG(POST_DSP_HACT_INFO, 0x1fff1fff, 0),
 134         .vpost_st_end = VOP_REG(POST_DSP_VACT_INFO, 0x1fff1fff, 0),
 135         .cfg_done = VOP_REG(REG_CFG_DONE, 0x1, 0),
 136 };
 137
 138 static const struct vop_reg_data vop_init_reg_table[] = {
 139         {SYS_CTRL, 0x00c00000},
 140         {DSP_CTRL0, 0x00000000},
 141         {WIN0_CTRL0, 0x00000080},
 142         {WIN1_CTRL0, 0x00000080},
 143         /* TODO: Win2/3 support multiple area function, but we haven't found
 144          * a suitable way to use it yet, so let's just use them as other windows
 145          * with only area 0 enabled.
 146          */
 147         {WIN2_CTRL0, 0x00000010},
 148         {WIN3_CTRL0, 0x00000010},
 149 };
 150
 151 /*
 152  * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
 153  * special support to get alpha blending working.  For now, just use overlay
 154  * window 3 for the drm cursor.
 155  *
 156  */
 157 static const struct vop_win_data rk3288_vop_win_data[] = {
 158         { .base = 0x00, .phy = &win01_data, .type = DRM_PLANE_TYPE_PRIMARY },
 159         { .base = 0x40, .phy = &win01_data, .type = DRM_PLANE_TYPE_OVERLAY },
 160         { .base = 0x00, .phy = &win23_data, .type = DRM_PLANE_TYPE_OVERLAY },
 161         { .base = 0x50, .phy = &win23_data, .type = DRM_PLANE_TYPE_CURSOR },
 162 };
 163
 164 static const int rk3288_vop_intrs[] = {
 165         DSP_HOLD_VALID_INTR,
 166         FS_INTR,
 167         LINE_FLAG_INTR,
 168         BUS_ERROR_INTR,
 169 };
 170
 171 static const struct vop_intr rk3288_vop_intr = {
 172         .intrs = rk3288_vop_intrs,
 173         .nintrs = ARRAY_SIZE(rk3288_vop_intrs),
 174         .status = VOP_REG(INTR_CTRL0, 0xf, 0),
 175         .enable = VOP_REG(INTR_CTRL0, 0xf, 4),
 176         .clear = VOP_REG(INTR_CTRL0, 0xf, 8),
 177 };
 178
 179 static const struct vop_data rk3288_vop = {
 180         .init_table = vop_init_reg_table,
 181         .intr = &rk3288_vop_intr,
 182         .table_size = ARRAY_SIZE(vop_init_reg_table),
 183         .ctrl = &ctrl_data,
 184         .win = rk3288_vop_win_data,
 185         .win_size = ARRAY_SIZE(rk3288_vop_win_data),
 186 };
 187
 188 static const struct of_device_id vop_driver_dt_match[] = {
 189         { .compatible = "rockchip,rk3288-vop",
 190           .data = &rk3288_vop },
 191         {},
 192 };
 193 MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
 194
 195 static int vop_probe(struct platform_device *pdev)
 196 {
 197         struct device *dev = &pdev->dev;
 198
 199         if (!dev->of_node) {
 200                 dev_err(dev, "can't find vop devices\n");
 201                 return -ENODEV;
 202         }
 203
 204         return component_add(dev, &vop_component_ops);
 205 }
 206
 207 static int vop_remove(struct platform_device *pdev)
 208 {
 209         component_del(&pdev->dev, &vop_component_ops);
 210
 211         return 0;
 212 }
 213
 214 struct platform_driver vop_platform_driver = {
 215         .probe = vop_probe,
 216         .remove = vop_remove,
 217         .driver = {
 218                 .name = "rockchip-vop",
 219                 .owner = THIS_MODULE,
 220                 .of_match_table = of_match_ptr(vop_driver_dt_match),
 221         },
 222 };
 223
 224 module_platform_driver(vop_platform_driver);
 225
 226 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
 227 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
 228 MODULE_LICENSE("GPL v2");