2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #include <linux/kernel.h>
18 #include <linux/component.h>
20 #include "rockchip_drm_vop.h"
21 #include "rockchip_vop_reg.h"
23 #define VOP_REG(off, _mask, s) \
29 #define VOP_REG_MASK(off, _mask, s) \
35 static const uint32_t formats_win_full[] = {
49 static const uint32_t formats_win_lite[] = {
60 static const struct vop_scl_extension rk3288_win_full_scl_ext = {
61 .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
62 .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
63 .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28),
64 .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26),
65 .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24),
66 .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23),
67 .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22),
68 .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20),
69 .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18),
70 .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16),
71 .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15),
72 .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12),
73 .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8),
74 .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7),
75 .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6),
76 .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5),
77 .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4),
78 .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2),
79 .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1),
80 .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0),
81 .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5),
84 static const struct vop_scl_regs rk3288_win_full_scl = {
85 .ext = &rk3288_win_full_scl_ext,
86 .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
87 .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
88 .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
89 .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
92 static const struct vop_win_phy rk3288_win01_data = {
93 .scl = &rk3288_win_full_scl,
94 .data_formats = formats_win_full,
95 .nformats = ARRAY_SIZE(formats_win_full),
96 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
97 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
98 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
99 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
100 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
101 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
102 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
103 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
104 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
105 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
106 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
107 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
110 static const struct vop_win_phy rk3288_win23_data = {
111 .data_formats = formats_win_lite,
112 .nformats = ARRAY_SIZE(formats_win_lite),
113 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4),
114 .format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
115 .rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
116 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
117 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0),
118 .yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0),
119 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0),
120 .src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
121 .dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0),
124 static const struct vop_win_phy rk3288_area1_data = {
125 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 5),
126 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO1, 0x0fff0fff, 0),
127 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST1, 0x1fff1fff, 0),
128 .yrgb_mst = VOP_REG(RK3288_WIN2_MST1, 0xffffffff, 0),
129 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 16),
132 static const struct vop_win_phy rk3288_area2_data = {
133 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 6),
134 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO2, 0x0fff0fff, 0),
135 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST2, 0x1fff1fff, 0),
136 .yrgb_mst = VOP_REG(RK3288_WIN2_MST2, 0xffffffff, 0),
137 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 0),
140 static const struct vop_win_phy rk3288_area3_data = {
141 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 7),
142 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO3, 0x0fff0fff, 0),
143 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST3, 0x1fff1fff, 0),
144 .yrgb_mst = VOP_REG(RK3288_WIN2_MST3, 0xffffffff, 0),
145 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 16),
148 static const struct vop_win_phy *rk3288_area_data[] = {
154 static const struct vop_ctrl rk3288_ctrl_data = {
155 .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
156 .dsp_layer_sel = VOP_REG(RK3288_DSP_CTRL1, 0xff, 8),
157 .gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
158 .mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20),
159 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
160 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
161 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
162 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
163 .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
164 .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
165 .data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19),
166 .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
167 .pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),
168 .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
169 .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
170 .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
171 .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
172 .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
173 .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
174 .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
177 static const struct vop_reg_data rk3288_init_reg_table[] = {
178 {RK3288_SYS_CTRL, 0x00c00000},
179 {RK3288_DSP_CTRL0, 0x00000000},
180 {RK3288_WIN0_CTRL0, 0x00000080},
181 {RK3288_WIN1_CTRL0, 0x00000080},
183 * Bit[0] is win2/3 gate en bit, there is no power consume with this
184 * bit enable. the bit's function similar with area plane enable bit,
185 * So default enable this bit, then We can control win2/3 area plane
186 * with its enable bit.
188 {RK3288_WIN2_CTRL0, 0x00000001},
189 {RK3288_WIN3_CTRL0, 0x00000001},
193 * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
194 * special support to get alpha blending working. For now, just use overlay
195 * window 3 for the drm cursor.
198 static const struct vop_win_data rk3288_vop_win_data[] = {
199 { .base = 0x00, .phy = &rk3288_win01_data,
200 .type = DRM_PLANE_TYPE_PRIMARY },
201 { .base = 0x40, .phy = &rk3288_win01_data,
202 .type = DRM_PLANE_TYPE_OVERLAY },
203 { .base = 0x00, .phy = &rk3288_win23_data,
204 .type = DRM_PLANE_TYPE_OVERLAY,
205 .area = rk3288_area_data,
206 .area_size = ARRAY_SIZE(rk3288_area_data), },
207 { .base = 0x50, .phy = &rk3288_win23_data,
208 .type = DRM_PLANE_TYPE_CURSOR,
209 .area = rk3288_area_data,
210 .area_size = ARRAY_SIZE(rk3288_area_data), },
213 static const int rk3288_vop_intrs[] = {
220 static const struct vop_intr rk3288_vop_intr = {
221 .intrs = rk3288_vop_intrs,
222 .nintrs = ARRAY_SIZE(rk3288_vop_intrs),
223 .status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
224 .enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
225 .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
228 static const struct vop_data rk3288_vop = {
229 .feature = VOP_FEATURE_OUTPUT_10BIT,
230 .init_table = rk3288_init_reg_table,
231 .table_size = ARRAY_SIZE(rk3288_init_reg_table),
232 .intr = &rk3288_vop_intr,
233 .ctrl = &rk3288_ctrl_data,
234 .win = rk3288_vop_win_data,
235 .win_size = ARRAY_SIZE(rk3288_vop_win_data),
238 static const struct vop_ctrl rk3399_ctrl_data = {
239 .standby = VOP_REG(RK3399_SYS_CTRL, 0x1, 22),
240 .gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23),
241 .rgb_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 12),
242 .hdmi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 13),
243 .edp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 14),
244 .mipi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 15),
245 .dsp_layer_sel = VOP_REG(RK3399_DSP_CTRL1, 0xff, 8),
246 .dither_down = VOP_REG(RK3399_DSP_CTRL1, 0xf, 1),
247 .dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6),
248 .data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19),
249 .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0),
250 .rgb_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16),
251 .hdmi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 20),
252 .edp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 24),
253 .mipi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 28),
254 .htotal_pw = VOP_REG(RK3399_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
255 .hact_st_end = VOP_REG(RK3399_DSP_HACT_ST_END, 0x1fff1fff, 0),
256 .vtotal_pw = VOP_REG(RK3399_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
257 .vact_st_end = VOP_REG(RK3399_DSP_VACT_ST_END, 0x1fff1fff, 0),
258 .hpost_st_end = VOP_REG(RK3399_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
259 .vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
260 .cfg_done = VOP_REG_MASK(RK3399_REG_CFG_DONE, 0x1, 0),
263 static const int rk3399_vop_intrs[] = {
273 static const struct vop_intr rk3399_vop_intr = {
274 .intrs = rk3399_vop_intrs,
275 .nintrs = ARRAY_SIZE(rk3399_vop_intrs),
276 .status = VOP_REG_MASK(RK3399_INTR_STATUS0, 0xffff, 0),
277 .enable = VOP_REG_MASK(RK3399_INTR_EN0, 0xffff, 0),
278 .clear = VOP_REG_MASK(RK3399_INTR_CLEAR0, 0xffff, 0),
281 static const struct vop_reg_data rk3399_init_reg_table[] = {
282 {RK3399_SYS_CTRL, 0x2000f800},
283 {RK3399_DSP_CTRL0, 0x00000000},
284 {RK3399_WIN0_CTRL0, 0x00000080},
285 {RK3399_WIN1_CTRL0, 0x00000080},
287 * Bit[0] is win2/3 gate en bit, there is no power consume with this
288 * bit enable. the bit's function similar with area plane enable bit,
289 * So default enable this bit, then We can control win2/3 area plane
290 * with its enable bit.
292 {RK3399_WIN2_CTRL0, 0x00000001},
293 {RK3399_WIN3_CTRL0, 0x00000001},
296 static const struct vop_win_phy rk3399_win23_data = {
297 .data_formats = formats_win_lite,
298 .nformats = ARRAY_SIZE(formats_win_lite),
299 .enable = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 4),
300 .format = VOP_REG(RK3399_WIN2_CTRL0, 0x3, 5),
301 .rb_swap = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 20),
302 .dsp_info = VOP_REG(RK3399_WIN2_DSP_INFO0, 0x0fff0fff, 0),
303 .dsp_st = VOP_REG(RK3399_WIN2_DSP_ST0, 0x1fff1fff, 0),
304 .yrgb_mst = VOP_REG(RK3399_WIN2_MST0, 0xffffffff, 0),
305 .yrgb_vir = VOP_REG(RK3399_WIN2_VIR0_1, 0x1fff, 0),
306 .src_alpha_ctl = VOP_REG(RK3399_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
307 .dst_alpha_ctl = VOP_REG(RK3399_WIN2_DST_ALPHA_CTRL, 0xff, 0),
310 static const struct vop_win_phy rk3399_area1_data = {
311 .enable = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 8),
312 .format = VOP_REG(RK3399_WIN2_CTRL0, 0x3, 9),
313 .rb_swap = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 23),
314 .dsp_info = VOP_REG(RK3399_WIN2_DSP_INFO1, 0x0fff0fff, 0),
315 .dsp_st = VOP_REG(RK3399_WIN2_DSP_ST1, 0x1fff1fff, 0),
316 .yrgb_mst = VOP_REG(RK3399_WIN2_MST1, 0xffffffff, 0),
317 .yrgb_vir = VOP_REG(RK3399_WIN2_VIR0_1, 0x1fff, 16),
320 static const struct vop_win_phy rk3399_area2_data = {
321 .enable = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 12),
322 .format = VOP_REG(RK3399_WIN2_CTRL0, 0x3, 13),
323 .rb_swap = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 26),
324 .dsp_info = VOP_REG(RK3399_WIN2_DSP_INFO2, 0x0fff0fff, 0),
325 .dsp_st = VOP_REG(RK3399_WIN2_DSP_ST2, 0x1fff1fff, 0),
326 .yrgb_mst = VOP_REG(RK3399_WIN2_MST2, 0xffffffff, 0),
327 .yrgb_vir = VOP_REG(RK3399_WIN2_VIR2_3, 0x1fff, 0),
330 static const struct vop_win_phy rk3399_area3_data = {
331 .enable = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 16),
332 .format = VOP_REG(RK3399_WIN2_CTRL0, 0x3, 17),
333 .rb_swap = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 29),
334 .dsp_info = VOP_REG(RK3399_WIN2_DSP_INFO3, 0x0fff0fff, 0),
335 .dsp_st = VOP_REG(RK3399_WIN2_DSP_ST3, 0x1fff1fff, 0),
336 .yrgb_mst = VOP_REG(RK3399_WIN2_MST3, 0xffffffff, 0),
337 .yrgb_vir = VOP_REG(RK3399_WIN2_VIR2_3, 0x1fff, 16),
340 static const struct vop_win_phy *rk3399_area_data[] = {
346 static const struct vop_win_data rk3399_vop_win_data[] = {
347 { .base = 0x00, .phy = &rk3288_win01_data,
348 .type = DRM_PLANE_TYPE_PRIMARY },
349 { .base = 0x40, .phy = &rk3288_win01_data,
350 .type = DRM_PLANE_TYPE_OVERLAY },
351 { .base = 0x00, .phy = &rk3399_win23_data,
352 .type = DRM_PLANE_TYPE_OVERLAY,
353 .area = rk3399_area_data,
354 .area_size = ARRAY_SIZE(rk3399_area_data), },
355 { .base = 0x50, .phy = &rk3399_win23_data,
356 .type = DRM_PLANE_TYPE_CURSOR,
357 .area = rk3399_area_data,
358 .area_size = ARRAY_SIZE(rk3399_area_data), },
361 static const struct vop_data rk3399_vop_big = {
362 .feature = VOP_FEATURE_OUTPUT_10BIT,
363 .init_table = rk3399_init_reg_table,
364 .table_size = ARRAY_SIZE(rk3399_init_reg_table),
365 .intr = &rk3399_vop_intr,
366 .ctrl = &rk3399_ctrl_data,
368 * rk3399 vop big windows register layout is same as rk3288.
370 .win = rk3399_vop_win_data,
371 .win_size = ARRAY_SIZE(rk3399_vop_win_data),
374 static const struct vop_win_data rk3399_vop_lit_win_data[] = {
375 { .base = 0x00, .phy = &rk3288_win01_data,
376 .type = DRM_PLANE_TYPE_PRIMARY },
378 { .base = 0x00, .phy = &rk3288_win23_data,
379 .type = DRM_PLANE_TYPE_CURSOR},
384 static const struct vop_data rk3399_vop_lit = {
385 .init_table = rk3399_init_reg_table,
386 .table_size = ARRAY_SIZE(rk3399_init_reg_table),
387 .intr = &rk3399_vop_intr,
388 .ctrl = &rk3399_ctrl_data,
390 * rk3399 vop lit windows register layout is same as rk3288,
391 * but cut off the win1 and win3 windows.
393 .win = rk3399_vop_lit_win_data,
394 .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data),
397 static const struct vop_scl_regs rk3066_win_scl = {
398 .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
399 .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
400 .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
401 .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
404 static const struct vop_win_phy rk3036_win0_data = {
405 .scl = &rk3066_win_scl,
406 .data_formats = formats_win_full,
407 .nformats = ARRAY_SIZE(formats_win_full),
408 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
409 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
410 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
411 .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
412 .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
413 .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
414 .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
415 .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
416 .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
417 .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16),
420 static const struct vop_win_phy rk3036_win1_data = {
421 .data_formats = formats_win_lite,
422 .nformats = ARRAY_SIZE(formats_win_lite),
423 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
424 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
425 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
426 .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
427 .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
428 .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
429 .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
430 .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
433 static const struct vop_win_data rk3036_vop_win_data[] = {
434 { .base = 0x00, .phy = &rk3036_win0_data,
435 .type = DRM_PLANE_TYPE_PRIMARY },
436 { .base = 0x00, .phy = &rk3036_win1_data,
437 .type = DRM_PLANE_TYPE_CURSOR },
440 static const int rk3036_vop_intrs[] = {
447 static const struct vop_intr rk3036_intr = {
448 .intrs = rk3036_vop_intrs,
449 .nintrs = ARRAY_SIZE(rk3036_vop_intrs),
450 .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
451 .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
452 .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
455 static const struct vop_ctrl rk3036_ctrl_data = {
456 .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
457 .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
458 .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
459 .dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8),
460 .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
461 .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
462 .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
463 .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
464 .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
467 static const struct vop_reg_data rk3036_vop_init_reg_table[] = {
468 {RK3036_DSP_CTRL1, 0x00000000},
471 static const struct vop_data rk3036_vop = {
472 .init_table = rk3036_vop_init_reg_table,
473 .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table),
474 .ctrl = &rk3036_ctrl_data,
475 .intr = &rk3036_intr,
476 .win = rk3036_vop_win_data,
477 .win_size = ARRAY_SIZE(rk3036_vop_win_data),
480 static const struct of_device_id vop_driver_dt_match[] = {
481 { .compatible = "rockchip,rk3288-vop",
482 .data = &rk3288_vop },
483 { .compatible = "rockchip,rk3036-vop",
484 .data = &rk3036_vop },
485 { .compatible = "rockchip,rk3399-vop-big",
486 .data = &rk3399_vop_big },
487 { .compatible = "rockchip,rk3399-vop-lit",
488 .data = &rk3399_vop_lit },
491 MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
493 static int vop_probe(struct platform_device *pdev)
495 struct device *dev = &pdev->dev;
498 dev_err(dev, "can't find vop devices\n");
502 return component_add(dev, &vop_component_ops);
505 static int vop_remove(struct platform_device *pdev)
507 component_del(&pdev->dev, &vop_component_ops);
512 struct platform_driver vop_platform_driver = {
514 .remove = vop_remove,
516 .name = "rockchip-vop",
517 .owner = THIS_MODULE,
518 .of_match_table = of_match_ptr(vop_driver_dt_match),
522 module_platform_driver(vop_platform_driver);
524 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
525 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
526 MODULE_LICENSE("GPL v2");