drivers/gpu/drm/rockchip/rockchip_vop_reg.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drmP.h>
  16
  17 #include <linux/kernel.h>
  18 #include <linux/component.h>
  19
  20 #include "rockchip_drm_vop.h"
  21 #include "rockchip_vop_reg.h"
  22
  23 #define VOP_REG_VER_MASK(off, _mask, s, _write_mask, _major, \
  24                          _begin_minor, _end_minor) \
  25                 {.offset = off, \
  26                  .mask = _mask, \
  27                  .shift = s, \
  28                  .write_mask = _write_mask, \
  29                  .major = _major, \
  30                  .begin_minor = _begin_minor, \
  31                  .end_minor = _end_minor,}
  32
  33 #define VOP_REG(off, _mask, s) \
  34                 VOP_REG_VER_MASK(off, _mask, s, false, 0, 0, -1)
  35
  36 #define VOP_REG_MASK(off, _mask, s) \
  37                 VOP_REG_VER_MASK(off, _mask, s, true, 0, 0, -1)
  38
  39 #define VOP_REG_VER(off, _mask, s, _major, _begin_minor, _end_minor) \
  40                 VOP_REG_VER_MASK(off, _mask, s, false, \
  41                                  _major, _begin_minor, _end_minor)
  42
  43
  44 static const uint32_t formats_win_full[] = {
  45         DRM_FORMAT_XRGB8888,
  46         DRM_FORMAT_ARGB8888,
  47         DRM_FORMAT_XBGR8888,
  48         DRM_FORMAT_ABGR8888,
  49         DRM_FORMAT_RGB888,
  50         DRM_FORMAT_BGR888,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_BGR565,
  53         DRM_FORMAT_NV12,
  54         DRM_FORMAT_NV16,
  55         DRM_FORMAT_NV24,
  56         DRM_FORMAT_NV12_10,
  57         DRM_FORMAT_NV16_10,
  58         DRM_FORMAT_NV24_10,
  59 };
  60
  61 static const uint32_t formats_win_lite[] = {
  62         DRM_FORMAT_XRGB8888,
  63         DRM_FORMAT_ARGB8888,
  64         DRM_FORMAT_XBGR8888,
  65         DRM_FORMAT_ABGR8888,
  66         DRM_FORMAT_RGB888,
  67         DRM_FORMAT_BGR888,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_BGR565,
  70 };
  71
  72 static const struct vop_scl_extension rk3288_win_full_scl_ext = {
  73         .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
  74         .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
  75         .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28),
  76         .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26),
  77         .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24),
  78         .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23),
  79         .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22),
  80         .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20),
  81         .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18),
  82         .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16),
  83         .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15),
  84         .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12),
  85         .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8),
  86         .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7),
  87         .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6),
  88         .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5),
  89         .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4),
  90         .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2),
  91         .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1),
  92         .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0),
  93         .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5),
  94 };
  95
  96 static const struct vop_scl_regs rk3288_win_full_scl = {
  97         .ext = &rk3288_win_full_scl_ext,
  98         .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
  99         .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
 100         .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
 101         .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
 102 };
 103
 104 static const struct vop_win_phy rk3288_win01_data = {
 105         .scl = &rk3288_win_full_scl,
 106         .data_formats = formats_win_full,
 107         .nformats = ARRAY_SIZE(formats_win_full),
 108         .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
 109         .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
 110         .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 4),
 111         .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
 112         .xmirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 21, 3, 2, -1),
 113         .ymirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 22, 3, 2, -1),
 114         .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
 115         .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
 116         .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
 117         .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
 118         .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
 119         .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
 120         .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
 121         .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xffffffff, 0),
 122         .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xffffffff, 0),
 123 };
 124
 125 static const struct vop_win_phy rk3288_win23_data = {
 126         .data_formats = formats_win_lite,
 127         .nformats = ARRAY_SIZE(formats_win_lite),
 128         .gate = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
 129         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4),
 130         .format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
 131         .rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
 132         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
 133         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0),
 134         .yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0),
 135         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0),
 136         .src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
 137         .dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0),
 138 };
 139
 140 static const struct vop_win_phy rk3288_area1_data = {
 141         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 5),
 142         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO1, 0x0fff0fff, 0),
 143         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST1, 0x1fff1fff, 0),
 144         .yrgb_mst = VOP_REG(RK3288_WIN2_MST1, 0xffffffff, 0),
 145         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 16),
 146 };
 147
 148 static const struct vop_win_phy rk3288_area2_data = {
 149         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 6),
 150         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO2, 0x0fff0fff, 0),
 151         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST2, 0x1fff1fff, 0),
 152         .yrgb_mst = VOP_REG(RK3288_WIN2_MST2, 0xffffffff, 0),
 153         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 0),
 154 };
 155
 156 static const struct vop_win_phy rk3288_area3_data = {
 157         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 7),
 158         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO3, 0x0fff0fff, 0),
 159         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST3, 0x1fff1fff, 0),
 160         .yrgb_mst = VOP_REG(RK3288_WIN2_MST3, 0xffffffff, 0),
 161         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 16),
 162 };
 163
 164 static const struct vop_win_phy *rk3288_area_data[] = {
 165         &rk3288_area1_data,
 166         &rk3288_area2_data,
 167         &rk3288_area3_data
 168 };
 169
 170 static const struct vop_ctrl rk3288_ctrl_data = {
 171         .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
 172         .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 173         .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
 174         .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 175         .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
 176         .vact_st_end_f1 = VOP_REG(RK3288_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
 177         .vs_st_end_f1 = VOP_REG(RK3288_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
 178         .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
 179         .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
 180         .vpost_st_end_f1 = VOP_REG(RK3288_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
 181         .post_scl_factor = VOP_REG(RK3288_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
 182         .post_scl_ctrl = VOP_REG(RK3288_POST_SCL_CTRL, 0x3, 0),
 183
 184         .dsp_interlace = VOP_REG(RK3288_DSP_CTRL0, 0x1, 10),
 185         .auto_gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
 186         .dsp_layer_sel = VOP_REG(RK3288_DSP_CTRL1, 0xff, 8),
 187         .post_lb_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 18, 3, 2, -1),
 188         .global_regdone_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 2, -1),
 189         .overlay_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 16, 3, 2, -1),
 190         .core_dclk_div = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 4, 3, 4, -1),
 191         .p2i_en = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 5, 3, 4, -1),
 192         .dclk_ddr = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 8, 3, 4, -1),
 193         .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11),
 194         .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
 195         .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
 196         .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
 197         .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
 198         .pin_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0xf, 4, 3, 0, 1),
 199         .dp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 16, 3, 2, -1),
 200         .rgb_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 16, 3, 2, -1),
 201         .hdmi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 20, 3, 2, -1),
 202         .edp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 24, 3, 2, -1),
 203         .mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 28, 3, 2, -1),
 204
 205         .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
 206         .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
 207
 208         .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12),
 209         .dsp_ccir656_avg = VOP_REG(RK3288_DSP_CTRL0, 0x1, 20),
 210         .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
 211         .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0),
 212         .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
 213
 214         .afbdc_rstn = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 3),
 215         .afbdc_en = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 0),
 216         .afbdc_sel = VOP_REG(RK3399_AFBCD0_CTRL, 0x3, 1),
 217         .afbdc_format = VOP_REG(RK3399_AFBCD0_CTRL, 0x1f, 16),
 218         .afbdc_hreg_block_split = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 21),
 219         .afbdc_hdr_ptr = VOP_REG(RK3399_AFBCD0_HDR_PTR, 0xffffffff, 0),
 220         .afbdc_pic_size = VOP_REG(RK3399_AFBCD0_PIC_SIZE, 0xffffffff, 0),
 221
 222         .xmirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 22),
 223         .ymirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 23),
 224
 225         .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0),
 226
 227         .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
 228 };
 229
 230 /*
 231  * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
 232  * special support to get alpha blending working.  For now, just use overlay
 233  * window 3 for the drm cursor.
 234  *
 235  */
 236 static const struct vop_win_data rk3288_vop_win_data[] = {
 237         { .base = 0x00, .phy = &rk3288_win01_data,
 238           .type = DRM_PLANE_TYPE_PRIMARY },
 239         { .base = 0x40, .phy = &rk3288_win01_data,
 240           .type = DRM_PLANE_TYPE_OVERLAY },
 241         { .base = 0x00, .phy = &rk3288_win23_data,
 242           .type = DRM_PLANE_TYPE_OVERLAY,
 243           .area = rk3288_area_data,
 244           .area_size = ARRAY_SIZE(rk3288_area_data), },
 245         { .base = 0x50, .phy = &rk3288_win23_data,
 246           .type = DRM_PLANE_TYPE_CURSOR,
 247           .area = rk3288_area_data,
 248           .area_size = ARRAY_SIZE(rk3288_area_data), },
 249 };
 250
 251 static const int rk3288_vop_intrs[] = {
 252         DSP_HOLD_VALID_INTR,
 253         FS_INTR,
 254         LINE_FLAG_INTR,
 255         BUS_ERROR_INTR,
 256 };
 257
 258 static const struct vop_intr rk3288_vop_intr = {
 259         .intrs = rk3288_vop_intrs,
 260         .nintrs = ARRAY_SIZE(rk3288_vop_intrs),
 261         .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
 262         .status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
 263         .enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
 264         .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
 265 };
 266
 267 static const struct vop_data rk3288_vop = {
 268         .version = VOP_VERSION(3, 1),
 269         .feature = VOP_FEATURE_OUTPUT_10BIT,
 270         .max_input = {4096, 8192},
 271         /*
 272          * TODO: rk3288 have two vop, big one support 3840x2160,
 273          * little one only support 2560x1600.
 274          * Now force use 3840x2160.
 275          */
 276         .max_output = {3840, 2160},
 277         .intr = &rk3288_vop_intr,
 278         .ctrl = &rk3288_ctrl_data,
 279         .win = rk3288_vop_win_data,
 280         .win_size = ARRAY_SIZE(rk3288_vop_win_data),
 281 };
 282
 283 static const int rk3368_vop_intrs[] = {
 284         FS_INTR,
 285         FS_NEW_INTR,
 286         ADDR_SAME_INTR,
 287         LINE_FLAG_INTR,
 288         LINE_FLAG1_INTR,
 289         BUS_ERROR_INTR,
 290         WIN0_EMPTY_INTR,
 291         WIN1_EMPTY_INTR,
 292         WIN2_EMPTY_INTR,
 293         WIN3_EMPTY_INTR,
 294         HWC_EMPTY_INTR,
 295         POST_BUF_EMPTY_INTR,
 296         PWM_GEN_INTR,
 297         DSP_HOLD_VALID_INTR,
 298 };
 299
 300 static const struct vop_intr rk3368_vop_intr = {
 301         .intrs = rk3368_vop_intrs,
 302         .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
 303         .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 0),
 304         .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 16),
 305         .status = VOP_REG_MASK(RK3368_INTR_STATUS, 0x3fff, 0),
 306         .enable = VOP_REG_MASK(RK3368_INTR_EN, 0x3fff, 0),
 307         .clear = VOP_REG_MASK(RK3368_INTR_CLEAR, 0x3fff, 0),
 308 };
 309
 310 static const struct vop_win_phy rk3368_win23_data = {
 311         .data_formats = formats_win_lite,
 312         .nformats = ARRAY_SIZE(formats_win_lite),
 313         .gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0),
 314         .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4),
 315         .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5),
 316         .ymirror = VOP_REG(RK3368_WIN2_CTRL1, 0x1, 15),
 317         .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20),
 318         .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0),
 319         .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0),
 320         .yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0),
 321         .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0),
 322         .src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
 323         .dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xff, 0),
 324 };
 325
 326 static const struct vop_win_phy rk3368_area1_data = {
 327         .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 8),
 328         .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 9),
 329         .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 23),
 330         .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO1, 0x0fff0fff, 0),
 331         .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST1, 0x1fff1fff, 0),
 332         .yrgb_mst = VOP_REG(RK3368_WIN2_MST1, 0xffffffff, 0),
 333         .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 16),
 334 };
 335
 336 static const struct vop_win_phy rk3368_area2_data = {
 337         .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 12),
 338         .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 13),
 339         .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 26),
 340         .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO2, 0x0fff0fff, 0),
 341         .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST2, 0x1fff1fff, 0),
 342         .yrgb_mst = VOP_REG(RK3368_WIN2_MST2, 0xffffffff, 0),
 343         .yrgb_vir = VOP_REG(RK3368_WIN2_VIR2_3, 0x1fff, 0),
 344 };
 345
 346 static const struct vop_win_phy rk3368_area3_data = {
 347         .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 16),
 348         .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 17),
 349         .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 29),
 350         .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO3, 0x0fff0fff, 0),
 351         .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST3, 0x1fff1fff, 0),
 352         .yrgb_mst = VOP_REG(RK3368_WIN2_MST3, 0xffffffff, 0),
 353         .yrgb_vir = VOP_REG(RK3368_WIN2_VIR2_3, 0x1fff, 16),
 354 };
 355
 356 static const struct vop_win_phy *rk3368_area_data[] = {
 357         &rk3368_area1_data,
 358         &rk3368_area2_data,
 359         &rk3368_area3_data
 360 };
 361
 362 static const struct vop_win_data rk3368_vop_win_data[] = {
 363         { .base = 0x00, .phy = &rk3288_win01_data,
 364           .type = DRM_PLANE_TYPE_PRIMARY },
 365         { .base = 0x40, .phy = &rk3288_win01_data,
 366           .type = DRM_PLANE_TYPE_OVERLAY },
 367         { .base = 0x00, .phy = &rk3368_win23_data,
 368           .type = DRM_PLANE_TYPE_OVERLAY,
 369           .area = rk3368_area_data,
 370           .area_size = ARRAY_SIZE(rk3368_area_data), },
 371         { .base = 0x50, .phy = &rk3368_win23_data,
 372           .type = DRM_PLANE_TYPE_CURSOR,
 373           .area = rk3368_area_data,
 374           .area_size = ARRAY_SIZE(rk3368_area_data), },
 375 };
 376
 377 static const struct vop_data rk3368_vop = {
 378         .version = VOP_VERSION(3, 2),
 379         .feature = VOP_FEATURE_OUTPUT_10BIT,
 380         .max_input = {4096, 8192},
 381         .max_output = {4096, 2160},
 382         .intr = &rk3368_vop_intr,
 383         .ctrl = &rk3288_ctrl_data,
 384         .win = rk3368_vop_win_data,
 385         .win_size = ARRAY_SIZE(rk3368_vop_win_data),
 386 };
 387
 388 static const struct vop_intr rk3366_vop_intr = {
 389         .intrs = rk3368_vop_intrs,
 390         .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
 391         .line_flag_num[0] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 0),
 392         .line_flag_num[1] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 16),
 393         .status = VOP_REG_MASK(RK3366_INTR_STATUS0, 0xffff, 0),
 394         .enable = VOP_REG_MASK(RK3366_INTR_EN0, 0xffff, 0),
 395         .clear = VOP_REG_MASK(RK3366_INTR_CLEAR0, 0xffff, 0),
 396 };
 397
 398 static const struct vop_data rk3366_vop = {
 399         .version = VOP_VERSION(3, 4),
 400         .feature = VOP_FEATURE_OUTPUT_10BIT,
 401         .max_input = {4096, 8192},
 402         .max_output = {4096, 2160},
 403         .intr = &rk3366_vop_intr,
 404         .ctrl = &rk3288_ctrl_data,
 405         .win = rk3368_vop_win_data,
 406         .win_size = ARRAY_SIZE(rk3368_vop_win_data),
 407 };
 408
 409 static const uint32_t vop_csc_y2r_bt601[] = {
 410         0x00000400, 0x0400059c, 0xfd25fea0, 0x07170400,
 411         0x00000000, 0xfffecab4, 0x00087932, 0xfff1d4f2,
 412 };
 413
 414 static const uint32_t vop_csc_y2r_bt601_12_235[] = {
 415         0x000004a8, 0x04a80662, 0xfcbffe6f, 0x081204a8,
 416         0x00000000, 0xfff2134e, 0x00087b58, 0xffeeb4b0,
 417 };
 418
 419 static const uint32_t vop_csc_r2y_bt601[] = {
 420         0x02590132, 0xff530075, 0x0200fead, 0xfe530200,
 421         0x0000ffad, 0x00000200, 0x00080200, 0x00080200,
 422 };
 423
 424 static const uint32_t vop_csc_r2y_bt601_12_235[] = {
 425         0x02040107, 0xff680064, 0x01c2fed6, 0xffb7fe87,
 426         0x0000ffb7, 0x00010200, 0x00080200, 0x00080200,
 427 };
 428
 429 static const uint32_t vop_csc_y2r_bt709[] = {
 430         0x000004a8, 0x04a8072c, 0xfddeff26, 0x087304a8,
 431         0x00000000, 0xfff08077, 0x0004cfed, 0xffedf1b8,
 432 };
 433
 434 static const uint32_t vop_csc_r2y_bt709[] = {
 435         0x027500bb, 0xff99003f, 0x01c2fea5, 0xfe6801c2,
 436         0x0000ffd7, 0x00010200, 0x00080200, 0x00080200,
 437 };
 438
 439 static const uint32_t vop_csc_y2r_bt2020[] = {
 440         0x000004a8, 0x04a806b6, 0xfd66ff40, 0x089004a8,
 441         0x00000000, 0xfff16bfc, 0x00058ae9, 0xffedb828,
 442 };
 443
 444 static const uint32_t vop_csc_r2y_bt2020[] = {
 445         0x025300e6, 0xff830034, 0x01c1febd, 0xfe6401c1,
 446         0x0000ffdc, 0x00010200, 0x00080200, 0x00080200,
 447 };
 448
 449 static const uint32_t vop_csc_r2r_bt709_to_bt2020[] = {
 450         0xfda606a4, 0xff80ffb5, 0xfff80488, 0xff99ffed,
 451         0x0000047a, 0x00000200, 0x00000200, 0x00000200,
 452 };
 453
 454 static const uint32_t vop_csc_r2r_bt2020_to_bt709[] = {
 455         0x01510282, 0x0047002c, 0x000c03ae, 0x005a0011,
 456         0x00000394, 0x00000200, 0x00000200, 0x00000200,
 457 };
 458
 459 static const struct vop_csc_table rk3399_csc_table = {
 460         .y2r_bt601              = vop_csc_y2r_bt601,
 461         .y2r_bt601_12_235       = vop_csc_y2r_bt601_12_235,
 462         .r2y_bt601              = vop_csc_r2y_bt601,
 463         .r2y_bt601_12_235       = vop_csc_r2y_bt601_12_235,
 464
 465         .y2r_bt709              = vop_csc_y2r_bt709,
 466         .r2y_bt709              = vop_csc_r2y_bt709,
 467
 468         .y2r_bt2020             = vop_csc_y2r_bt2020,
 469         .r2y_bt2020             = vop_csc_r2y_bt2020,
 470
 471         .r2r_bt709_to_bt2020    = vop_csc_r2r_bt709_to_bt2020,
 472         .r2r_bt2020_to_bt709    = vop_csc_r2r_bt2020_to_bt709,
 473 };
 474
 475 static const struct vop_csc rk3399_win0_csc = {
 476         .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 0),
 477         .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1),
 478         .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 2),
 479         .y2r_offset = RK3399_WIN0_YUV2YUV_Y2R,
 480         .r2r_offset = RK3399_WIN0_YUV2YUV_3X3,
 481         .r2y_offset = RK3399_WIN0_YUV2YUV_R2Y,
 482 };
 483
 484 static const struct vop_csc rk3399_win1_csc = {
 485         .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 8),
 486         .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 9),
 487         .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 10),
 488         .y2r_offset = RK3399_WIN1_YUV2YUV_Y2R,
 489         .r2r_offset = RK3399_WIN1_YUV2YUV_3X3,
 490         .r2y_offset = RK3399_WIN1_YUV2YUV_R2Y,
 491 };
 492
 493 static const struct vop_win_data rk3399_vop_win_data[] = {
 494         { .base = 0x00, .phy = &rk3288_win01_data, .csc = &rk3399_win0_csc,
 495           .type = DRM_PLANE_TYPE_PRIMARY },
 496         { .base = 0x40, .phy = &rk3288_win01_data, .csc = &rk3399_win1_csc,
 497           .type = DRM_PLANE_TYPE_OVERLAY },
 498         { .base = 0x00, .phy = &rk3368_win23_data,
 499           .type = DRM_PLANE_TYPE_OVERLAY,
 500           .area = rk3368_area_data,
 501           .area_size = ARRAY_SIZE(rk3368_area_data), },
 502         { .base = 0x50, .phy = &rk3368_win23_data,
 503           .type = DRM_PLANE_TYPE_CURSOR,
 504           .area = rk3368_area_data,
 505           .area_size = ARRAY_SIZE(rk3368_area_data), },
 506 };
 507
 508 static const struct vop_data rk3399_vop_big = {
 509         .version = VOP_VERSION(3, 5),
 510         .csc_table = &rk3399_csc_table,
 511         .feature = VOP_FEATURE_OUTPUT_10BIT | VOP_FEATURE_AFBDC,
 512         .max_input = {4096, 8192},
 513         .max_output = {4096, 2160},
 514         .intr = &rk3366_vop_intr,
 515         .ctrl = &rk3288_ctrl_data,
 516         .win = rk3399_vop_win_data,
 517         .win_size = ARRAY_SIZE(rk3399_vop_win_data),
 518 };
 519
 520 static const struct vop_win_data rk3399_vop_lit_win_data[] = {
 521         { .base = 0x00, .phy = &rk3288_win01_data, .csc = &rk3399_win0_csc,
 522           .type = DRM_PLANE_TYPE_PRIMARY },
 523         { .phy = NULL },
 524         { .base = 0x00, .phy = &rk3368_win23_data,
 525           .type = DRM_PLANE_TYPE_CURSOR,
 526           .area = rk3368_area_data,
 527           .area_size = ARRAY_SIZE(rk3368_area_data), },
 528         { .phy = NULL },
 529 };
 530
 531
 532 static const struct vop_data rk3399_vop_lit = {
 533         .version = VOP_VERSION(3, 6),
 534         .csc_table = &rk3399_csc_table,
 535         .max_input = {4096, 8192},
 536         .max_output = {2560, 1600},
 537         .intr = &rk3366_vop_intr,
 538         .ctrl = &rk3288_ctrl_data,
 539         .win = rk3399_vop_lit_win_data,
 540         .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data),
 541 };
 542
 543 static const struct vop_data rk322x_vop = {
 544         .version = VOP_VERSION(3, 7),
 545         .feature = VOP_FEATURE_OUTPUT_10BIT,
 546         .max_input = {4096, 8192},
 547         .max_output = {4096, 2160},
 548         .intr = &rk3366_vop_intr,
 549         .ctrl = &rk3288_ctrl_data,
 550         .win = rk3368_vop_win_data,
 551         .win_size = ARRAY_SIZE(rk3368_vop_win_data),
 552 };
 553
 554 static const struct vop_ctrl rk3328_ctrl_data = {
 555         .standby = VOP_REG(RK3328_SYS_CTRL, 0x1, 22),
 556         .auto_gate_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 23),
 557         .htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 558         .hact_st_end = VOP_REG(RK3328_DSP_HACT_ST_END, 0x1fff1fff, 0),
 559         .vtotal_pw = VOP_REG(RK3328_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 560         .vact_st_end = VOP_REG(RK3328_DSP_VACT_ST_END, 0x1fff1fff, 0),
 561         .vact_st_end_f1 = VOP_REG(RK3328_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
 562         .vs_st_end_f1 = VOP_REG(RK3328_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
 563         .hpost_st_end = VOP_REG(RK3328_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
 564         .vpost_st_end = VOP_REG(RK3328_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
 565         .vpost_st_end_f1 = VOP_REG(RK3328_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
 566         .dsp_interlace = VOP_REG(RK3328_DSP_CTRL0, 0x1, 10),
 567         .dsp_layer_sel = VOP_REG(RK3328_DSP_CTRL1, 0xff, 8),
 568         .post_lb_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 18),
 569         .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11),
 570         .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16),
 571         .core_dclk_div = VOP_REG(RK3328_DSP_CTRL0, 0x1, 4),
 572         .p2i_en = VOP_REG(RK3328_DSP_CTRL0, 0x1, 5),
 573         .rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12),
 574         .hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13),
 575         .edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14),
 576         .mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15),
 577         .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 16),
 578         .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 20),
 579         .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 24),
 580         .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 28),
 581
 582         .dither_down = VOP_REG(RK3328_DSP_CTRL1, 0xf, 1),
 583         .dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6),
 584
 585         .dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12),
 586         .dsp_ccir656_avg = VOP_REG(RK3328_DSP_CTRL0, 0x1, 20),
 587         .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18),
 588         .dsp_lut_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 0),
 589         .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0),
 590
 591         .xmirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 22),
 592         .ymirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 23),
 593
 594         .dsp_background = VOP_REG(RK3328_DSP_BG, 0xffffffff, 0),
 595
 596         .cfg_done = VOP_REG(RK3328_REG_CFG_DONE, 0x1, 0),
 597 };
 598
 599 static const struct vop_intr rk3328_vop_intr = {
 600         .intrs = rk3368_vop_intrs,
 601         .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
 602         .line_flag_num[0] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 0),
 603         .line_flag_num[1] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 16),
 604         .status = VOP_REG_MASK(RK3328_INTR_STATUS0, 0xffff, 0),
 605         .enable = VOP_REG_MASK(RK3328_INTR_EN0, 0xffff, 0),
 606         .clear = VOP_REG_MASK(RK3328_INTR_CLEAR0, 0xffff, 0),
 607 };
 608
 609 static const struct vop_win_data rk3328_vop_win_data[] = {
 610         { .base = 0xd0, .phy = &rk3288_win01_data,
 611           .type = DRM_PLANE_TYPE_PRIMARY },
 612         { .base = 0x1d0, .phy = &rk3288_win01_data,
 613           .type = DRM_PLANE_TYPE_OVERLAY },
 614         { .base = 0x2d0, .phy = &rk3288_win01_data,
 615           .type = DRM_PLANE_TYPE_OVERLAY },
 616         { .base = 0x3d0, .phy = &rk3288_win01_data,
 617           .type = DRM_PLANE_TYPE_CURSOR },
 618 };
 619
 620 static const struct vop_data rk3328_vop = {
 621         .version = VOP_VERSION(3, 8),
 622         .feature = VOP_FEATURE_OUTPUT_10BIT,
 623         .max_input = {4096, 8192},
 624         .max_output = {4096, 2160},
 625         .intr = &rk3328_vop_intr,
 626         .ctrl = &rk3328_ctrl_data,
 627         .win = rk3328_vop_win_data,
 628         .win_size = ARRAY_SIZE(rk3328_vop_win_data),
 629 };
 630
 631 static const struct vop_scl_regs rk3066_win_scl = {
 632         .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
 633         .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
 634         .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
 635         .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
 636 };
 637
 638 static const struct vop_win_phy rk3036_win0_data = {
 639         .scl = &rk3066_win_scl,
 640         .data_formats = formats_win_full,
 641         .nformats = ARRAY_SIZE(formats_win_full),
 642         .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
 643         .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
 644         .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
 645         .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
 646         .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
 647         .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
 648         .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
 649         .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
 650         .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
 651         .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16),
 652         .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 18),
 653         .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0)
 654 };
 655
 656 static const struct vop_win_phy rk3036_win1_data = {
 657         .data_formats = formats_win_lite,
 658         .nformats = ARRAY_SIZE(formats_win_lite),
 659         .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
 660         .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
 661         .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
 662         .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
 663         .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
 664         .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
 665         .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
 666         .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
 667         .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 19),
 668         .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1)
 669 };
 670
 671 static const struct vop_win_data rk3036_vop_win_data[] = {
 672         { .base = 0x00, .phy = &rk3036_win0_data,
 673           .type = DRM_PLANE_TYPE_PRIMARY },
 674         { .base = 0x00, .phy = &rk3036_win1_data,
 675           .type = DRM_PLANE_TYPE_CURSOR },
 676 };
 677
 678 static const int rk3036_vop_intrs[] = {
 679         DSP_HOLD_VALID_INTR,
 680         FS_INTR,
 681         LINE_FLAG_INTR,
 682         BUS_ERROR_INTR,
 683 };
 684
 685 static const struct vop_intr rk3036_intr = {
 686         .intrs = rk3036_vop_intrs,
 687         .nintrs = ARRAY_SIZE(rk3036_vop_intrs),
 688         .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
 689         .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
 690         .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
 691         .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
 692 };
 693
 694 static const struct vop_ctrl rk3036_ctrl_data = {
 695         .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
 696         .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
 697         .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24),
 698         .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
 699         .dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8),
 700         .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 701         .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
 702         .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 703         .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
 704         .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
 705 };
 706
 707 static const struct vop_data rk3036_vop = {
 708         .version = VOP_VERSION(2, 2),
 709         .max_input = {1920, 1080},
 710         .max_output = {1920, 1080},
 711         .ctrl = &rk3036_ctrl_data,
 712         .intr = &rk3036_intr,
 713         .win = rk3036_vop_win_data,
 714         .win_size = ARRAY_SIZE(rk3036_vop_win_data),
 715 };
 716
 717 static const struct of_device_id vop_driver_dt_match[] = {
 718         { .compatible = "rockchip,rk3036-vop",
 719           .data = &rk3036_vop },
 720         { .compatible = "rockchip,rk3288-vop",
 721           .data = &rk3288_vop },
 722         { .compatible = "rockchip,rk3368-vop",
 723           .data = &rk3368_vop },
 724         { .compatible = "rockchip,rk3366-vop",
 725           .data = &rk3366_vop },
 726         { .compatible = "rockchip,rk3399-vop-big",
 727           .data = &rk3399_vop_big },
 728         { .compatible = "rockchip,rk3399-vop-lit",
 729           .data = &rk3399_vop_lit },
 730         { .compatible = "rockchip,rk322x-vop",
 731           .data = &rk322x_vop },
 732         { .compatible = "rockchip,rk3328-vop",
 733           .data = &rk3328_vop },
 734         {},
 735 };
 736 MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
 737
 738 static int vop_probe(struct platform_device *pdev)
 739 {
 740         struct device *dev = &pdev->dev;
 741
 742         if (!dev->of_node) {
 743                 dev_err(dev, "can't find vop devices\n");
 744                 return -ENODEV;
 745         }
 746
 747         return component_add(dev, &vop_component_ops);
 748 }
 749
 750 static int vop_remove(struct platform_device *pdev)
 751 {
 752         component_del(&pdev->dev, &vop_component_ops);
 753
 754         return 0;
 755 }
 756
 757 struct platform_driver vop_platform_driver = {
 758         .probe = vop_probe,
 759         .remove = vop_remove,
 760         .driver = {
 761                 .name = "rockchip-vop",
 762                 .owner = THIS_MODULE,
 763                 .of_match_table = of_match_ptr(vop_driver_dt_match),
 764         },
 765 };
 766
 767 module_platform_driver(vop_platform_driver);
 768
 769 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
 770 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
 771 MODULE_LICENSE("GPL v2");