2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #ifndef _ROCKCHIP_DRM_VOP_H
16 #define _ROCKCHIP_DRM_VOP_H
18 enum vop_data_format {
39 struct vop_reg standby;
40 struct vop_reg data_blank;
41 struct vop_reg gate_en;
42 struct vop_reg mmu_en;
43 struct vop_reg rgb_en;
44 struct vop_reg edp_en;
45 struct vop_reg hdmi_en;
46 struct vop_reg mipi_en;
47 struct vop_reg out_mode;
48 struct vop_reg dither_down;
49 struct vop_reg dither_up;
50 struct vop_reg pin_pol;
52 struct vop_reg htotal_pw;
53 struct vop_reg hact_st_end;
54 struct vop_reg vtotal_pw;
55 struct vop_reg vact_st_end;
56 struct vop_reg hpost_st_end;
57 struct vop_reg vpost_st_end;
59 struct vop_reg cfg_done;
65 struct vop_reg enable;
67 struct vop_reg status;
70 struct vop_reg cbcr_vsd_mode;
71 struct vop_reg cbcr_vsu_mode;
72 struct vop_reg cbcr_hsd_mode;
73 struct vop_reg cbcr_ver_scl_mode;
74 struct vop_reg cbcr_hor_scl_mode;
75 struct vop_reg yrgb_vsd_mode;
76 struct vop_reg yrgb_vsu_mode;
77 struct vop_reg yrgb_hsd_mode;
78 struct vop_reg yrgb_ver_scl_mode;
79 struct vop_reg yrgb_hor_scl_mode;
80 struct vop_reg line_load_mode;
81 struct vop_reg cbcr_axi_gather_num;
82 struct vop_reg yrgb_axi_gather_num;
83 struct vop_reg vsd_cbcr_gt2;
84 struct vop_reg vsd_cbcr_gt4;
85 struct vop_reg vsd_yrgb_gt2;
86 struct vop_reg vsd_yrgb_gt4;
87 struct vop_reg bic_coe_sel;
88 struct vop_reg cbcr_axi_gather_en;
89 struct vop_reg yrgb_axi_gather_en;
91 struct vop_reg lb_mode;
92 struct vop_reg scale_yrgb_x;
93 struct vop_reg scale_yrgb_y;
94 struct vop_reg scale_cbcr_x;
95 struct vop_reg scale_cbcr_y;
99 const struct vop_scl_regs *scl;
100 const uint32_t *data_formats;
103 struct vop_reg enable;
104 struct vop_reg format;
105 struct vop_reg rb_swap;
106 struct vop_reg act_info;
107 struct vop_reg dsp_info;
108 struct vop_reg dsp_st;
109 struct vop_reg yrgb_mst;
110 struct vop_reg uv_mst;
111 struct vop_reg yrgb_vir;
112 struct vop_reg uv_vir;
114 struct vop_reg dst_alpha_ctl;
115 struct vop_reg src_alpha_ctl;
118 struct vop_win_data {
120 const struct vop_win_phy *phy;
121 enum drm_plane_type type;
125 const struct vop_reg_data *init_table;
126 unsigned int table_size;
127 const struct vop_ctrl *ctrl;
128 const struct vop_intr *intr;
129 const struct vop_win_data *win;
130 unsigned int win_size;
133 /* interrupt define */
134 #define DSP_HOLD_VALID_INTR (1 << 0)
135 #define FS_INTR (1 << 1)
136 #define LINE_FLAG_INTR (1 << 2)
137 #define BUS_ERROR_INTR (1 << 3)
139 #define INTR_MASK (DSP_HOLD_VALID_INTR | FS_INTR | \
140 LINE_FLAG_INTR | BUS_ERROR_INTR)
142 #define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4)
143 #define FS_INTR_EN(x) ((x) << 5)
144 #define LINE_FLAG_INTR_EN(x) ((x) << 6)
145 #define BUS_ERROR_INTR_EN(x) ((x) << 7)
146 #define DSP_HOLD_VALID_INTR_MASK (1 << 4)
147 #define FS_INTR_MASK (1 << 5)
148 #define LINE_FLAG_INTR_MASK (1 << 6)
149 #define BUS_ERROR_INTR_MASK (1 << 7)
151 #define INTR_CLR_SHIFT 8
152 #define DSP_HOLD_VALID_INTR_CLR (1 << (INTR_CLR_SHIFT + 0))
153 #define FS_INTR_CLR (1 << (INTR_CLR_SHIFT + 1))
154 #define LINE_FLAG_INTR_CLR (1 << (INTR_CLR_SHIFT + 2))
155 #define BUS_ERROR_INTR_CLR (1 << (INTR_CLR_SHIFT + 3))
157 #define DSP_LINE_NUM(x) (((x) & 0x1fff) << 12)
158 #define DSP_LINE_NUM_MASK (0x1fff << 12)
160 /* src alpha ctrl define */
161 #define SRC_FADING_VALUE(x) (((x) & 0xff) << 24)
162 #define SRC_GLOBAL_ALPHA(x) (((x) & 0xff) << 16)
163 #define SRC_FACTOR_M0(x) (((x) & 0x7) << 6)
164 #define SRC_ALPHA_CAL_M0(x) (((x) & 0x1) << 5)
165 #define SRC_BLEND_M0(x) (((x) & 0x3) << 3)
166 #define SRC_ALPHA_M0(x) (((x) & 0x1) << 2)
167 #define SRC_COLOR_M0(x) (((x) & 0x1) << 1)
168 #define SRC_ALPHA_EN(x) (((x) & 0x1) << 0)
169 /* dst alpha ctrl define */
170 #define DST_FACTOR_M0(x) (((x) & 0x7) << 6)
173 * display output interface supported by rockchip lcdc
175 #define ROCKCHIP_OUT_MODE_P888 0
176 #define ROCKCHIP_OUT_MODE_P666 1
177 #define ROCKCHIP_OUT_MODE_P565 2
178 /* for use special outface */
179 #define ROCKCHIP_OUT_MODE_AAAA 15
186 enum global_blend_mode {
189 ALPHA_PER_PIX_GLOBAL,
192 enum alpha_cal_mode {
199 ALPHA_SRC_NO_PRE_MUL,
230 enum scale_down_mode {
231 SCALE_DOWN_BIL = 0x0,
235 #define FRAC_16_16(mult, div) (((mult) << 16) / (div))
236 #define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12
237 #define SCL_MAX_VSKIPLINES 4
238 #define MIN_SCL_FT_AFTER_VSKIP 1
240 static inline uint16_t scl_cal_scale(int src, int dst, int shift)
242 return ((src * 2 - 3) << (shift - 1)) / (dst - 1);
245 #define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12)
246 #define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16)
247 #define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16)
249 static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
254 act_height = (src_h + vskiplines - 1) / vskiplines;
256 return GET_SCL_FT_BILI_DN(act_height, dst_h);
259 static inline enum scale_mode scl_get_scl_mode(int src, int dst)
269 static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)
273 for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2)
274 if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP)
280 static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
285 lb_mode = LB_RGB_3840X2;
286 else if (width > 1920)
287 lb_mode = LB_RGB_2560X4;
289 lb_mode = LB_RGB_1920X5;
290 else if (width > 1280)
291 lb_mode = LB_YUV_3840X5;
293 lb_mode = LB_YUV_2560X8;
298 extern const struct component_ops vop_component_ops;
299 #endif /* _ROCKCHIP_DRM_VOP_H */