2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #ifndef _ROCKCHIP_DRM_VOP_H
16 #define _ROCKCHIP_DRM_VOP_H
19 * major: IP major vertion, used for IP structure
20 * minor: big feature change under same structure
22 #define VOP_VERSION(major, minor) ((major) << 8 | (minor))
23 #define VOP_MAJOR(version) ((version) >> 8)
24 #define VOP_MINOR(version) ((version) & 0xff)
26 #define AFBDC_FMT_RGB565 0x0
27 #define AFBDC_FMT_U8U8U8U8 0x5
28 #define AFBDC_FMT_U8U8U8 0x4
41 enum vop_data_format {
59 uint32_t begin_minor:4;
62 uint32_t write_mask:1;
66 struct vop_reg y2r_en;
67 struct vop_reg r2r_en;
68 struct vop_reg r2y_en;
76 struct vop_reg standby;
77 struct vop_reg htotal_pw;
78 struct vop_reg hact_st_end;
79 struct vop_reg vtotal_pw;
80 struct vop_reg vact_st_end;
81 struct vop_reg vact_st_end_f1;
82 struct vop_reg vs_st_end_f1;
83 struct vop_reg hpost_st_end;
84 struct vop_reg vpost_st_end;
85 struct vop_reg vpost_st_end_f1;
86 struct vop_reg post_scl_factor;
87 struct vop_reg post_scl_ctrl;
88 struct vop_reg dsp_interlace;
89 struct vop_reg global_regdone_en;
90 struct vop_reg auto_gate_en;
91 struct vop_reg post_lb_mode;
92 struct vop_reg dsp_layer_sel;
93 struct vop_reg overlay_mode;
94 struct vop_reg core_dclk_div;
95 struct vop_reg dclk_ddr;
96 struct vop_reg p2i_en;
97 struct vop_reg rgb_en;
98 struct vop_reg edp_en;
99 struct vop_reg hdmi_en;
100 struct vop_reg mipi_en;
101 struct vop_reg dp_en;
102 struct vop_reg pin_pol;
103 struct vop_reg rgb_pin_pol;
104 struct vop_reg hdmi_pin_pol;
105 struct vop_reg edp_pin_pol;
106 struct vop_reg mipi_pin_pol;
107 struct vop_reg dp_pin_pol;
109 struct vop_reg dither_up;
110 struct vop_reg dither_down;
112 struct vop_reg dsp_data_swap;
113 struct vop_reg dsp_ccir656_avg;
114 struct vop_reg dsp_black;
115 struct vop_reg dsp_blank;
116 struct vop_reg dsp_outzero;
117 struct vop_reg dsp_lut_en;
119 struct vop_reg out_mode;
121 struct vop_reg xmirror;
122 struct vop_reg ymirror;
123 struct vop_reg dsp_background;
126 struct vop_reg afbdc_en;
127 struct vop_reg afbdc_sel;
128 struct vop_reg afbdc_format;
129 struct vop_reg afbdc_hreg_block_split;
130 struct vop_reg afbdc_pic_size;
131 struct vop_reg afbdc_hdr_ptr;
132 struct vop_reg afbdc_rstn;
134 struct vop_reg cfg_done;
140 struct vop_reg line_flag_num[2];
141 struct vop_reg enable;
142 struct vop_reg clear;
143 struct vop_reg status;
146 struct vop_scl_extension {
147 struct vop_reg cbcr_vsd_mode;
148 struct vop_reg cbcr_vsu_mode;
149 struct vop_reg cbcr_hsd_mode;
150 struct vop_reg cbcr_ver_scl_mode;
151 struct vop_reg cbcr_hor_scl_mode;
152 struct vop_reg yrgb_vsd_mode;
153 struct vop_reg yrgb_vsu_mode;
154 struct vop_reg yrgb_hsd_mode;
155 struct vop_reg yrgb_ver_scl_mode;
156 struct vop_reg yrgb_hor_scl_mode;
157 struct vop_reg line_load_mode;
158 struct vop_reg cbcr_axi_gather_num;
159 struct vop_reg yrgb_axi_gather_num;
160 struct vop_reg vsd_cbcr_gt2;
161 struct vop_reg vsd_cbcr_gt4;
162 struct vop_reg vsd_yrgb_gt2;
163 struct vop_reg vsd_yrgb_gt4;
164 struct vop_reg bic_coe_sel;
165 struct vop_reg cbcr_axi_gather_en;
166 struct vop_reg yrgb_axi_gather_en;
167 struct vop_reg lb_mode;
170 struct vop_scl_regs {
171 const struct vop_scl_extension *ext;
173 struct vop_reg scale_yrgb_x;
174 struct vop_reg scale_yrgb_y;
175 struct vop_reg scale_cbcr_x;
176 struct vop_reg scale_cbcr_y;
179 struct vop_csc_table {
180 const uint32_t *y2r_bt601;
181 const uint32_t *y2r_bt601_12_235;
182 const uint32_t *y2r_bt601_10bit;
183 const uint32_t *y2r_bt601_10bit_12_235;
184 const uint32_t *r2y_bt601;
185 const uint32_t *r2y_bt601_12_235;
186 const uint32_t *r2y_bt601_10bit;
187 const uint32_t *r2y_bt601_10bit_12_235;
189 const uint32_t *y2r_bt709;
190 const uint32_t *y2r_bt709_10bit;
191 const uint32_t *r2y_bt709;
192 const uint32_t *r2y_bt709_10bit;
194 const uint32_t *y2r_bt2020;
195 const uint32_t *r2y_bt2020;
197 const uint32_t *r2r_bt709_to_bt2020;
198 const uint32_t *r2r_bt2020_to_bt709;
208 VOP_CSC_R2R_BT2020_TO_BT709,
209 VOP_CSC_R2R_BT709_TO_2020,
212 enum _vop_overlay_mode {
218 const struct vop_scl_regs *scl;
219 const uint32_t *data_formats;
223 struct vop_reg enable;
224 struct vop_reg format;
225 struct vop_reg fmt_10;
226 struct vop_reg xmirror;
227 struct vop_reg ymirror;
228 struct vop_reg rb_swap;
229 struct vop_reg act_info;
230 struct vop_reg dsp_info;
231 struct vop_reg dsp_st;
232 struct vop_reg yrgb_mst;
233 struct vop_reg uv_mst;
234 struct vop_reg yrgb_vir;
235 struct vop_reg uv_vir;
237 struct vop_reg dst_alpha_ctl;
238 struct vop_reg src_alpha_ctl;
239 struct vop_reg alpha_mode;
240 struct vop_reg alpha_en;
241 struct vop_reg key_color;
242 struct vop_reg key_en;
245 struct vop_win_data {
247 enum drm_plane_type type;
248 const struct vop_win_phy *phy;
249 const struct vop_win_phy **area;
250 const struct vop_csc *csc;
251 unsigned int area_size;
254 #define VOP_FEATURE_OUTPUT_10BIT BIT(0)
255 #define VOP_FEATURE_AFBDC BIT(1)
263 const struct vop_reg_data *init_table;
264 unsigned int table_size;
265 const struct vop_ctrl *ctrl;
266 const struct vop_intr *intr;
267 const struct vop_win_data *win;
268 const struct vop_csc_table *csc_table;
269 unsigned int win_size;
271 struct vop_rect max_input;
272 struct vop_rect max_output;
276 /* interrupt define */
277 #define DSP_HOLD_VALID_INTR (1 << 0)
278 #define FS_INTR (1 << 1)
279 #define LINE_FLAG_INTR (1 << 2)
280 #define BUS_ERROR_INTR (1 << 3)
281 #define FS_NEW_INTR (1 << 4)
282 #define ADDR_SAME_INTR (1 << 5)
283 #define LINE_FLAG1_INTR (1 << 6)
284 #define WIN0_EMPTY_INTR (1 << 7)
285 #define WIN1_EMPTY_INTR (1 << 8)
286 #define WIN2_EMPTY_INTR (1 << 9)
287 #define WIN3_EMPTY_INTR (1 << 10)
288 #define HWC_EMPTY_INTR (1 << 11)
289 #define POST_BUF_EMPTY_INTR (1 << 12)
290 #define PWM_GEN_INTR (1 << 13)
292 #define INTR_MASK (DSP_HOLD_VALID_INTR | FS_INTR | \
293 LINE_FLAG_INTR | BUS_ERROR_INTR | \
294 FS_NEW_INTR | LINE_FLAG1_INTR | \
295 WIN0_EMPTY_INTR | WIN1_EMPTY_INTR | \
296 WIN2_EMPTY_INTR | WIN3_EMPTY_INTR | \
297 HWC_EMPTY_INTR | POST_BUF_EMPTY_INTR)
299 #define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4)
300 #define FS_INTR_EN(x) ((x) << 5)
301 #define LINE_FLAG_INTR_EN(x) ((x) << 6)
302 #define BUS_ERROR_INTR_EN(x) ((x) << 7)
303 #define DSP_HOLD_VALID_INTR_MASK (1 << 4)
304 #define FS_INTR_MASK (1 << 5)
305 #define LINE_FLAG_INTR_MASK (1 << 6)
306 #define BUS_ERROR_INTR_MASK (1 << 7)
308 #define INTR_CLR_SHIFT 8
309 #define DSP_HOLD_VALID_INTR_CLR (1 << (INTR_CLR_SHIFT + 0))
310 #define FS_INTR_CLR (1 << (INTR_CLR_SHIFT + 1))
311 #define LINE_FLAG_INTR_CLR (1 << (INTR_CLR_SHIFT + 2))
312 #define BUS_ERROR_INTR_CLR (1 << (INTR_CLR_SHIFT + 3))
314 #define DSP_LINE_NUM(x) (((x) & 0x1fff) << 12)
315 #define DSP_LINE_NUM_MASK (0x1fff << 12)
317 /* src alpha ctrl define */
318 #define SRC_FADING_VALUE(x) (((x) & 0xff) << 24)
319 #define SRC_GLOBAL_ALPHA(x) (((x) & 0xff) << 16)
320 #define SRC_FACTOR_M0(x) (((x) & 0x7) << 6)
321 #define SRC_ALPHA_CAL_M0(x) (((x) & 0x1) << 5)
322 #define SRC_BLEND_M0(x) (((x) & 0x3) << 3)
323 #define SRC_ALPHA_M0(x) (((x) & 0x1) << 2)
324 #define SRC_COLOR_M0(x) (((x) & 0x1) << 1)
325 #define SRC_ALPHA_EN(x) (((x) & 0x1) << 0)
326 /* dst alpha ctrl define */
327 #define DST_FACTOR_M0(x) (((x) & 0x7) << 6)
330 * display output interface supported by rockchip lcdc
332 #define ROCKCHIP_OUT_MODE_P888 0
333 #define ROCKCHIP_OUT_MODE_P666 1
334 #define ROCKCHIP_OUT_MODE_P565 2
335 #define ROCKCHIP_OUT_MODE_YUV420 14
336 /* for use special outface */
337 #define ROCKCHIP_OUT_MODE_AAAA 15
339 #define ROCKCHIP_OUT_MODE_TYPE(x) ((x) >> 16)
340 #define ROCKCHIP_OUT_MODE(x) ((x) & 0xffff)
341 #define ROCKCHIP_DSP_MODE(type, mode) \
342 (DRM_MODE_CONNECTOR_##type << 16) | \
343 (ROCKCHIP_OUT_MODE_##mode & 0xffff)
350 enum global_blend_mode {
353 ALPHA_PER_PIX_GLOBAL,
356 enum alpha_cal_mode {
363 ALPHA_SRC_NO_PRE_MUL,
394 enum scale_down_mode {
395 SCALE_DOWN_BIL = 0x0,
399 enum dither_down_mode {
400 RGB888_TO_RGB565 = 0x0,
401 RGB888_TO_RGB666 = 0x1
404 enum dither_down_mode_sel {
405 DITHER_DOWN_ALLEGRO = 0x0,
406 DITHER_DOWN_FRC = 0x1
409 #define PRE_DITHER_DOWN_EN(x) ((x) << 0)
410 #define DITHER_DOWN_EN(x) ((x) << 1)
411 #define DITHER_DOWN_MODE(x) ((x) << 2)
412 #define DITHER_DOWN_MODE_SEL(x) ((x) << 3)
421 #define FRAC_16_16(mult, div) (((mult) << 16) / (div))
422 #define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12
423 #define SCL_MAX_VSKIPLINES 4
424 #define MIN_SCL_FT_AFTER_VSKIP 1
426 static inline uint16_t scl_cal_scale(int src, int dst, int shift)
428 return ((src * 2 - 3) << (shift - 1)) / (dst - 1);
431 static inline uint16_t scl_cal_scale2(int src, int dst)
433 return ((src - 1) << 12) / (dst - 1);
436 #define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12)
437 #define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16)
438 #define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16)
440 static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
445 act_height = (src_h + vskiplines - 1) / vskiplines;
447 return GET_SCL_FT_BILI_DN(act_height, dst_h);
450 static inline enum scale_mode scl_get_scl_mode(int src, int dst)
460 static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)
464 for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2)
465 if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP)
471 static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
476 lb_mode = LB_RGB_3840X2;
477 else if (width > 1920)
478 lb_mode = LB_RGB_2560X4;
480 lb_mode = LB_RGB_1920X5;
481 else if (width > 1280)
482 lb_mode = LB_YUV_3840X5;
484 lb_mode = LB_YUV_2560X8;
489 extern const struct component_ops vop_component_ops;
490 #endif /* _ROCKCHIP_DRM_VOP_H */