2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #ifndef _ROCKCHIP_DRM_VOP_H
16 #define _ROCKCHIP_DRM_VOP_H
19 * major: IP major vertion, used for IP structure
20 * minor: big feature change under same structure
22 #define VOP_VERSION(major, minor) ((major) << 8 | (minor))
23 #define VOP_MAJOR(version) ((version) >> 8)
24 #define VOP_MINOR(version) ((version) & 0xff)
26 #define AFBDC_FMT_RGB565 0x0
27 #define AFBDC_FMT_U8U8U8U8 0x5
28 #define AFBDC_FMT_U8U8U8 0x4
41 enum vop_data_format {
59 uint32_t begin_minor:4;
62 uint32_t write_mask:1;
66 struct vop_reg y2r_en;
67 struct vop_reg r2r_en;
68 struct vop_reg r2y_en;
76 struct vop_reg standby;
77 struct vop_reg htotal_pw;
78 struct vop_reg hact_st_end;
79 struct vop_reg vtotal_pw;
80 struct vop_reg vact_st_end;
81 struct vop_reg vact_st_end_f1;
82 struct vop_reg vs_st_end_f1;
83 struct vop_reg hpost_st_end;
84 struct vop_reg vpost_st_end;
85 struct vop_reg vpost_st_end_f1;
86 struct vop_reg dsp_interlace;
87 struct vop_reg global_regdone_en;
88 struct vop_reg auto_gate_en;
89 struct vop_reg post_lb_mode;
90 struct vop_reg dsp_layer_sel;
91 struct vop_reg overlay_mode;
92 struct vop_reg core_dclk_div;
93 struct vop_reg p2i_en;
94 struct vop_reg rgb_en;
95 struct vop_reg edp_en;
96 struct vop_reg hdmi_en;
97 struct vop_reg mipi_en;
98 struct vop_reg pin_pol;
99 struct vop_reg rgb_pin_pol;
100 struct vop_reg hdmi_pin_pol;
101 struct vop_reg edp_pin_pol;
102 struct vop_reg mipi_pin_pol;
104 struct vop_reg dither_up;
105 struct vop_reg dither_down;
107 struct vop_reg dsp_data_swap;
108 struct vop_reg dsp_ccir656_avg;
109 struct vop_reg dsp_black;
110 struct vop_reg dsp_blank;
111 struct vop_reg dsp_outzero;
112 struct vop_reg dsp_lut_en;
114 struct vop_reg out_mode;
116 struct vop_reg xmirror;
117 struct vop_reg ymirror;
118 struct vop_reg dsp_background;
121 struct vop_reg afbdc_en;
122 struct vop_reg afbdc_sel;
123 struct vop_reg afbdc_format;
124 struct vop_reg afbdc_hreg_block_split;
125 struct vop_reg afbdc_pic_size;
126 struct vop_reg afbdc_hdr_ptr;
127 struct vop_reg afbdc_rstn;
129 struct vop_reg cfg_done;
135 struct vop_reg line_flag_num[2];
136 struct vop_reg enable;
137 struct vop_reg clear;
138 struct vop_reg status;
141 struct vop_scl_extension {
142 struct vop_reg cbcr_vsd_mode;
143 struct vop_reg cbcr_vsu_mode;
144 struct vop_reg cbcr_hsd_mode;
145 struct vop_reg cbcr_ver_scl_mode;
146 struct vop_reg cbcr_hor_scl_mode;
147 struct vop_reg yrgb_vsd_mode;
148 struct vop_reg yrgb_vsu_mode;
149 struct vop_reg yrgb_hsd_mode;
150 struct vop_reg yrgb_ver_scl_mode;
151 struct vop_reg yrgb_hor_scl_mode;
152 struct vop_reg line_load_mode;
153 struct vop_reg cbcr_axi_gather_num;
154 struct vop_reg yrgb_axi_gather_num;
155 struct vop_reg vsd_cbcr_gt2;
156 struct vop_reg vsd_cbcr_gt4;
157 struct vop_reg vsd_yrgb_gt2;
158 struct vop_reg vsd_yrgb_gt4;
159 struct vop_reg bic_coe_sel;
160 struct vop_reg cbcr_axi_gather_en;
161 struct vop_reg yrgb_axi_gather_en;
162 struct vop_reg lb_mode;
165 struct vop_scl_regs {
166 const struct vop_scl_extension *ext;
168 struct vop_reg scale_yrgb_x;
169 struct vop_reg scale_yrgb_y;
170 struct vop_reg scale_cbcr_x;
171 struct vop_reg scale_cbcr_y;
174 struct vop_csc_table {
175 const uint32_t *y2r_bt601;
176 const uint32_t *y2r_bt601_12_235;
177 const uint32_t *y2r_bt601_10bit;
178 const uint32_t *y2r_bt601_10bit_12_235;
179 const uint32_t *r2y_bt601;
180 const uint32_t *r2y_bt601_12_235;
181 const uint32_t *r2y_bt601_10bit;
182 const uint32_t *r2y_bt601_10bit_12_235;
184 const uint32_t *y2r_bt709;
185 const uint32_t *y2r_bt709_10bit;
186 const uint32_t *r2y_bt709;
187 const uint32_t *r2y_bt709_10bit;
189 const uint32_t *y2r_bt2020;
190 const uint32_t *r2y_bt2020;
192 const uint32_t *r2r_bt709_to_bt2020;
193 const uint32_t *r2r_bt2020_to_bt709;
203 VOP_CSC_R2R_BT2020_TO_BT709,
204 VOP_CSC_R2R_BT709_TO_2020,
208 const struct vop_scl_regs *scl;
209 const uint32_t *data_formats;
213 struct vop_reg enable;
214 struct vop_reg format;
215 struct vop_reg fmt_10;
216 struct vop_reg xmirror;
217 struct vop_reg ymirror;
218 struct vop_reg rb_swap;
219 struct vop_reg act_info;
220 struct vop_reg dsp_info;
221 struct vop_reg dsp_st;
222 struct vop_reg yrgb_mst;
223 struct vop_reg uv_mst;
224 struct vop_reg yrgb_vir;
225 struct vop_reg uv_vir;
227 struct vop_reg dst_alpha_ctl;
228 struct vop_reg src_alpha_ctl;
229 struct vop_reg alpha_mode;
230 struct vop_reg alpha_en;
231 struct vop_reg key_color;
232 struct vop_reg key_en;
235 struct vop_win_data {
237 enum drm_plane_type type;
238 const struct vop_win_phy *phy;
239 const struct vop_win_phy **area;
240 const struct vop_csc *csc;
241 unsigned int area_size;
244 #define VOP_FEATURE_OUTPUT_10BIT BIT(0)
245 #define VOP_FEATURE_AFBDC BIT(1)
248 const struct vop_reg_data *init_table;
249 unsigned int table_size;
250 const struct vop_ctrl *ctrl;
251 const struct vop_intr *intr;
252 const struct vop_win_data *win;
253 const struct vop_csc_table *csc_table;
254 unsigned int win_size;
259 /* interrupt define */
260 #define DSP_HOLD_VALID_INTR (1 << 0)
261 #define FS_INTR (1 << 1)
262 #define LINE_FLAG_INTR (1 << 2)
263 #define BUS_ERROR_INTR (1 << 3)
264 #define FS_NEW_INTR (1 << 4)
265 #define ADDR_SAME_INTR (1 << 5)
266 #define LINE_FLAG1_INTR (1 << 6)
267 #define WIN0_EMPTY_INTR (1 << 7)
268 #define WIN1_EMPTY_INTR (1 << 8)
269 #define WIN2_EMPTY_INTR (1 << 9)
270 #define WIN3_EMPTY_INTR (1 << 10)
271 #define HWC_EMPTY_INTR (1 << 11)
272 #define POST_BUF_EMPTY_INTR (1 << 12)
273 #define PWM_GEN_INTR (1 << 13)
275 #define INTR_MASK (DSP_HOLD_VALID_INTR | FS_INTR | \
276 LINE_FLAG_INTR | BUS_ERROR_INTR | \
277 FS_NEW_INTR | LINE_FLAG1_INTR | \
278 WIN0_EMPTY_INTR | WIN1_EMPTY_INTR | \
279 WIN2_EMPTY_INTR | WIN3_EMPTY_INTR | \
280 HWC_EMPTY_INTR | POST_BUF_EMPTY_INTR)
282 #define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4)
283 #define FS_INTR_EN(x) ((x) << 5)
284 #define LINE_FLAG_INTR_EN(x) ((x) << 6)
285 #define BUS_ERROR_INTR_EN(x) ((x) << 7)
286 #define DSP_HOLD_VALID_INTR_MASK (1 << 4)
287 #define FS_INTR_MASK (1 << 5)
288 #define LINE_FLAG_INTR_MASK (1 << 6)
289 #define BUS_ERROR_INTR_MASK (1 << 7)
291 #define INTR_CLR_SHIFT 8
292 #define DSP_HOLD_VALID_INTR_CLR (1 << (INTR_CLR_SHIFT + 0))
293 #define FS_INTR_CLR (1 << (INTR_CLR_SHIFT + 1))
294 #define LINE_FLAG_INTR_CLR (1 << (INTR_CLR_SHIFT + 2))
295 #define BUS_ERROR_INTR_CLR (1 << (INTR_CLR_SHIFT + 3))
297 #define DSP_LINE_NUM(x) (((x) & 0x1fff) << 12)
298 #define DSP_LINE_NUM_MASK (0x1fff << 12)
300 /* src alpha ctrl define */
301 #define SRC_FADING_VALUE(x) (((x) & 0xff) << 24)
302 #define SRC_GLOBAL_ALPHA(x) (((x) & 0xff) << 16)
303 #define SRC_FACTOR_M0(x) (((x) & 0x7) << 6)
304 #define SRC_ALPHA_CAL_M0(x) (((x) & 0x1) << 5)
305 #define SRC_BLEND_M0(x) (((x) & 0x3) << 3)
306 #define SRC_ALPHA_M0(x) (((x) & 0x1) << 2)
307 #define SRC_COLOR_M0(x) (((x) & 0x1) << 1)
308 #define SRC_ALPHA_EN(x) (((x) & 0x1) << 0)
309 /* dst alpha ctrl define */
310 #define DST_FACTOR_M0(x) (((x) & 0x7) << 6)
313 * display output interface supported by rockchip lcdc
315 #define ROCKCHIP_OUT_MODE_P888 0
316 #define ROCKCHIP_OUT_MODE_P666 1
317 #define ROCKCHIP_OUT_MODE_P565 2
318 /* for use special outface */
319 #define ROCKCHIP_OUT_MODE_AAAA 15
321 #define ROCKCHIP_OUT_MODE_TYPE(x) ((x) >> 16)
322 #define ROCKCHIP_OUT_MODE(x) ((x) & 0xffff)
323 #define ROCKCHIP_DSP_MODE(type, mode) \
324 (DRM_MODE_CONNECTOR_##type << 16) | \
325 (ROCKCHIP_OUT_MODE_##mode & 0xffff)
332 enum global_blend_mode {
335 ALPHA_PER_PIX_GLOBAL,
338 enum alpha_cal_mode {
345 ALPHA_SRC_NO_PRE_MUL,
376 enum scale_down_mode {
377 SCALE_DOWN_BIL = 0x0,
381 #define FRAC_16_16(mult, div) (((mult) << 16) / (div))
382 #define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12
383 #define SCL_MAX_VSKIPLINES 4
384 #define MIN_SCL_FT_AFTER_VSKIP 1
386 static inline uint16_t scl_cal_scale(int src, int dst, int shift)
388 return ((src * 2 - 3) << (shift - 1)) / (dst - 1);
391 static inline uint16_t scl_cal_scale2(int src, int dst)
393 return ((src - 1) << 12) / (dst - 1);
396 #define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12)
397 #define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16)
398 #define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16)
400 static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
405 act_height = (src_h + vskiplines - 1) / vskiplines;
407 return GET_SCL_FT_BILI_DN(act_height, dst_h);
410 static inline enum scale_mode scl_get_scl_mode(int src, int dst)
420 static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)
424 for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2)
425 if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP)
431 static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
436 lb_mode = LB_RGB_3840X2;
437 else if (width > 1920)
438 lb_mode = LB_RGB_2560X4;
440 lb_mode = LB_RGB_1920X5;
441 else if (width > 1280)
442 lb_mode = LB_YUV_3840X5;
444 lb_mode = LB_YUV_2560X8;
449 extern const struct component_ops vop_component_ops;
450 #endif /* _ROCKCHIP_DRM_VOP_H */