2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #ifndef _ROCKCHIP_DRM_VOP_H
16 #define _ROCKCHIP_DRM_VOP_H
19 * major: IP major vertion, used for IP structure
20 * minor: big feature change under same structure
22 #define VOP_VERSION(major, minor) ((major) << 8 | (minor))
23 #define VOP_MAJOR(version) ((version) >> 8)
24 #define VOP_MINOR(version) ((version) & 0xff)
37 enum vop_data_format {
55 uint32_t begin_minor:4;
58 uint32_t write_mask:1;
62 struct vop_reg y2r_en;
63 struct vop_reg r2r_en;
64 struct vop_reg r2y_en;
72 struct vop_reg standby;
73 struct vop_reg htotal_pw;
74 struct vop_reg hact_st_end;
75 struct vop_reg vtotal_pw;
76 struct vop_reg vact_st_end;
77 struct vop_reg vact_st_end_f1;
78 struct vop_reg hpost_st_end;
79 struct vop_reg vpost_st_end;
80 struct vop_reg vpost_st_end_f1;
81 struct vop_reg dsp_interlace;
82 struct vop_reg global_regdone_en;
83 struct vop_reg auto_gate_en;
84 struct vop_reg post_lb_mode;
85 struct vop_reg dsp_layer_sel;
86 struct vop_reg overlay_mode;
87 struct vop_reg core_dclk_div;
88 struct vop_reg p2i_en;
89 struct vop_reg rgb_en;
90 struct vop_reg edp_en;
91 struct vop_reg hdmi_en;
92 struct vop_reg mipi_en;
93 struct vop_reg pin_pol;
94 struct vop_reg rgb_pin_pol;
95 struct vop_reg hdmi_pin_pol;
96 struct vop_reg edp_pin_pol;
97 struct vop_reg mipi_pin_pol;
99 struct vop_reg dither_up;
100 struct vop_reg dither_down;
102 struct vop_reg dsp_data_swap;
103 struct vop_reg dsp_ccir656_avg;
104 struct vop_reg dsp_black;
105 struct vop_reg dsp_blank;
106 struct vop_reg dsp_outzero;
107 struct vop_reg dsp_lut_en;
109 struct vop_reg out_mode;
111 struct vop_reg xmirror;
112 struct vop_reg ymirror;
113 struct vop_reg dsp_background;
115 struct vop_reg cfg_done;
121 struct vop_reg line_flag_num;
122 struct vop_reg enable;
123 struct vop_reg clear;
124 struct vop_reg status;
127 struct vop_scl_extension {
128 struct vop_reg cbcr_vsd_mode;
129 struct vop_reg cbcr_vsu_mode;
130 struct vop_reg cbcr_hsd_mode;
131 struct vop_reg cbcr_ver_scl_mode;
132 struct vop_reg cbcr_hor_scl_mode;
133 struct vop_reg yrgb_vsd_mode;
134 struct vop_reg yrgb_vsu_mode;
135 struct vop_reg yrgb_hsd_mode;
136 struct vop_reg yrgb_ver_scl_mode;
137 struct vop_reg yrgb_hor_scl_mode;
138 struct vop_reg line_load_mode;
139 struct vop_reg cbcr_axi_gather_num;
140 struct vop_reg yrgb_axi_gather_num;
141 struct vop_reg vsd_cbcr_gt2;
142 struct vop_reg vsd_cbcr_gt4;
143 struct vop_reg vsd_yrgb_gt2;
144 struct vop_reg vsd_yrgb_gt4;
145 struct vop_reg bic_coe_sel;
146 struct vop_reg cbcr_axi_gather_en;
147 struct vop_reg yrgb_axi_gather_en;
148 struct vop_reg lb_mode;
151 struct vop_scl_regs {
152 const struct vop_scl_extension *ext;
154 struct vop_reg scale_yrgb_x;
155 struct vop_reg scale_yrgb_y;
156 struct vop_reg scale_cbcr_x;
157 struct vop_reg scale_cbcr_y;
160 struct vop_csc_table {
161 const uint32_t *y2r_bt601;
162 const uint32_t *y2r_bt601_12_235;
163 const uint32_t *y2r_bt601_10bit;
164 const uint32_t *y2r_bt601_10bit_12_235;
165 const uint32_t *r2y_bt601;
166 const uint32_t *r2y_bt601_12_235;
167 const uint32_t *r2y_bt601_10bit;
168 const uint32_t *r2y_bt601_10bit_12_235;
170 const uint32_t *y2r_bt709;
171 const uint32_t *y2r_bt709_10bit;
172 const uint32_t *r2y_bt709;
173 const uint32_t *r2y_bt709_10bit;
175 const uint32_t *y2r_bt2020;
176 const uint32_t *r2y_bt2020;
178 const uint32_t *r2r_bt709_to_bt2020;
179 const uint32_t *r2r_bt2020_to_bt709;
189 VOP_CSC_R2R_BT2020_TO_BT709,
190 VOP_CSC_R2R_BT709_TO_2020,
194 const struct vop_scl_regs *scl;
195 const uint32_t *data_formats;
199 struct vop_reg enable;
200 struct vop_reg format;
201 struct vop_reg xmirror;
202 struct vop_reg ymirror;
203 struct vop_reg rb_swap;
204 struct vop_reg act_info;
205 struct vop_reg dsp_info;
206 struct vop_reg dsp_st;
207 struct vop_reg yrgb_mst;
208 struct vop_reg uv_mst;
209 struct vop_reg yrgb_vir;
210 struct vop_reg uv_vir;
212 struct vop_reg dst_alpha_ctl;
213 struct vop_reg src_alpha_ctl;
214 struct vop_reg alpha_mode;
215 struct vop_reg alpha_en;
216 struct vop_reg key_color;
217 struct vop_reg key_en;
220 struct vop_win_data {
222 enum drm_plane_type type;
223 const struct vop_win_phy *phy;
224 const struct vop_win_phy **area;
225 const struct vop_csc *csc;
226 unsigned int area_size;
229 #define VOP_FEATURE_OUTPUT_10BIT BIT(0)
232 const struct vop_reg_data *init_table;
233 unsigned int table_size;
234 const struct vop_ctrl *ctrl;
235 const struct vop_intr *intr;
236 const struct vop_win_data *win;
237 const struct vop_csc_table *csc_table;
238 unsigned int win_size;
243 /* interrupt define */
244 #define DSP_HOLD_VALID_INTR (1 << 0)
245 #define FS_INTR (1 << 1)
246 #define LINE_FLAG_INTR (1 << 2)
247 #define BUS_ERROR_INTR (1 << 3)
248 #define FS_NEW_INTR (1 << 4)
249 #define ADDR_SAME_INTR (1 << 5)
250 #define LINE_FLAG1_INTR (1 << 6)
251 #define WIN0_EMPTY_INTR (1 << 7)
252 #define WIN1_EMPTY_INTR (1 << 8)
253 #define WIN2_EMPTY_INTR (1 << 9)
254 #define WIN3_EMPTY_INTR (1 << 10)
255 #define HWC_EMPTY_INTR (1 << 11)
256 #define POST_BUF_EMPTY_INTR (1 << 12)
257 #define PWM_GEN_INTR (1 << 13)
259 #define INTR_MASK (DSP_HOLD_VALID_INTR | FS_INTR | \
260 LINE_FLAG_INTR | BUS_ERROR_INTR | \
261 FS_NEW_INTR | LINE_FLAG1_INTR | \
262 WIN0_EMPTY_INTR | WIN1_EMPTY_INTR | \
263 WIN2_EMPTY_INTR | WIN3_EMPTY_INTR | \
264 HWC_EMPTY_INTR | POST_BUF_EMPTY_INTR)
266 #define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4)
267 #define FS_INTR_EN(x) ((x) << 5)
268 #define LINE_FLAG_INTR_EN(x) ((x) << 6)
269 #define BUS_ERROR_INTR_EN(x) ((x) << 7)
270 #define DSP_HOLD_VALID_INTR_MASK (1 << 4)
271 #define FS_INTR_MASK (1 << 5)
272 #define LINE_FLAG_INTR_MASK (1 << 6)
273 #define BUS_ERROR_INTR_MASK (1 << 7)
275 #define INTR_CLR_SHIFT 8
276 #define DSP_HOLD_VALID_INTR_CLR (1 << (INTR_CLR_SHIFT + 0))
277 #define FS_INTR_CLR (1 << (INTR_CLR_SHIFT + 1))
278 #define LINE_FLAG_INTR_CLR (1 << (INTR_CLR_SHIFT + 2))
279 #define BUS_ERROR_INTR_CLR (1 << (INTR_CLR_SHIFT + 3))
281 #define DSP_LINE_NUM(x) (((x) & 0x1fff) << 12)
282 #define DSP_LINE_NUM_MASK (0x1fff << 12)
284 /* src alpha ctrl define */
285 #define SRC_FADING_VALUE(x) (((x) & 0xff) << 24)
286 #define SRC_GLOBAL_ALPHA(x) (((x) & 0xff) << 16)
287 #define SRC_FACTOR_M0(x) (((x) & 0x7) << 6)
288 #define SRC_ALPHA_CAL_M0(x) (((x) & 0x1) << 5)
289 #define SRC_BLEND_M0(x) (((x) & 0x3) << 3)
290 #define SRC_ALPHA_M0(x) (((x) & 0x1) << 2)
291 #define SRC_COLOR_M0(x) (((x) & 0x1) << 1)
292 #define SRC_ALPHA_EN(x) (((x) & 0x1) << 0)
293 /* dst alpha ctrl define */
294 #define DST_FACTOR_M0(x) (((x) & 0x7) << 6)
297 * display output interface supported by rockchip lcdc
299 #define ROCKCHIP_OUT_MODE_P888 0
300 #define ROCKCHIP_OUT_MODE_P666 1
301 #define ROCKCHIP_OUT_MODE_P565 2
302 /* for use special outface */
303 #define ROCKCHIP_OUT_MODE_AAAA 15
305 #define ROCKCHIP_OUT_MODE_TYPE(x) ((x) >> 16)
306 #define ROCKCHIP_OUT_MODE(x) ((x) & 0xffff)
307 #define ROCKCHIP_DSP_MODE(type, mode) \
308 (DRM_MODE_CONNECTOR_##type << 16) | \
309 (ROCKCHIP_OUT_MODE_##mode & 0xffff)
316 enum global_blend_mode {
319 ALPHA_PER_PIX_GLOBAL,
322 enum alpha_cal_mode {
329 ALPHA_SRC_NO_PRE_MUL,
360 enum scale_down_mode {
361 SCALE_DOWN_BIL = 0x0,
365 #define FRAC_16_16(mult, div) (((mult) << 16) / (div))
366 #define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12
367 #define SCL_MAX_VSKIPLINES 4
368 #define MIN_SCL_FT_AFTER_VSKIP 1
370 static inline uint16_t scl_cal_scale(int src, int dst, int shift)
372 return ((src * 2 - 3) << (shift - 1)) / (dst - 1);
375 static inline uint16_t scl_cal_scale2(int src, int dst)
377 return ((src - 1) << 12) / (dst - 1);
380 #define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12)
381 #define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16)
382 #define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16)
384 static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
389 act_height = (src_h + vskiplines - 1) / vskiplines;
391 return GET_SCL_FT_BILI_DN(act_height, dst_h);
394 static inline enum scale_mode scl_get_scl_mode(int src, int dst)
404 static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)
408 for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2)
409 if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP)
415 static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
420 lb_mode = LB_RGB_3840X2;
421 else if (width > 1920)
422 lb_mode = LB_RGB_2560X4;
424 lb_mode = LB_RGB_1920X5;
425 else if (width > 1280)
426 lb_mode = LB_YUV_3840X5;
428 lb_mode = LB_YUV_2560X8;
433 extern const struct component_ops vop_component_ops;
434 #endif /* _ROCKCHIP_DRM_VOP_H */