drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/clk.h>
  26 #include <linux/of.h>
  27 #include <linux/of_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/component.h>
  30
  31 #include <linux/reset.h>
  32 #include <linux/delay.h>
  33
  34 #include "rockchip_drm_drv.h"
  35 #include "rockchip_drm_gem.h"
  36 #include "rockchip_drm_fb.h"
  37 #include "rockchip_drm_vop.h"
  38
  39 #define VOP_REG(off, _mask, s) \
  40                 {.offset = off, \
  41                  .mask = _mask, \
  42                  .shift = s,}
  43
  44 #define __REG_SET_RELAXED(x, off, mask, shift, v) \
  45                 vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift)
  46 #define __REG_SET_NORMAL(x, off, mask, shift, v) \
  47                 vop_mask_write(x, off, (mask) << shift, (v) << shift)
  48
  49 #define REG_SET(x, base, reg, v, mode) \
  50                 __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v)
  51
  52 #define VOP_WIN_SET(x, win, name, v) \
  53                 REG_SET(x, win->base, win->phy->name, v, RELAXED)
  54 #define VOP_SCL_SET(x, win, name, v) \
  55                 REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
  56 #define VOP_CTRL_SET(x, name, v) \
  57                 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
  58
  59 #define VOP_WIN_GET(x, win, name) \
  60                 vop_read_reg(x, win->base, &win->phy->name)
  61
  62 #define VOP_WIN_GET_YRGBADDR(vop, win) \
  63                 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
  64
  65 #define to_vop(x) container_of(x, struct vop, crtc)
  66 #define to_vop_win(x) container_of(x, struct vop_win, base)
  67 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
  68
  69 struct vop_plane_state {
  70         struct drm_plane_state base;
  71         int format;
  72         struct drm_rect src;
  73         struct drm_rect dest;
  74         dma_addr_t yrgb_mst;
  75         bool enable;
  76 };
  77
  78 struct vop_win {
  79         struct drm_plane base;
  80         const struct vop_win_data *data;
  81         struct vop *vop;
  82
  83         struct vop_plane_state state;
  84 };
  85
  86 struct vop {
  87         struct drm_crtc crtc;
  88         struct device *dev;
  89         struct drm_device *drm_dev;
  90         bool is_enabled;
  91
  92         /* mutex vsync_ work */
  93         struct mutex vsync_mutex;
  94         bool vsync_work_pending;
  95         struct completion dsp_hold_completion;
  96         struct completion wait_update_complete;
  97         struct drm_pending_vblank_event *event;
  98
  99         const struct vop_data *data;
 100
 101         uint32_t *regsbak;
 102         void __iomem *regs;
 103
 104         /* physical map length of vop register */
 105         uint32_t len;
 106
 107         /* one time only one process allowed to config the register */
 108         spinlock_t reg_lock;
 109         /* lock vop irq reg */
 110         spinlock_t irq_lock;
 111
 112         unsigned int irq;
 113
 114         /* vop AHP clk */
 115         struct clk *hclk;
 116         /* vop dclk */
 117         struct clk *dclk;
 118         /* vop share memory frequency */
 119         struct clk *aclk;
 120
 121         /* vop dclk reset */
 122         struct reset_control *dclk_rst;
 123
 124         struct vop_win win[];
 125 };
 126
 127 enum vop_data_format {
 128         VOP_FMT_ARGB8888 = 0,
 129         VOP_FMT_RGB888,
 130         VOP_FMT_RGB565,
 131         VOP_FMT_YUV420SP = 4,
 132         VOP_FMT_YUV422SP,
 133         VOP_FMT_YUV444SP,
 134 };
 135
 136 struct vop_reg_data {
 137         uint32_t offset;
 138         uint32_t value;
 139 };
 140
 141 struct vop_reg {
 142         uint32_t offset;
 143         uint32_t shift;
 144         uint32_t mask;
 145 };
 146
 147 struct vop_ctrl {
 148         struct vop_reg standby;
 149         struct vop_reg data_blank;
 150         struct vop_reg gate_en;
 151         struct vop_reg mmu_en;
 152         struct vop_reg rgb_en;
 153         struct vop_reg edp_en;
 154         struct vop_reg hdmi_en;
 155         struct vop_reg mipi_en;
 156         struct vop_reg out_mode;
 157         struct vop_reg dither_down;
 158         struct vop_reg dither_up;
 159         struct vop_reg pin_pol;
 160
 161         struct vop_reg htotal_pw;
 162         struct vop_reg hact_st_end;
 163         struct vop_reg vtotal_pw;
 164         struct vop_reg vact_st_end;
 165         struct vop_reg hpost_st_end;
 166         struct vop_reg vpost_st_end;
 167 };
 168
 169 struct vop_scl_regs {
 170         struct vop_reg cbcr_vsd_mode;
 171         struct vop_reg cbcr_vsu_mode;
 172         struct vop_reg cbcr_hsd_mode;
 173         struct vop_reg cbcr_ver_scl_mode;
 174         struct vop_reg cbcr_hor_scl_mode;
 175         struct vop_reg yrgb_vsd_mode;
 176         struct vop_reg yrgb_vsu_mode;
 177         struct vop_reg yrgb_hsd_mode;
 178         struct vop_reg yrgb_ver_scl_mode;
 179         struct vop_reg yrgb_hor_scl_mode;
 180         struct vop_reg line_load_mode;
 181         struct vop_reg cbcr_axi_gather_num;
 182         struct vop_reg yrgb_axi_gather_num;
 183         struct vop_reg vsd_cbcr_gt2;
 184         struct vop_reg vsd_cbcr_gt4;
 185         struct vop_reg vsd_yrgb_gt2;
 186         struct vop_reg vsd_yrgb_gt4;
 187         struct vop_reg bic_coe_sel;
 188         struct vop_reg cbcr_axi_gather_en;
 189         struct vop_reg yrgb_axi_gather_en;
 190
 191         struct vop_reg lb_mode;
 192         struct vop_reg scale_yrgb_x;
 193         struct vop_reg scale_yrgb_y;
 194         struct vop_reg scale_cbcr_x;
 195         struct vop_reg scale_cbcr_y;
 196 };
 197
 198 struct vop_win_phy {
 199         const struct vop_scl_regs *scl;
 200         const uint32_t *data_formats;
 201         uint32_t nformats;
 202
 203         struct vop_reg enable;
 204         struct vop_reg format;
 205         struct vop_reg rb_swap;
 206         struct vop_reg act_info;
 207         struct vop_reg dsp_info;
 208         struct vop_reg dsp_st;
 209         struct vop_reg yrgb_mst;
 210         struct vop_reg uv_mst;
 211         struct vop_reg yrgb_vir;
 212         struct vop_reg uv_vir;
 213
 214         struct vop_reg dst_alpha_ctl;
 215         struct vop_reg src_alpha_ctl;
 216 };
 217
 218 struct vop_win_data {
 219         uint32_t base;
 220         const struct vop_win_phy *phy;
 221         enum drm_plane_type type;
 222 };
 223
 224 struct vop_data {
 225         const struct vop_reg_data *init_table;
 226         unsigned int table_size;
 227         const struct vop_ctrl *ctrl;
 228         const struct vop_win_data *win;
 229         unsigned int win_size;
 230 };
 231
 232 static const uint32_t formats_01[] = {
 233         DRM_FORMAT_XRGB8888,
 234         DRM_FORMAT_ARGB8888,
 235         DRM_FORMAT_XBGR8888,
 236         DRM_FORMAT_ABGR8888,
 237         DRM_FORMAT_RGB888,
 238         DRM_FORMAT_BGR888,
 239         DRM_FORMAT_RGB565,
 240         DRM_FORMAT_BGR565,
 241         DRM_FORMAT_NV12,
 242         DRM_FORMAT_NV16,
 243         DRM_FORMAT_NV24,
 244 };
 245
 246 static const uint32_t formats_234[] = {
 247         DRM_FORMAT_XRGB8888,
 248         DRM_FORMAT_ARGB8888,
 249         DRM_FORMAT_XBGR8888,
 250         DRM_FORMAT_ABGR8888,
 251         DRM_FORMAT_RGB888,
 252         DRM_FORMAT_BGR888,
 253         DRM_FORMAT_RGB565,
 254         DRM_FORMAT_BGR565,
 255 };
 256
 257 static const struct vop_scl_regs win_full_scl = {
 258         .cbcr_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 31),
 259         .cbcr_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 30),
 260         .cbcr_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 28),
 261         .cbcr_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 26),
 262         .cbcr_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 24),
 263         .yrgb_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 23),
 264         .yrgb_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 22),
 265         .yrgb_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 20),
 266         .yrgb_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 18),
 267         .yrgb_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 16),
 268         .line_load_mode = VOP_REG(WIN0_CTRL1, 0x1, 15),
 269         .cbcr_axi_gather_num = VOP_REG(WIN0_CTRL1, 0x7, 12),
 270         .yrgb_axi_gather_num = VOP_REG(WIN0_CTRL1, 0xf, 8),
 271         .vsd_cbcr_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 7),
 272         .vsd_cbcr_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 6),
 273         .vsd_yrgb_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 5),
 274         .vsd_yrgb_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 4),
 275         .bic_coe_sel = VOP_REG(WIN0_CTRL1, 0x3, 2),
 276         .cbcr_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 1),
 277         .yrgb_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 0),
 278         .lb_mode = VOP_REG(WIN0_CTRL0, 0x7, 5),
 279         .scale_yrgb_x = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
 280         .scale_yrgb_y = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
 281         .scale_cbcr_x = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
 282         .scale_cbcr_y = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 16),
 283 };
 284
 285 static const struct vop_win_phy win01_data = {
 286         .scl = &win_full_scl,
 287         .data_formats = formats_01,
 288         .nformats = ARRAY_SIZE(formats_01),
 289         .enable = VOP_REG(WIN0_CTRL0, 0x1, 0),
 290         .format = VOP_REG(WIN0_CTRL0, 0x7, 1),
 291         .rb_swap = VOP_REG(WIN0_CTRL0, 0x1, 12),
 292         .act_info = VOP_REG(WIN0_ACT_INFO, 0x1fff1fff, 0),
 293         .dsp_info = VOP_REG(WIN0_DSP_INFO, 0x0fff0fff, 0),
 294         .dsp_st = VOP_REG(WIN0_DSP_ST, 0x1fff1fff, 0),
 295         .yrgb_mst = VOP_REG(WIN0_YRGB_MST, 0xffffffff, 0),
 296         .uv_mst = VOP_REG(WIN0_CBR_MST, 0xffffffff, 0),
 297         .yrgb_vir = VOP_REG(WIN0_VIR, 0x3fff, 0),
 298         .uv_vir = VOP_REG(WIN0_VIR, 0x3fff, 16),
 299         .src_alpha_ctl = VOP_REG(WIN0_SRC_ALPHA_CTRL, 0xff, 0),
 300         .dst_alpha_ctl = VOP_REG(WIN0_DST_ALPHA_CTRL, 0xff, 0),
 301 };
 302
 303 static const struct vop_win_phy win23_data = {
 304         .data_formats = formats_234,
 305         .nformats = ARRAY_SIZE(formats_234),
 306         .enable = VOP_REG(WIN2_CTRL0, 0x1, 0),
 307         .format = VOP_REG(WIN2_CTRL0, 0x7, 1),
 308         .rb_swap = VOP_REG(WIN2_CTRL0, 0x1, 12),
 309         .dsp_info = VOP_REG(WIN2_DSP_INFO0, 0x0fff0fff, 0),
 310         .dsp_st = VOP_REG(WIN2_DSP_ST0, 0x1fff1fff, 0),
 311         .yrgb_mst = VOP_REG(WIN2_MST0, 0xffffffff, 0),
 312         .yrgb_vir = VOP_REG(WIN2_VIR0_1, 0x1fff, 0),
 313         .src_alpha_ctl = VOP_REG(WIN2_SRC_ALPHA_CTRL, 0xff, 0),
 314         .dst_alpha_ctl = VOP_REG(WIN2_DST_ALPHA_CTRL, 0xff, 0),
 315 };
 316
 317 static const struct vop_ctrl ctrl_data = {
 318         .standby = VOP_REG(SYS_CTRL, 0x1, 22),
 319         .gate_en = VOP_REG(SYS_CTRL, 0x1, 23),
 320         .mmu_en = VOP_REG(SYS_CTRL, 0x1, 20),
 321         .rgb_en = VOP_REG(SYS_CTRL, 0x1, 12),
 322         .hdmi_en = VOP_REG(SYS_CTRL, 0x1, 13),
 323         .edp_en = VOP_REG(SYS_CTRL, 0x1, 14),
 324         .mipi_en = VOP_REG(SYS_CTRL, 0x1, 15),
 325         .dither_down = VOP_REG(DSP_CTRL1, 0xf, 1),
 326         .dither_up = VOP_REG(DSP_CTRL1, 0x1, 6),
 327         .data_blank = VOP_REG(DSP_CTRL0, 0x1, 19),
 328         .out_mode = VOP_REG(DSP_CTRL0, 0xf, 0),
 329         .pin_pol = VOP_REG(DSP_CTRL0, 0xf, 4),
 330         .htotal_pw = VOP_REG(DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 331         .hact_st_end = VOP_REG(DSP_HACT_ST_END, 0x1fff1fff, 0),
 332         .vtotal_pw = VOP_REG(DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 333         .vact_st_end = VOP_REG(DSP_VACT_ST_END, 0x1fff1fff, 0),
 334         .hpost_st_end = VOP_REG(POST_DSP_HACT_INFO, 0x1fff1fff, 0),
 335         .vpost_st_end = VOP_REG(POST_DSP_VACT_INFO, 0x1fff1fff, 0),
 336 };
 337
 338 static const struct vop_reg_data vop_init_reg_table[] = {
 339         {SYS_CTRL, 0x00c00000},
 340         {DSP_CTRL0, 0x00000000},
 341         {WIN0_CTRL0, 0x00000080},
 342         {WIN1_CTRL0, 0x00000080},
 343         /* TODO: Win2/3 support multiple area function, but we haven't found
 344          * a suitable way to use it yet, so let's just use them as other windows
 345          * with only area 0 enabled.
 346          */
 347         {WIN2_CTRL0, 0x00000010},
 348         {WIN3_CTRL0, 0x00000010},
 349 };
 350
 351 /*
 352  * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
 353  * special support to get alpha blending working.  For now, just use overlay
 354  * window 3 for the drm cursor.
 355  *
 356  */
 357 static const struct vop_win_data rk3288_vop_win_data[] = {
 358         { .base = 0x00, .phy = &win01_data, .type = DRM_PLANE_TYPE_PRIMARY },
 359         { .base = 0x40, .phy = &win01_data, .type = DRM_PLANE_TYPE_OVERLAY },
 360         { .base = 0x00, .phy = &win23_data, .type = DRM_PLANE_TYPE_OVERLAY },
 361         { .base = 0x50, .phy = &win23_data, .type = DRM_PLANE_TYPE_CURSOR },
 362 };
 363
 364 static const struct vop_data rk3288_vop = {
 365         .init_table = vop_init_reg_table,
 366         .table_size = ARRAY_SIZE(vop_init_reg_table),
 367         .ctrl = &ctrl_data,
 368         .win = rk3288_vop_win_data,
 369         .win_size = ARRAY_SIZE(rk3288_vop_win_data),
 370 };
 371
 372 static const struct of_device_id vop_driver_dt_match[] = {
 373         { .compatible = "rockchip,rk3288-vop",
 374           .data = &rk3288_vop },
 375         {},
 376 };
 377 MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
 378
 379 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 380 {
 381         writel(v, vop->regs + offset);
 382         vop->regsbak[offset >> 2] = v;
 383 }
 384
 385 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 386 {
 387         return readl(vop->regs + offset);
 388 }
 389
 390 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 391                                     const struct vop_reg *reg)
 392 {
 393         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 394 }
 395
 396 static inline void vop_cfg_done(struct vop *vop)
 397 {
 398         writel(0x01, vop->regs + REG_CFG_DONE);
 399 }
 400
 401 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 402                                   uint32_t mask, uint32_t v)
 403 {
 404         if (mask) {
 405                 uint32_t cached_val = vop->regsbak[offset >> 2];
 406
 407                 cached_val = (cached_val & ~mask) | v;
 408                 writel(cached_val, vop->regs + offset);
 409                 vop->regsbak[offset >> 2] = cached_val;
 410         }
 411 }
 412
 413 static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset,
 414                                           uint32_t mask, uint32_t v)
 415 {
 416         if (mask) {
 417                 uint32_t cached_val = vop->regsbak[offset >> 2];
 418
 419                 cached_val = (cached_val & ~mask) | v;
 420                 writel_relaxed(cached_val, vop->regs + offset);
 421                 vop->regsbak[offset >> 2] = cached_val;
 422         }
 423 }
 424
 425 static bool has_rb_swapped(uint32_t format)
 426 {
 427         switch (format) {
 428         case DRM_FORMAT_XBGR8888:
 429         case DRM_FORMAT_ABGR8888:
 430         case DRM_FORMAT_BGR888:
 431         case DRM_FORMAT_BGR565:
 432                 return true;
 433         default:
 434                 return false;
 435         }
 436 }
 437
 438 static enum vop_data_format vop_convert_format(uint32_t format)
 439 {
 440         switch (format) {
 441         case DRM_FORMAT_XRGB8888:
 442         case DRM_FORMAT_ARGB8888:
 443         case DRM_FORMAT_XBGR8888:
 444         case DRM_FORMAT_ABGR8888:
 445                 return VOP_FMT_ARGB8888;
 446         case DRM_FORMAT_RGB888:
 447         case DRM_FORMAT_BGR888:
 448                 return VOP_FMT_RGB888;
 449         case DRM_FORMAT_RGB565:
 450         case DRM_FORMAT_BGR565:
 451                 return VOP_FMT_RGB565;
 452         case DRM_FORMAT_NV12:
 453                 return VOP_FMT_YUV420SP;
 454         case DRM_FORMAT_NV16:
 455                 return VOP_FMT_YUV422SP;
 456         case DRM_FORMAT_NV24:
 457                 return VOP_FMT_YUV444SP;
 458         default:
 459                 DRM_ERROR("unsupport format[%08x]\n", format);
 460                 return -EINVAL;
 461         }
 462 }
 463
 464 static bool is_yuv_support(uint32_t format)
 465 {
 466         switch (format) {
 467         case DRM_FORMAT_NV12:
 468         case DRM_FORMAT_NV16:
 469         case DRM_FORMAT_NV24:
 470                 return true;
 471         default:
 472                 return false;
 473         }
 474 }
 475
 476 static bool is_alpha_support(uint32_t format)
 477 {
 478         switch (format) {
 479         case DRM_FORMAT_ARGB8888:
 480         case DRM_FORMAT_ABGR8888:
 481                 return true;
 482         default:
 483                 return false;
 484         }
 485 }
 486
 487 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 488                                   uint32_t dst, bool is_horizontal,
 489                                   int vsu_mode, int *vskiplines)
 490 {
 491         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 492
 493         if (is_horizontal) {
 494                 if (mode == SCALE_UP)
 495                         val = GET_SCL_FT_BIC(src, dst);
 496                 else if (mode == SCALE_DOWN)
 497                         val = GET_SCL_FT_BILI_DN(src, dst);
 498         } else {
 499                 if (mode == SCALE_UP) {
 500                         if (vsu_mode == SCALE_UP_BIL)
 501                                 val = GET_SCL_FT_BILI_UP(src, dst);
 502                         else
 503                                 val = GET_SCL_FT_BIC(src, dst);
 504                 } else if (mode == SCALE_DOWN) {
 505                         if (vskiplines) {
 506                                 *vskiplines = scl_get_vskiplines(src, dst);
 507                                 val = scl_get_bili_dn_vskip(src, dst,
 508                                                             *vskiplines);
 509                         } else {
 510                                 val = GET_SCL_FT_BILI_DN(src, dst);
 511                         }
 512                 }
 513         }
 514
 515         return val;
 516 }
 517
 518 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
 519                              uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 520                              uint32_t dst_h, uint32_t pixel_format)
 521 {
 522         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 523         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 524         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 525         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 526         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 527         bool is_yuv = is_yuv_support(pixel_format);
 528         uint16_t cbcr_src_w = src_w / hsub;
 529         uint16_t cbcr_src_h = src_h / vsub;
 530         uint16_t vsu_mode;
 531         uint16_t lb_mode;
 532         uint32_t val;
 533         int vskiplines;
 534
 535         if (dst_w > 3840) {
 536                 DRM_ERROR("Maximum destination width (3840) exceeded\n");
 537                 return;
 538         }
 539
 540         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 541         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 542
 543         if (is_yuv) {
 544                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 545                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 546                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 547                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 548                 else
 549                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 550         } else {
 551                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 552                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 553                 else
 554                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 555         }
 556
 557         VOP_SCL_SET(vop, win, lb_mode, lb_mode);
 558         if (lb_mode == LB_RGB_3840X2) {
 559                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 560                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 561                         return;
 562                 }
 563                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 564                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 565                         return;
 566                 }
 567                 vsu_mode = SCALE_UP_BIL;
 568         } else if (lb_mode == LB_RGB_2560X4) {
 569                 vsu_mode = SCALE_UP_BIL;
 570         } else {
 571                 vsu_mode = SCALE_UP_BIC;
 572         }
 573
 574         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 575                                 true, 0, NULL);
 576         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 577         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 578                                 false, vsu_mode, &vskiplines);
 579         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 580
 581         VOP_SCL_SET(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 582         VOP_SCL_SET(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 583
 584         VOP_SCL_SET(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 585         VOP_SCL_SET(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 586         VOP_SCL_SET(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 587         VOP_SCL_SET(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 588         VOP_SCL_SET(vop, win, yrgb_vsu_mode, vsu_mode);
 589         if (is_yuv) {
 590                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 591                                         dst_w, true, 0, NULL);
 592                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 593                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 594                                         dst_h, false, vsu_mode, &vskiplines);
 595                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 596
 597                 VOP_SCL_SET(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 598                 VOP_SCL_SET(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 599                 VOP_SCL_SET(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 600                 VOP_SCL_SET(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 601                 VOP_SCL_SET(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 602                 VOP_SCL_SET(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 603                 VOP_SCL_SET(vop, win, cbcr_vsu_mode, vsu_mode);
 604         }
 605 }
 606
 607 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 608 {
 609         unsigned long flags;
 610
 611         if (WARN_ON(!vop->is_enabled))
 612                 return;
 613
 614         spin_lock_irqsave(&vop->irq_lock, flags);
 615
 616         vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK,
 617                        DSP_HOLD_VALID_INTR_EN(1));
 618
 619         spin_unlock_irqrestore(&vop->irq_lock, flags);
 620 }
 621
 622 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 623 {
 624         unsigned long flags;
 625
 626         if (WARN_ON(!vop->is_enabled))
 627                 return;
 628
 629         spin_lock_irqsave(&vop->irq_lock, flags);
 630
 631         vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK,
 632                        DSP_HOLD_VALID_INTR_EN(0));
 633
 634         spin_unlock_irqrestore(&vop->irq_lock, flags);
 635 }
 636
 637 static void vop_enable(struct drm_crtc *crtc)
 638 {
 639         struct vop *vop = to_vop(crtc);
 640         int ret;
 641
 642         if (vop->is_enabled)
 643                 return;
 644
 645         ret = pm_runtime_get_sync(vop->dev);
 646         if (ret < 0) {
 647                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 648                 return;
 649         }
 650
 651         ret = clk_enable(vop->hclk);
 652         if (ret < 0) {
 653                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 654                 return;
 655         }
 656
 657         ret = clk_enable(vop->dclk);
 658         if (ret < 0) {
 659                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 660                 goto err_disable_hclk;
 661         }
 662
 663         ret = clk_enable(vop->aclk);
 664         if (ret < 0) {
 665                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 666                 goto err_disable_dclk;
 667         }
 668
 669         /*
 670          * Slave iommu shares power, irq and clock with vop.  It was associated
 671          * automatically with this master device via common driver code.
 672          * Now that we have enabled the clock we attach it to the shared drm
 673          * mapping.
 674          */
 675         ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
 676         if (ret) {
 677                 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
 678                 goto err_disable_aclk;
 679         }
 680
 681         memcpy(vop->regs, vop->regsbak, vop->len);
 682         /*
 683          * At here, vop clock & iommu is enable, R/W vop regs would be safe.
 684          */
 685         vop->is_enabled = true;
 686
 687         spin_lock(&vop->reg_lock);
 688
 689         VOP_CTRL_SET(vop, standby, 0);
 690
 691         spin_unlock(&vop->reg_lock);
 692
 693         enable_irq(vop->irq);
 694
 695         drm_crtc_vblank_on(crtc);
 696
 697         return;
 698
 699 err_disable_aclk:
 700         clk_disable(vop->aclk);
 701 err_disable_dclk:
 702         clk_disable(vop->dclk);
 703 err_disable_hclk:
 704         clk_disable(vop->hclk);
 705 }
 706
 707 static void vop_crtc_disable(struct drm_crtc *crtc)
 708 {
 709         struct vop *vop = to_vop(crtc);
 710
 711         if (!vop->is_enabled)
 712                 return;
 713
 714         drm_crtc_vblank_off(crtc);
 715
 716         /*
 717          * Vop standby will take effect at end of current frame,
 718          * if dsp hold valid irq happen, it means standby complete.
 719          *
 720          * we must wait standby complete when we want to disable aclk,
 721          * if not, memory bus maybe dead.
 722          */
 723         reinit_completion(&vop->dsp_hold_completion);
 724         vop_dsp_hold_valid_irq_enable(vop);
 725
 726         spin_lock(&vop->reg_lock);
 727
 728         VOP_CTRL_SET(vop, standby, 1);
 729
 730         spin_unlock(&vop->reg_lock);
 731
 732         wait_for_completion(&vop->dsp_hold_completion);
 733
 734         vop_dsp_hold_valid_irq_disable(vop);
 735
 736         disable_irq(vop->irq);
 737
 738         vop->is_enabled = false;
 739
 740         /*
 741          * vop standby complete, so iommu detach is safe.
 742          */
 743         rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 744
 745         clk_disable(vop->dclk);
 746         clk_disable(vop->aclk);
 747         clk_disable(vop->hclk);
 748         pm_runtime_put(vop->dev);
 749 }
 750
 751 static void vop_plane_destroy(struct drm_plane *plane)
 752 {
 753         drm_plane_cleanup(plane);
 754 }
 755
 756 static int vop_plane_atomic_check(struct drm_plane *plane,
 757                            struct drm_plane_state *state)
 758 {
 759         struct drm_crtc *crtc = state->crtc;
 760         struct drm_framebuffer *fb = state->fb;
 761         struct vop_win *vop_win = to_vop_win(plane);
 762         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 763         const struct vop_win_data *win = vop_win->data;
 764         bool visible;
 765         int ret;
 766         struct drm_rect *dest = &vop_plane_state->dest;
 767         struct drm_rect *src = &vop_plane_state->src;
 768         struct drm_rect clip;
 769         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 770                                         DRM_PLANE_HELPER_NO_SCALING;
 771         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 772                                         DRM_PLANE_HELPER_NO_SCALING;
 773
 774         crtc = crtc ? crtc : plane->state->crtc;
 775         /*
 776          * Both crtc or plane->state->crtc can be null.
 777          */
 778         if (!crtc || !fb)
 779                 goto out_disable;
 780         src->x1 = state->src_x;
 781         src->y1 = state->src_y;
 782         src->x2 = state->src_x + state->src_w;
 783         src->y2 = state->src_y + state->src_h;
 784         dest->x1 = state->crtc_x;
 785         dest->y1 = state->crtc_y;
 786         dest->x2 = state->crtc_x + state->crtc_w;
 787         dest->y2 = state->crtc_y + state->crtc_h;
 788
 789         clip.x1 = 0;
 790         clip.y1 = 0;
 791         clip.x2 = crtc->mode.hdisplay;
 792         clip.y2 = crtc->mode.vdisplay;
 793
 794         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
 795                                             src, dest, &clip,
 796                                             min_scale,
 797                                             max_scale,
 798                                             true, true, &visible);
 799         if (ret)
 800                 return ret;
 801
 802         if (!visible)
 803                 goto out_disable;
 804
 805         vop_plane_state->format = vop_convert_format(fb->pixel_format);
 806         if (vop_plane_state->format < 0)
 807                 return vop_plane_state->format;
 808
 809         /*
 810          * Src.x1 can be odd when do clip, but yuv plane start point
 811          * need align with 2 pixel.
 812          */
 813         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
 814                 return -EINVAL;
 815
 816         vop_plane_state->enable = true;
 817
 818         return 0;
 819
 820 out_disable:
 821         vop_plane_state->enable = false;
 822         return 0;
 823 }
 824
 825 static void vop_plane_atomic_disable(struct drm_plane *plane,
 826                                      struct drm_plane_state *old_state)
 827 {
 828         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
 829         struct vop_win *vop_win = to_vop_win(plane);
 830         const struct vop_win_data *win = vop_win->data;
 831         struct vop *vop = to_vop(old_state->crtc);
 832
 833         if (!old_state->crtc)
 834                 return;
 835
 836         spin_lock(&vop->reg_lock);
 837
 838         VOP_WIN_SET(vop, win, enable, 0);
 839
 840         spin_unlock(&vop->reg_lock);
 841
 842         vop_plane_state->enable = false;
 843 }
 844
 845 static void vop_plane_atomic_update(struct drm_plane *plane,
 846                 struct drm_plane_state *old_state)
 847 {
 848         struct drm_plane_state *state = plane->state;
 849         struct drm_crtc *crtc = state->crtc;
 850         struct vop_win *vop_win = to_vop_win(plane);
 851         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 852         const struct vop_win_data *win = vop_win->data;
 853         struct vop *vop = to_vop(state->crtc);
 854         struct drm_framebuffer *fb = state->fb;
 855         unsigned int actual_w, actual_h;
 856         unsigned int dsp_stx, dsp_sty;
 857         uint32_t act_info, dsp_info, dsp_st;
 858         struct drm_rect *src = &vop_plane_state->src;
 859         struct drm_rect *dest = &vop_plane_state->dest;
 860         struct drm_gem_object *obj, *uv_obj;
 861         struct rockchip_gem_object *rk_obj, *rk_uv_obj;
 862         unsigned long offset;
 863         dma_addr_t dma_addr;
 864         uint32_t val;
 865         bool rb_swap;
 866
 867         /*
 868          * can't update plane when vop is disabled.
 869          */
 870         if (!crtc)
 871                 return;
 872
 873         if (WARN_ON(!vop->is_enabled))
 874                 return;
 875
 876         if (!vop_plane_state->enable) {
 877                 vop_plane_atomic_disable(plane, old_state);
 878                 return;
 879         }
 880
 881         obj = rockchip_fb_get_gem_obj(fb, 0);
 882         rk_obj = to_rockchip_obj(obj);
 883
 884         actual_w = drm_rect_width(src) >> 16;
 885         actual_h = drm_rect_height(src) >> 16;
 886         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
 887
 888         dsp_info = (drm_rect_height(dest) - 1) << 16;
 889         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
 890
 891         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
 892         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 893         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
 894
 895         offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
 896         offset += (src->y1 >> 16) * fb->pitches[0];
 897         vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
 898
 899         spin_lock(&vop->reg_lock);
 900
 901         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
 902         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
 903         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
 904         if (is_yuv_support(fb->pixel_format)) {
 905                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
 906                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
 907                 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
 908
 909                 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
 910                 rk_uv_obj = to_rockchip_obj(uv_obj);
 911
 912                 offset = (src->x1 >> 16) * bpp / hsub;
 913                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 914
 915                 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
 916                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
 917                 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
 918         }
 919
 920         if (win->phy->scl)
 921                 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
 922                                     drm_rect_width(dest), drm_rect_height(dest),
 923                                     fb->pixel_format);
 924
 925         VOP_WIN_SET(vop, win, act_info, act_info);
 926         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
 927         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
 928
 929         rb_swap = has_rb_swapped(fb->pixel_format);
 930         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
 931
 932         if (is_alpha_support(fb->pixel_format)) {
 933                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
 934                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
 935                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
 936                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
 937                         SRC_BLEND_M0(ALPHA_PER_PIX) |
 938                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
 939                         SRC_FACTOR_M0(ALPHA_ONE);
 940                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
 941         } else {
 942                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
 943         }
 944
 945         VOP_WIN_SET(vop, win, enable, 1);
 946         spin_unlock(&vop->reg_lock);
 947 }
 948
 949 static const struct drm_plane_helper_funcs plane_helper_funcs = {
 950         .atomic_check = vop_plane_atomic_check,
 951         .atomic_update = vop_plane_atomic_update,
 952         .atomic_disable = vop_plane_atomic_disable,
 953 };
 954
 955 void vop_atomic_plane_reset(struct drm_plane *plane)
 956 {
 957         struct vop_plane_state *vop_plane_state =
 958                                         to_vop_plane_state(plane->state);
 959
 960         if (plane->state && plane->state->fb)
 961                 drm_framebuffer_unreference(plane->state->fb);
 962
 963         kfree(vop_plane_state);
 964         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
 965         if (!vop_plane_state)
 966                 return;
 967
 968         plane->state = &vop_plane_state->base;
 969         plane->state->plane = plane;
 970 }
 971
 972 struct drm_plane_state *
 973 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
 974 {
 975         struct vop_plane_state *old_vop_plane_state;
 976         struct vop_plane_state *vop_plane_state;
 977
 978         if (WARN_ON(!plane->state))
 979                 return NULL;
 980
 981         old_vop_plane_state = to_vop_plane_state(plane->state);
 982         vop_plane_state = kmemdup(old_vop_plane_state,
 983                                   sizeof(*vop_plane_state), GFP_KERNEL);
 984         if (!vop_plane_state)
 985                 return NULL;
 986
 987         __drm_atomic_helper_plane_duplicate_state(plane,
 988                                                   &vop_plane_state->base);
 989
 990         return &vop_plane_state->base;
 991 }
 992
 993 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
 994                                            struct drm_plane_state *state)
 995 {
 996         struct vop_plane_state *vop_state = to_vop_plane_state(state);
 997
 998         __drm_atomic_helper_plane_destroy_state(plane, state);
 999
1000         kfree(vop_state);
1001 }
1002
1003 static const struct drm_plane_funcs vop_plane_funcs = {
1004         .update_plane   = drm_atomic_helper_update_plane,
1005         .disable_plane  = drm_atomic_helper_disable_plane,
1006         .destroy = vop_plane_destroy,
1007         .reset = vop_atomic_plane_reset,
1008         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
1009         .atomic_destroy_state = vop_atomic_plane_destroy_state,
1010 };
1011
1012 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
1013                                   int connector_type,
1014                                   int out_mode)
1015 {
1016         struct vop *vop = to_vop(crtc);
1017
1018         if (WARN_ON(!vop->is_enabled))
1019                 return -EINVAL;
1020
1021         switch (connector_type) {
1022         case DRM_MODE_CONNECTOR_LVDS:
1023                 VOP_CTRL_SET(vop, rgb_en, 1);
1024                 break;
1025         case DRM_MODE_CONNECTOR_eDP:
1026                 VOP_CTRL_SET(vop, edp_en, 1);
1027                 break;
1028         case DRM_MODE_CONNECTOR_HDMIA:
1029                 VOP_CTRL_SET(vop, hdmi_en, 1);
1030                 break;
1031         default:
1032                 DRM_ERROR("unsupport connector_type[%d]\n", connector_type);
1033                 return -EINVAL;
1034         };
1035         VOP_CTRL_SET(vop, out_mode, out_mode);
1036
1037         return 0;
1038 }
1039 EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
1040
1041 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1042 {
1043         struct vop *vop = to_vop(crtc);
1044         unsigned long flags;
1045
1046         if (WARN_ON(!vop->is_enabled))
1047                 return -EPERM;
1048
1049         spin_lock_irqsave(&vop->irq_lock, flags);
1050
1051         vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(1));
1052
1053         spin_unlock_irqrestore(&vop->irq_lock, flags);
1054
1055         return 0;
1056 }
1057
1058 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1059 {
1060         struct vop *vop = to_vop(crtc);
1061         unsigned long flags;
1062
1063         if (WARN_ON(!vop->is_enabled))
1064                 return;
1065
1066         spin_lock_irqsave(&vop->irq_lock, flags);
1067         vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(0));
1068         spin_unlock_irqrestore(&vop->irq_lock, flags);
1069 }
1070
1071 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
1072 {
1073         struct vop *vop = to_vop(crtc);
1074
1075         reinit_completion(&vop->wait_update_complete);
1076         WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
1077 }
1078
1079 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1080         .enable_vblank = vop_crtc_enable_vblank,
1081         .disable_vblank = vop_crtc_disable_vblank,
1082         .wait_for_update = vop_crtc_wait_for_update,
1083 };
1084
1085 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1086                                 const struct drm_display_mode *mode,
1087                                 struct drm_display_mode *adjusted_mode)
1088 {
1089         if (adjusted_mode->htotal == 0 || adjusted_mode->vtotal == 0)
1090                 return false;
1091
1092         return true;
1093 }
1094
1095 static void vop_crtc_enable(struct drm_crtc *crtc)
1096 {
1097         struct vop *vop = to_vop(crtc);
1098         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1099         u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1100         u16 hdisplay = adjusted_mode->hdisplay;
1101         u16 htotal = adjusted_mode->htotal;
1102         u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1103         u16 hact_end = hact_st + hdisplay;
1104         u16 vdisplay = adjusted_mode->vdisplay;
1105         u16 vtotal = adjusted_mode->vtotal;
1106         u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1107         u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1108         u16 vact_end = vact_st + vdisplay;
1109         uint32_t val;
1110
1111         vop_enable(crtc);
1112         /*
1113          * If dclk rate is zero, mean that scanout is stop,
1114          * we don't need wait any more.
1115          */
1116         if (clk_get_rate(vop->dclk)) {
1117                 /*
1118                  * Rk3288 vop timing register is immediately, when configure
1119                  * display timing on display time, may cause tearing.
1120                  *
1121                  * Vop standby will take effect at end of current frame,
1122                  * if dsp hold valid irq happen, it means standby complete.
1123                  *
1124                  * mode set:
1125                  *    standby and wait complete --> |----
1126                  *                                  | display time
1127                  *                                  |----
1128                  *                                  |---> dsp hold irq
1129                  *     configure display timing --> |
1130                  *         standby exit             |
1131                  *                                  | new frame start.
1132                  */
1133
1134                 reinit_completion(&vop->dsp_hold_completion);
1135                 vop_dsp_hold_valid_irq_enable(vop);
1136
1137                 spin_lock(&vop->reg_lock);
1138
1139                 VOP_CTRL_SET(vop, standby, 1);
1140
1141                 spin_unlock(&vop->reg_lock);
1142
1143                 wait_for_completion(&vop->dsp_hold_completion);
1144
1145                 vop_dsp_hold_valid_irq_disable(vop);
1146         }
1147
1148         val = 0x8;
1149         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
1150         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
1151         VOP_CTRL_SET(vop, pin_pol, val);
1152
1153         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1154         val = hact_st << 16;
1155         val |= hact_end;
1156         VOP_CTRL_SET(vop, hact_st_end, val);
1157         VOP_CTRL_SET(vop, hpost_st_end, val);
1158
1159         VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
1160         val = vact_st << 16;
1161         val |= vact_end;
1162         VOP_CTRL_SET(vop, vact_st_end, val);
1163         VOP_CTRL_SET(vop, vpost_st_end, val);
1164
1165         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1166
1167         VOP_CTRL_SET(vop, standby, 0);
1168 }
1169
1170 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1171                                   struct drm_crtc_state *old_crtc_state)
1172 {
1173         struct vop *vop = to_vop(crtc);
1174
1175         if (WARN_ON(!vop->is_enabled))
1176                 return;
1177
1178         spin_lock(&vop->reg_lock);
1179
1180         vop_cfg_done(vop);
1181
1182         spin_unlock(&vop->reg_lock);
1183 }
1184
1185 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1186                                   struct drm_crtc_state *old_crtc_state)
1187 {
1188         struct vop *vop = to_vop(crtc);
1189
1190         if (crtc->state->event) {
1191                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1192
1193                 vop->event = crtc->state->event;
1194                 crtc->state->event = NULL;
1195         }
1196 }
1197
1198 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1199         .enable = vop_crtc_enable,
1200         .disable = vop_crtc_disable,
1201         .mode_fixup = vop_crtc_mode_fixup,
1202         .atomic_flush = vop_crtc_atomic_flush,
1203         .atomic_begin = vop_crtc_atomic_begin,
1204 };
1205
1206 static void vop_crtc_destroy(struct drm_crtc *crtc)
1207 {
1208         drm_crtc_cleanup(crtc);
1209 }
1210
1211 static const struct drm_crtc_funcs vop_crtc_funcs = {
1212         .set_config = drm_atomic_helper_set_config,
1213         .page_flip = drm_atomic_helper_page_flip,
1214         .destroy = vop_crtc_destroy,
1215         .reset = drm_atomic_helper_crtc_reset,
1216         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
1217         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
1218 };
1219
1220 static bool vop_win_pending_is_complete(struct vop_win *vop_win)
1221 {
1222         struct drm_plane *plane = &vop_win->base;
1223         struct vop_plane_state *state = to_vop_plane_state(plane->state);
1224         dma_addr_t yrgb_mst;
1225
1226         if (!state->enable)
1227                 return VOP_WIN_GET(vop_win->vop, vop_win->data, enable) == 0;
1228
1229         yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data);
1230
1231         return yrgb_mst == state->yrgb_mst;
1232 }
1233
1234 static void vop_handle_vblank(struct vop *vop)
1235 {
1236         struct drm_device *drm = vop->drm_dev;
1237         struct drm_crtc *crtc = &vop->crtc;
1238         unsigned long flags;
1239         int i;
1240
1241         for (i = 0; i < vop->data->win_size; i++) {
1242                 if (!vop_win_pending_is_complete(&vop->win[i]))
1243                         return;
1244         }
1245
1246         if (vop->event) {
1247                 spin_lock_irqsave(&drm->event_lock, flags);
1248
1249                 drm_crtc_send_vblank_event(crtc, vop->event);
1250                 drm_crtc_vblank_put(crtc);
1251                 vop->event = NULL;
1252
1253                 spin_unlock_irqrestore(&drm->event_lock, flags);
1254         }
1255         if (!completion_done(&vop->wait_update_complete))
1256                 complete(&vop->wait_update_complete);
1257 }
1258
1259 static irqreturn_t vop_isr(int irq, void *data)
1260 {
1261         struct vop *vop = data;
1262         struct drm_crtc *crtc = &vop->crtc;
1263         uint32_t intr0_reg, active_irqs;
1264         unsigned long flags;
1265         int ret = IRQ_NONE;
1266
1267         /*
1268          * INTR_CTRL0 register has interrupt status, enable and clear bits, we
1269          * must hold irq_lock to avoid a race with enable/disable_vblank().
1270         */
1271         spin_lock_irqsave(&vop->irq_lock, flags);
1272         intr0_reg = vop_readl(vop, INTR_CTRL0);
1273         active_irqs = intr0_reg & INTR_MASK;
1274         /* Clear all active interrupt sources */
1275         if (active_irqs)
1276                 vop_writel(vop, INTR_CTRL0,
1277                            intr0_reg | (active_irqs << INTR_CLR_SHIFT));
1278         spin_unlock_irqrestore(&vop->irq_lock, flags);
1279
1280         /* This is expected for vop iommu irqs, since the irq is shared */
1281         if (!active_irqs)
1282                 return IRQ_NONE;
1283
1284         if (active_irqs & DSP_HOLD_VALID_INTR) {
1285                 complete(&vop->dsp_hold_completion);
1286                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1287                 ret = IRQ_HANDLED;
1288         }
1289
1290         if (active_irqs & FS_INTR) {
1291                 drm_crtc_handle_vblank(crtc);
1292                 vop_handle_vblank(vop);
1293                 active_irqs &= ~FS_INTR;
1294                 ret = IRQ_HANDLED;
1295         }
1296
1297         /* Unhandled irqs are spurious. */
1298         if (active_irqs)
1299                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1300
1301         return ret;
1302 }
1303
1304 static int vop_create_crtc(struct vop *vop)
1305 {
1306         const struct vop_data *vop_data = vop->data;
1307         struct device *dev = vop->dev;
1308         struct drm_device *drm_dev = vop->drm_dev;
1309         struct drm_plane *primary = NULL, *cursor = NULL, *plane;
1310         struct drm_crtc *crtc = &vop->crtc;
1311         struct device_node *port;
1312         int ret;
1313         int i;
1314
1315         /*
1316          * Create drm_plane for primary and cursor planes first, since we need
1317          * to pass them to drm_crtc_init_with_planes, which sets the
1318          * "possible_crtcs" to the newly initialized crtc.
1319          */
1320         for (i = 0; i < vop_data->win_size; i++) {
1321                 struct vop_win *vop_win = &vop->win[i];
1322                 const struct vop_win_data *win_data = vop_win->data;
1323
1324                 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1325                     win_data->type != DRM_PLANE_TYPE_CURSOR)
1326                         continue;
1327
1328                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1329                                                0, &vop_plane_funcs,
1330                                                win_data->phy->data_formats,
1331                                                win_data->phy->nformats,
1332                                                win_data->type, NULL);
1333                 if (ret) {
1334                         DRM_ERROR("failed to initialize plane\n");
1335                         goto err_cleanup_planes;
1336                 }
1337
1338                 plane = &vop_win->base;
1339                 drm_plane_helper_add(plane, &plane_helper_funcs);
1340                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1341                         primary = plane;
1342                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1343                         cursor = plane;
1344         }
1345
1346         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1347                                         &vop_crtc_funcs, NULL);
1348         if (ret)
1349                 return ret;
1350
1351         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1352
1353         /*
1354          * Create drm_planes for overlay windows with possible_crtcs restricted
1355          * to the newly created crtc.
1356          */
1357         for (i = 0; i < vop_data->win_size; i++) {
1358                 struct vop_win *vop_win = &vop->win[i];
1359                 const struct vop_win_data *win_data = vop_win->data;
1360                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1361
1362                 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1363                         continue;
1364
1365                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1366                                                possible_crtcs,
1367                                                &vop_plane_funcs,
1368                                                win_data->phy->data_formats,
1369                                                win_data->phy->nformats,
1370                                                win_data->type, NULL);
1371                 if (ret) {
1372                         DRM_ERROR("failed to initialize overlay plane\n");
1373                         goto err_cleanup_crtc;
1374                 }
1375                 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1376         }
1377
1378         port = of_get_child_by_name(dev->of_node, "port");
1379         if (!port) {
1380                 DRM_ERROR("no port node found in %s\n",
1381                           dev->of_node->full_name);
1382                 goto err_cleanup_crtc;
1383         }
1384
1385         init_completion(&vop->dsp_hold_completion);
1386         init_completion(&vop->wait_update_complete);
1387         crtc->port = port;
1388         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1389
1390         return 0;
1391
1392 err_cleanup_crtc:
1393         drm_crtc_cleanup(crtc);
1394 err_cleanup_planes:
1395         list_for_each_entry(plane, &drm_dev->mode_config.plane_list, head)
1396                 drm_plane_cleanup(plane);
1397         return ret;
1398 }
1399
1400 static void vop_destroy_crtc(struct vop *vop)
1401 {
1402         struct drm_crtc *crtc = &vop->crtc;
1403
1404         rockchip_unregister_crtc_funcs(crtc);
1405         of_node_put(crtc->port);
1406         drm_crtc_cleanup(crtc);
1407 }
1408
1409 static int vop_initial(struct vop *vop)
1410 {
1411         const struct vop_data *vop_data = vop->data;
1412         const struct vop_reg_data *init_table = vop_data->init_table;
1413         struct reset_control *ahb_rst;
1414         int i, ret;
1415
1416         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1417         if (IS_ERR(vop->hclk)) {
1418                 dev_err(vop->dev, "failed to get hclk source\n");
1419                 return PTR_ERR(vop->hclk);
1420         }
1421         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1422         if (IS_ERR(vop->aclk)) {
1423                 dev_err(vop->dev, "failed to get aclk source\n");
1424                 return PTR_ERR(vop->aclk);
1425         }
1426         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1427         if (IS_ERR(vop->dclk)) {
1428                 dev_err(vop->dev, "failed to get dclk source\n");
1429                 return PTR_ERR(vop->dclk);
1430         }
1431
1432         ret = clk_prepare(vop->dclk);
1433         if (ret < 0) {
1434                 dev_err(vop->dev, "failed to prepare dclk\n");
1435                 return ret;
1436         }
1437
1438         /* Enable both the hclk and aclk to setup the vop */
1439         ret = clk_prepare_enable(vop->hclk);
1440         if (ret < 0) {
1441                 dev_err(vop->dev, "failed to prepare/enable hclk\n");
1442                 goto err_unprepare_dclk;
1443         }
1444
1445         ret = clk_prepare_enable(vop->aclk);
1446         if (ret < 0) {
1447                 dev_err(vop->dev, "failed to prepare/enable aclk\n");
1448                 goto err_disable_hclk;
1449         }
1450
1451         /*
1452          * do hclk_reset, reset all vop registers.
1453          */
1454         ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1455         if (IS_ERR(ahb_rst)) {
1456                 dev_err(vop->dev, "failed to get ahb reset\n");
1457                 ret = PTR_ERR(ahb_rst);
1458                 goto err_disable_aclk;
1459         }
1460         reset_control_assert(ahb_rst);
1461         usleep_range(10, 20);
1462         reset_control_deassert(ahb_rst);
1463
1464         memcpy(vop->regsbak, vop->regs, vop->len);
1465
1466         for (i = 0; i < vop_data->table_size; i++)
1467                 vop_writel(vop, init_table[i].offset, init_table[i].value);
1468
1469         for (i = 0; i < vop_data->win_size; i++) {
1470                 const struct vop_win_data *win = &vop_data->win[i];
1471
1472                 VOP_WIN_SET(vop, win, enable, 0);
1473         }
1474
1475         vop_cfg_done(vop);
1476
1477         /*
1478          * do dclk_reset, let all config take affect.
1479          */
1480         vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1481         if (IS_ERR(vop->dclk_rst)) {
1482                 dev_err(vop->dev, "failed to get dclk reset\n");
1483                 ret = PTR_ERR(vop->dclk_rst);
1484                 goto err_disable_aclk;
1485         }
1486         reset_control_assert(vop->dclk_rst);
1487         usleep_range(10, 20);
1488         reset_control_deassert(vop->dclk_rst);
1489
1490         clk_disable(vop->hclk);
1491         clk_disable(vop->aclk);
1492
1493         vop->is_enabled = false;
1494
1495         return 0;
1496
1497 err_disable_aclk:
1498         clk_disable_unprepare(vop->aclk);
1499 err_disable_hclk:
1500         clk_disable_unprepare(vop->hclk);
1501 err_unprepare_dclk:
1502         clk_unprepare(vop->dclk);
1503         return ret;
1504 }
1505
1506 /*
1507  * Initialize the vop->win array elements.
1508  */
1509 static void vop_win_init(struct vop *vop)
1510 {
1511         const struct vop_data *vop_data = vop->data;
1512         unsigned int i;
1513
1514         for (i = 0; i < vop_data->win_size; i++) {
1515                 struct vop_win *vop_win = &vop->win[i];
1516                 const struct vop_win_data *win_data = &vop_data->win[i];
1517
1518                 vop_win->data = win_data;
1519                 vop_win->vop = vop;
1520         }
1521 }
1522
1523 static int vop_bind(struct device *dev, struct device *master, void *data)
1524 {
1525         struct platform_device *pdev = to_platform_device(dev);
1526         const struct of_device_id *of_id;
1527         const struct vop_data *vop_data;
1528         struct drm_device *drm_dev = data;
1529         struct vop *vop;
1530         struct resource *res;
1531         size_t alloc_size;
1532         int ret, irq;
1533
1534         of_id = of_match_device(vop_driver_dt_match, dev);
1535         vop_data = of_id->data;
1536         if (!vop_data)
1537                 return -ENODEV;
1538
1539         /* Allocate vop struct and its vop_win array */
1540         alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
1541         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1542         if (!vop)
1543                 return -ENOMEM;
1544
1545         vop->dev = dev;
1546         vop->data = vop_data;
1547         vop->drm_dev = drm_dev;
1548         dev_set_drvdata(dev, vop);
1549
1550         vop_win_init(vop);
1551
1552         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1553         vop->len = resource_size(res);
1554         vop->regs = devm_ioremap_resource(dev, res);
1555         if (IS_ERR(vop->regs))
1556                 return PTR_ERR(vop->regs);
1557
1558         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1559         if (!vop->regsbak)
1560                 return -ENOMEM;
1561
1562         ret = vop_initial(vop);
1563         if (ret < 0) {
1564                 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1565                 return ret;
1566         }
1567
1568         irq = platform_get_irq(pdev, 0);
1569         if (irq < 0) {
1570                 dev_err(dev, "cannot find irq for vop\n");
1571                 return irq;
1572         }
1573         vop->irq = (unsigned int)irq;
1574
1575         spin_lock_init(&vop->reg_lock);
1576         spin_lock_init(&vop->irq_lock);
1577
1578         mutex_init(&vop->vsync_mutex);
1579
1580         ret = devm_request_irq(dev, vop->irq, vop_isr,
1581                                IRQF_SHARED, dev_name(dev), vop);
1582         if (ret)
1583                 return ret;
1584
1585         /* IRQ is initially disabled; it gets enabled in power_on */
1586         disable_irq(vop->irq);
1587
1588         ret = vop_create_crtc(vop);
1589         if (ret)
1590                 return ret;
1591
1592         pm_runtime_enable(&pdev->dev);
1593         return 0;
1594 }
1595
1596 static void vop_unbind(struct device *dev, struct device *master, void *data)
1597 {
1598         struct vop *vop = dev_get_drvdata(dev);
1599
1600         pm_runtime_disable(dev);
1601         vop_destroy_crtc(vop);
1602 }
1603
1604 static const struct component_ops vop_component_ops = {
1605         .bind = vop_bind,
1606         .unbind = vop_unbind,
1607 };
1608
1609 static int vop_probe(struct platform_device *pdev)
1610 {
1611         struct device *dev = &pdev->dev;
1612
1613         if (!dev->of_node) {
1614                 dev_err(dev, "can't find vop devices\n");
1615                 return -ENODEV;
1616         }
1617
1618         return component_add(dev, &vop_component_ops);
1619 }
1620
1621 static int vop_remove(struct platform_device *pdev)
1622 {
1623         component_del(&pdev->dev, &vop_component_ops);
1624
1625         return 0;
1626 }
1627
1628 struct platform_driver vop_platform_driver = {
1629         .probe = vop_probe,
1630         .remove = vop_remove,
1631         .driver = {
1632                 .name = "rockchip-vop",
1633                 .owner = THIS_MODULE,
1634                 .of_match_table = of_match_ptr(vop_driver_dt_match),
1635         },
1636 };
1637
1638 module_platform_driver(vop_platform_driver);
1639
1640 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
1641 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
1642 MODULE_LICENSE("GPL v2");